CN1858751A - Method for printed circuit board power completeness simulation - Google Patents
Method for printed circuit board power completeness simulation Download PDFInfo
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- CN1858751A CN1858751A CN 200510110104 CN200510110104A CN1858751A CN 1858751 A CN1858751 A CN 1858751A CN 200510110104 CN200510110104 CN 200510110104 CN 200510110104 A CN200510110104 A CN 200510110104A CN 1858751 A CN1858751 A CN 1858751A
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Abstract
This invention discloses a method for emulating the integrated power supply of a PCB, in which, accurate PI emulation to a PCB is carried out by a device attribute provided by a third party theoretical plot and related power integrality emulation software and the first attribute related to the device models and parameters in the third theoretical plot is added to the second attribute of the same plot symbol, only the second attribute of the theoretical plot symbol is preserved in the net list generated in the theoretical plot, after an emulation tool is called into the list, related models and parameters are presented to related devices based on the first attribute included in the second attribute, then a net list is generated in related supply integrality emulation software, finally, the net list is modified to be replaced to models and parameters assigned in the third party theoretical plot for further compiling and emulation and the parameters assigned in the third party theoretical plot can be the parameter S library.
Description
Technical field
The present invention relates to electronic technology, particularly the printed circuit board power completeness simulation technology.
Background technology
Along with the development of infotech, electron device and people's life is more and more closer.PCB is a kind of important components in most electron devices.Along with the complexity day by day of electron device function and the raising of performance, the density of PCB and the frequency of its related device are all constantly soaring, and the various challenges that the high-speed and high-density PCB designing institute that the slip-stick artist faces brings also constantly increase.Remove signal integrity (SignalIntegrity is called for short " the SI ") problem that everybody knows, power supply integrality (Power Integrity is called for short " PI ") also is the hot issue of high-speed and high-density PCB.
With respect to signal integrity, PI is a kind of newer technology, and the stability problem that power supply is supplied with mainly is discussed, and it is considered to one of maximum at present challenge of high-speed and high-density PCB design.In High Speed System, power delivery system (Power Deliver System, be called for short " PDS ") on different frequency, the impedance operator difference, make PCB go up power plane with ground connection the voltage between flat being not quite similar everywhere of circuit board, thereby cause power supply discontinuous, the generation power supply noise, have influence on the power supply of chip, cause the logic error of chip.For example, when electric current passed through device power source pin inflow device or passes through pin inflow place, ground in moment, because the existence of device package inductance and power supply are supplied with the existence of inductance in the loop, will produce electric source disturbance and ground bullet noise, make the voltage of power supply power supply fluctuation occur.Can steady operation for system, require PDS in related frequency range, can or approach to provide electric current, PI problem that Here it is under the state of target impedance with target impedance.If can not solve the PI problem well, can have a strong impact on the operate as normal of system.In order to guarantee the correct operation of high speed device, the deviser should eliminate the fluctuation of this voltage, keeps the power distribution path of approaching target impedance.
Usually, the PI problem mainly solves by two approach: optimize the stack-design and the placement-and-routing of circuit board, and increase decoupling capacitance.Wherein, it is the most general increasing decoupling capacitance, and the most frequently used method.Decoupling capacitance has the effect of filtering, can eliminate noise and ground bullet noise that electric source disturbance produces, burning voltage.Popular says, the effect of decoupling capacitance be with unnecessary electrical power storage in capacitor, and when supply of electrical energy is not enough, the feedback power supply system.
When carrying out the emulation of frequency PCB, because system frequency is very high, be usually operated at the microwave section, therefore traditional circuit model also is not suitable for.In the frequency range of high frequency, circuit devcie can show some characteristics that it does not have when low frequency, can not represent with its original resistance, inductance or capacitance merely again, and this mainly is because the effect of reactance component parasitic parameter.For example, the equivalent electrical circuit of electric capacity when high frequency as shown in Figure 1.Equivalent electrical circuit shown in Figure 1 can artificial capacitor when high frequency circuit characteristic and explain its ghost effect, help the deviser to determine such as characteristics such as series resonance frequency, equivalent series inductance and transition functions.When high frequency, scattering parameter (Scattering parameter is called for short " S parameter ") can more in depth be understood ghost effect, is widely used for representing the characteristic of Microwave Net.The S parameter is typically expressed as the forward direction of a two-port system and reverse measurement result, has showed the various characteristics of device, for example parallel resonance, series resonance, insertion loss, insert phase place, the amplitude of the loss of turning back and phase place etc.Manufacturer or designer are when carrying out the PCB design, the S parameter model of devices such as electric capacity all is provided, the S parameter model of the general symbols such as electric capacity (Symbol) that use in PCB design concept figure all is stored under the particular category, for example can be the schematic symbol in the sym catalogue.The S parameter can be share with simulation software, for example when carrying out PI emulation, just must analyze the S supplemental characteristic of electric capacity.
In existing P CB design, adopted the method for designing that virtual prototype is carried out emulation to optimize the PI design of circuit board in a large number, strive that the design phase promptly finds out problem, thereby high-level efficiency, finish system design in high quality, shortened the design cycle effectively and saved design cost.Emulation tool can generate relevant circuit meshwork list (Netlist) according to designer's design, and calculates according to certain circuit or device model, thereby realizes PI emulation.The purpose of PI emulation is exactly the impedance curve that obtains power-supply system.Under signal situation very at a high speed, the target impedance that reaches and be connected the electric capacity formation between them between the power supply of PCB and ground level must satisfy certain situation just can make signal meet the requirements.PI emulation can obtain the impedance of PDS accurately to voltage adjuster, electric capacity, the modeling of system power supply ground level, obtain the function curve that the PCB of gang goes up each cell impedance and frequency by the wave simulation device.The target of PI emulation is to see the segmented shape on power supply ground, and whether the layer thickness on PCB power supply ground and added electric capacity kind and data meet the demands.
For example, carry out gang's curve that PI emulation obtains as shown in Figure 2.When the simulation result of Fig. 2 curve is analyzed, if the horizontal dotted line of curve in the middle of being positioned at meets the demands with the impedance on next expression power supply ground.
When the prior art scheme is carried out PCB PI emulation, at first in PCB layout software correlation module, carry out the principle diagram design of PCB, call the information of the symbolic model in the simulation software storehouse then and carry out emulation according to the schematic diagram formation net table that the designer designs by the designer; If the schematic diagram of PCB is to use third party's schematic diagram of third party software design, then some symbols in third party's schematic diagram are used default parameter and model.
For example, the allegro software of cadence company wherein includes a PI simulation software module, can be used for the schematic diagram of the PCB that designs at this software is carried out PI emulation.If the PCB schematic diagram uses the PCB layout software module of allegro software to design, information such as some symbols that then use in the schematic diagram such as the model of electric capacity and parameter can be obtained from the component models storehouse of simulation software; If the PCB schematic diagram uses the third party software design of non-allegro, information such as some symbols that then use in the schematic diagram such as the model of electric capacity and parameter are directly used default value.
In actual applications, there is following problem in such scheme: existing technical scheme is inaccurate to the PI simulation result of third party's schematic diagram.
Cause the main cause of this situation to be, emulation tool and third party's schematic diagram do not have interface in the existing technical scheme, do not read the numbering (CODE) of symbol in third party's schematic diagram, therefore can't determine the model and the parameter of symbol accurately, also can't utilize in the external libraries model accurately and the information of symbol in third party's schematic diagram, can only use default model and parameter, cause the PI simulation result inaccurate.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of method of printed circuit board power completeness simulation, makes to carry out PI emulation accurately to the printed circuit board (PCB) that third party's schematic diagram provides.
For achieving the above object, the invention provides a kind of method of printed circuit board power completeness simulation, comprise following steps:
A adds the information of first attribute of device in third party's schematic diagram of printed circuit board (PCB) in the information of this device second attribute to;
B generates power completeness simulation net table according to this third party's schematic diagram, and wherein this device uses default model and parameter, and only keeps the information of second attribute in generative process;
First attribute information that is comprised in second attribute information of C according to this device in this power completeness simulation net table is model and the parameter of setting for this device in described third party's schematic diagram with the default model of this device in this power completeness simulation net table and parameter modification;
D recompilates amended power completeness simulation net table and carries out power completeness simulation according to the compiling result.
Wherein, described first attribute is the numbering of described device, is used for the device of a kind of specified type of unique identification.
In this external described method, described second attribute is the device name of described device.
In this external described method, in the described steps A, described first attribute is added on after described second attribute, and this first, second attribute all adopts textual form.
In this external described method, described device is electric capacity, inductance or resistance.
In this external described method, model that described third party's schematic diagram uses and parameter are for using model or other test model of scattering parameter.
In this external described method, described step C further comprises following steps:
First attribute information that is comprised in second attribute information of C1 according to device described in the described power completeness simulation net table is for this device adds model name;
C2 is according to this model name, is pairing model of this model name and parameter in described third party's schematic diagram with the default model and the parameter modification of this device in this power completeness simulation net table.
In this external described method, among the described step C2, in described power completeness simulation net table, specify the model of described third party's schematic diagram use and the path of parameter according to described model name.
In this external described method, among the described step C2, model and the parameter of utilizing described third party's schematic diagram to use are directly carried out assignment in described power completeness simulation net table.
In this external described method, described model name is the numbering of described device.
By relatively finding, the key distinction of technical scheme of the present invention and prior art is, in the device symbol of third party's schematic diagram, first attribute information of device model and parameter correlation added in second attribute information under the principle of uniformity schematic symbol, wherein first attribute information can be in the power completeness simulation net table that generates, and only keeps second attribute of schematic symbol in the net table.After corresponding power completeness simulation instrument was called in this net table, first attribute information that is comprised in second attribute information according to this net table was composed corresponding model and parameter to corresponding device in corresponding power completeness simulation instrument again.In the line related property finished simulation software, generate the net table, at last by revising model and the parameter that the net table replaces to appointment in third party's schematic diagram, for further compiling and emulation.Designated parameters in third party's schematic diagram can be outside third party S parameter library.
Difference on this technical scheme has brought comparatively significantly beneficial effect, i.e. PI emulation is more accurate.By unsupported first attribute information of PCB software is added in second attribute information of its support, feasible processing through PCB software, after the generation as power completeness simulation net table, first attribute information is still kept indirectly, thereby can go to mate model and parameter in third party's schematic diagram according to this information.Come down between PCB software and third party's schematic diagram, to have set up interface by first contained in second attribute information attribute information.Precise analytic model and parameter in third party's schematic diagram have been arranged, just can make PI emulation more accurate.
Because the present invention program can call outside third party S parameter library, thereby guaranteed the accuracy of PI emulation,, can effectively reduce the possibility of design iterations for the design of PCB system provides reliable reference, and then further reduced the system design cycle, reduced the system design cost.
Description of drawings
Fig. 1 is the equivalent circuit diagram of electric capacity when high frequency;
Fig. 2 is the synoptic diagram that carries out gang's curve that PI emulation obtains;
Fig. 3 is the process flow diagram of PI emulation mode of the PCB of first better embodiment according to the present invention;
Fig. 4 is a unmodified preceding text message of describing the required description of an electric capacity symbol in the present invention's first better embodiment;
Fig. 5 revises the back to describe the text message that the electric capacity symbol is required in the present invention's first better embodiment;
Fig. 6 is the net table of the third party's schematic diagram after the section processes in the present invention's first better embodiment;
Fig. 7 is the interface when composing model to device in the present invention's first better embodiment;
Fig. 8 is a part that generates the PI emulation net table that contains default symbolic model in the present invention's first better embodiment;
Fig. 9 is revised as the result who obtains behind the model that uses third party S parameter library to PI emulation net table shown in Figure 8.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
In order to be illustrated more clearly in the solution of the present invention, illustrate below in conjunction with the present invention's first better embodiment.Wherein, the current PC B software that uses of first better embodiment is the allegro software of cadence company.
The flow process of the PI emulation mode of the PCB of first better embodiment as shown in Figure 3 according to the present invention.
At first enter step 310, revise the electric capacity symbol is relevant in third party's schematic diagram information make its numbering in current PC B software as seen.Device of each symbology among the present invention is as electric capacity etc.In first better embodiment of the present invention, the association attributes of schematic symbol leaves under the sys catalogue of third party's schematic diagram, and a unmodified preceding electric capacity symbolic information as shown in Figure 4.Wherein, special with the oval CODE that indicates promptly number be can unique this symbol of differentiation sign (Identification, abbreviation " ID "), it is unique corresponding with the model and the parameter of symbol; Device (DEVICE) is the ID of electric capacity model.In the present invention's first better embodiment, in this step, CODE information is added to after the DEVICE information, though allegro software is when reading in the symbolic information of third party's schematic diagram, do not read CODE information, therefore like this but read DEVICE information, processing can provide the interface of allegro software and third party's schematic diagram, make CODE information in allegro software as seen.In the present invention's first better embodiment, the situation of an electric capacity symbolic information shown in Figure 4 after step 310 is handled as shown in Figure 5.Wherein, the special CODE information of adding that is at DEVICE information afterbody with oval sign.
Then enter step 320, it is imported current PC B software after in the net table that third party's schematic diagram generates, adding the numbering of symbol.In the present invention's first better embodiment, if do not carry out the processing of this step, the net table that third party's schematic diagram generates can import current PC B software, but can not comprise CODE information, therefore in the net table, import current PC B software then can obtain symbol from the net table that imports CODE information after the numbering of interpolation symbol again.Net table in the present invention's first better embodiment after the section processes as shown in Figure 6, and is wherein, special in the electric capacity after the oval CODE information that is the interpolation symbol that indicates.
Then enter step 330, carry out the PI simulation process and generate the PI emulation net table that contains default symbolic model.In the present invention's first better embodiment, the execution and the prior art of PI simulation process are basic identical, unique difference is, when composing the model of symbol, the model name that signal model (Signal Model) field is filled in needs can be used for identifying this symbol in third party's schematic diagram corresponding model and parameter.Need to prove that the signal model field can be according to the CODE information hand filling that comprises in front type of device (DevType) field.In the present invention's first better embodiment, interface when composing the model of symbol as shown in Figure 7, wherein, selected electric capacity of a behavior, its DevType field is C-0603_001U08070247, Signal Model field is assigned C_08070247, and 08070247 is the CODE ID of this electric capacity.In addition of particular note, though obtained the PI simulation result after this step is finished, can't call the model and the parameter of the appointment of outside third party's schematic diagram in the simulation process of this moment, so the result is inaccurate.In the present invention's first better embodiment, a part that generates the PI emulation net table contain default symbolic model as shown in Figure 8.Wherein, the special default parameter that is this electric capacity use that indicates of rectangle.
Then enter step 340, revise PI emulation net table and make model that symbol wherein uses model as the S parameter library of appointment.Because the processing of preceding step makes in PI net table, the title of symbol has been set up relation one to one with their numberings separately, therefore, in this step, can directly specify the path of the model of third party S parameter library according to the title of symbol, also can utilize the Model parameter of third party S parameter library to carry out assignment.In the present invention's first better embodiment, directly specify the path of the model of third party S parameter library.In the present invention's first better embodiment, PI emulation net table shown in Figure 8 is revised as the model that uses third party S parameter library after, the result who obtains is as shown in Figure 9.Wherein, the outstanding delegation of background colour shows the path of the model of third party's parameter library that this electric capacity uses.
Then enter step 350, use PCB software to recompilate amended PI emulation net table and emulation.Therefore persons of ordinary skill in the art may appreciate that in this step, can use the model of third party S parameter library, can obtain third party's schematic diagram PI simulation result accurately.
On the basis of first better embodiment of the present invention, in order to realize these steps more easily, in second better embodiment of the present invention, modification and editor to symbol, net table and PI emulation net table in the above-mentioned steps all finish by Automatic Program.
The step of emulation and first embodiment are basic identical in the 3rd embodiment of the present invention, and difference only is that the device of being correlated with is inductance, the simulation result difference that is used in third party S parameter library difference, obtains.
Though pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (10)
1. the method for a printed circuit board power completeness simulation is characterized in that, comprises following steps:
A adds the information of first attribute of device in third party's schematic diagram of printed circuit board (PCB) in the information of this device second attribute to;
B generates power completeness simulation net table according to this third party's schematic diagram, and wherein this device uses default model and parameter, and is generating the information that the table back only needs reservation second attribute of netting;
First attribute information that is comprised in second attribute information of C according to this device in this power completeness simulation net table is model and the parameter of setting for this device in described third party's schematic diagram with the default model of this device in this power completeness simulation net table and parameter modification;
D recompilates amended described power completeness simulation net table and carries out power completeness simulation according to the compiling result.
2. the method for printed circuit board power completeness simulation according to claim 1 is characterized in that, described first attribute is the numbering of described device, is used for the device of a kind of specified type of unique identification.
3. the method for printed circuit board power completeness simulation according to claim 2 is characterized in that, described second attribute is the device name of described device.
4. the method for printed circuit board power completeness simulation according to claim 3 is characterized in that, in the described steps A, described first attribute is added on after described second attribute, and this first, second attribute all adopts textual form.
5. according to the method for each described printed circuit board power completeness simulation in the claim 1 to 4, it is characterized in that described device is electric capacity, inductance or resistance.
6. the method for printed circuit board power completeness simulation according to claim 5 is characterized in that, model that described third party's schematic diagram uses and parameter are for using the model and the parameter of scattering parameter.
7. according to the method for each described printed circuit board power completeness simulation in the claim 1 to 4, it is characterized in that described step C further comprises following steps:
First attribute information that is comprised in second attribute information of C1 according to device described in the described power completeness simulation net table is for this device adds model name;
C2 is according to this model name, is pairing model of this model name and parameter in described third party's schematic diagram with the default model and the parameter modification of this device in this power completeness simulation net table.
8. the method for printed circuit board power completeness simulation according to claim 7, it is characterized in that, among the described step C2, in described power completeness simulation net table, specify the model of described third party's schematic diagram use and the path of parameter according to described model name.
9. the method for printed circuit board power completeness simulation according to claim 7 is characterized in that, among the described step C2, model and the parameter of utilizing described third party's schematic diagram to use are directly carried out assignment in described power completeness simulation net table.
10. the method for printed circuit board power completeness simulation according to claim 7 is characterized in that, described model name is the numbering of described device.
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| CN102129496A (en) * | 2011-03-10 | 2011-07-20 | 浪潮(北京)电子信息产业有限公司 | Method and system for simulating power integrity of chip |
| CN102156766A (en) * | 2010-12-29 | 2011-08-17 | 中兴通讯股份有限公司 | Method and device thereof for obtaining scattering matrix of connector pin drilling array |
| CN102542079A (en) * | 2010-12-20 | 2012-07-04 | 中国科学院微电子研究所 | Conversion method and device for device model data between circuit emulators |
| CN103049586A (en) * | 2011-10-12 | 2013-04-17 | 无锡江南计算技术研究所 | Simulation method of power-supply distribution system and obtaining method of target impedance |
| CN103324768A (en) * | 2012-03-21 | 2013-09-25 | 苏州芯禾电子科技有限公司 | Quickly marking method of schematic circuit diagram |
| CN104731994A (en) * | 2013-12-23 | 2015-06-24 | 上海华虹宏力半导体制造有限公司 | Method of generating schematic netlist through nonstandard cell library |
| CN105404754A (en) * | 2015-12-09 | 2016-03-16 | 浪潮电子信息产业股份有限公司 | Method for evaluating SI signal quality based on POWER impact |
| CN106919757A (en) * | 2017-03-02 | 2017-07-04 | 济南浪潮高新科技投资发展有限公司 | A kind of method of the more piece point source emulation based on Cadence |
| CN107609224A (en) * | 2017-08-18 | 2018-01-19 | 郑州云海信息技术有限公司 | A kind of method that power supply disturbance is introduced in link simulation |
| CN107644122A (en) * | 2017-08-29 | 2018-01-30 | 深圳市兴森快捷电路科技股份有限公司 | A kind of ODB++ file modifications method, apparatus and readable storage medium storing program for executing |
| CN108694262A (en) * | 2017-04-11 | 2018-10-23 | 中兴通讯股份有限公司 | A kind of decoupling capacitor optimization method and device |
| CN111291526A (en) * | 2020-03-17 | 2020-06-16 | 芯启源(上海)半导体科技有限公司 | Novel method for simulating stability of fast power supply loop |
| CN115659704A (en) * | 2022-12-22 | 2023-01-31 | 成都华兴汇明科技有限公司 | Simulation method based on microwave module |
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- 2005-11-08 CN CNB2005101101049A patent/CN100386766C/en not_active Expired - Fee Related
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| CN102542079A (en) * | 2010-12-20 | 2012-07-04 | 中国科学院微电子研究所 | Conversion method and device for device model data between circuit emulators |
| CN102542079B (en) * | 2010-12-20 | 2013-11-27 | 中国科学院微电子研究所 | Conversion method and device for device model data between circuit emulators |
| CN102156766A (en) * | 2010-12-29 | 2011-08-17 | 中兴通讯股份有限公司 | Method and device thereof for obtaining scattering matrix of connector pin drilling array |
| CN102129496A (en) * | 2011-03-10 | 2011-07-20 | 浪潮(北京)电子信息产业有限公司 | Method and system for simulating power integrity of chip |
| CN103049586B (en) * | 2011-10-12 | 2016-10-12 | 无锡江南计算技术研究所 | The emulation mode of power distribution system and the acquisition methods of target impedance |
| CN103049586A (en) * | 2011-10-12 | 2013-04-17 | 无锡江南计算技术研究所 | Simulation method of power-supply distribution system and obtaining method of target impedance |
| CN103324768A (en) * | 2012-03-21 | 2013-09-25 | 苏州芯禾电子科技有限公司 | Quickly marking method of schematic circuit diagram |
| CN104731994A (en) * | 2013-12-23 | 2015-06-24 | 上海华虹宏力半导体制造有限公司 | Method of generating schematic netlist through nonstandard cell library |
| CN105404754A (en) * | 2015-12-09 | 2016-03-16 | 浪潮电子信息产业股份有限公司 | Method for evaluating SI signal quality based on POWER impact |
| CN106919757A (en) * | 2017-03-02 | 2017-07-04 | 济南浪潮高新科技投资发展有限公司 | A kind of method of the more piece point source emulation based on Cadence |
| CN108694262A (en) * | 2017-04-11 | 2018-10-23 | 中兴通讯股份有限公司 | A kind of decoupling capacitor optimization method and device |
| CN108694262B (en) * | 2017-04-11 | 2023-09-29 | 中兴通讯股份有限公司 | Decoupling capacitor optimization method and device |
| CN107609224A (en) * | 2017-08-18 | 2018-01-19 | 郑州云海信息技术有限公司 | A kind of method that power supply disturbance is introduced in link simulation |
| CN107644122A (en) * | 2017-08-29 | 2018-01-30 | 深圳市兴森快捷电路科技股份有限公司 | A kind of ODB++ file modifications method, apparatus and readable storage medium storing program for executing |
| CN111291526A (en) * | 2020-03-17 | 2020-06-16 | 芯启源(上海)半导体科技有限公司 | Novel method for simulating stability of fast power supply loop |
| CN115659704A (en) * | 2022-12-22 | 2023-01-31 | 成都华兴汇明科技有限公司 | Simulation method based on microwave module |
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