CN114580340A - Chip power supply decoupling simulation optimization method and device - Google Patents
Chip power supply decoupling simulation optimization method and device Download PDFInfo
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Abstract
The application relates to a method and a device for optimizing decoupling simulation of a chip power supply. According to the chip power supply design method and device, the chip power supply can meet the quality standard, the design success rate of a chip system is improved, meanwhile, the preset resource range can be met, the resource consumption cost is saved, the trial and error cost is reduced, and the chip design efficiency is improved. The method comprises the following steps: acquiring an initial printed circuit board design drawing of a chip to be designed, and acquiring initial circuit parameters based on the initial printed circuit board design drawing; inputting initial circuit parameters and capacitor device parameters into a power integrity simulation model, and adjusting the capacitor device parameters until power simulation performance parameters of the power integrity simulation model meet preset requirement standards; calculating a resource consumption component based on the adjusted parameter of the capacitor device, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range; and outputting the adjusted resource consumption component.
Description
Technical Field
The present application relates to the field of semiconductor chip technology, and in particular, to a method and apparatus for optimizing power decoupling simulation of a chip.
Background
The processor chip is widely applied to various scenes such as computers, mobile phones, deep learning, scientific computing and the like, in a process of designing a hardware circuit such as a CPU (central processing unit), a GPU (graphics processing unit) and the like, a PI (Power integrity) is very important, the Power integrity refers to the quality of a Power supply, in an actual application process, a Power supply module in the chip cannot achieve the effect of an ideal Power supply due to the influence of a PCB (printed circuit board) wiring or load requirement, a voltage or current waveform provided by the actual Power supply cannot be as stable and flat as the ideal Power supply, but has more fluctuation and noise, and further influences the performance of the whole chip, for example, the problem of screen splash caused by unstable work of a hardware circuit of a display card.
In order to ensure the integrity of a power supply, a power supply decoupling method is mostly adopted in the current chip design, and power supply decoupling refers to designing a proper capacitor for a power supply pin so as to filter power supply noise and ensure that the power supply can meet the system performance requirement. The existing power decoupling method is mostly a stacking type or an experience type, wherein the stacking type refers to the type and the number of capacitors added to each pin of a power chip, and the more the capacitors are, the better the capacitors are. The empirical derivation is the design of the power decoupling circuit by virtue of experience accumulated by engineers.
However, as the current chip circuit is developed towards a large-scale integrated circuit, the density of the single board is higher and higher, the requirement on the integrity of the power supply is higher and higher, a pile of unnecessary capacitors are easily added in the stock group, the stock group occupies valuable PCB space, and the experience group needs to carry out actual measurement on the processor chip every time, so that at least one to two plate-making iteration cycles are needed, and the trial-and-error cost is increased. Therefore, the existing power decoupling method consumes more resource cost, and is not beneficial to improving the chip design efficiency.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method and an apparatus for optimizing power decoupling simulation of a chip.
In a first aspect, the application provides a method for optimizing power decoupling simulation of a chip. The method comprises the following steps:
acquiring an initial printed circuit board design drawing of a chip to be designed, and acquiring initial circuit parameters based on the initial printed circuit board design drawing;
inputting the initial circuit parameters and the parameters of the capacitor device into a power integrity simulation model, and adjusting the parameters of the capacitor device until power simulation performance parameters output by the power integrity simulation model meet a preset requirement standard;
calculating a resource consumption component based on the adjusted parameter of the capacitor device, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
and outputting the adjusted resource consumption component.
In one embodiment, the inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until a total resource consumption amount output by the preset resource optimization model meets a preset resource range includes:
inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption;
and adjusting each resource consumption component until the total resource consumption amount meets the preset range.
In one embodiment, the resource consumption component comprises a capacitance amount and a capacitance average resource consumption amount; the inputting the resource consumption components into the preset resource optimization model, calculating a total product of the resource consumption components through the preset resource optimization model, and taking the product as a total resource consumption amount includes:
inputting the capacitance quantity and the capacitance average resource consumption into the preset resource optimization model, calculating a first product of the capacitance quantity and the capacitance average resource consumption through the preset resource optimization model, and taking the first product as the total resource consumption.
In one embodiment, the resource consumption component further comprises a capacitance class; the inputting the resource consumption components into the preset resource optimization model, calculating a total product of the resource consumption components through the preset resource optimization model, and taking the product as a total resource consumption amount includes:
inputting the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a second product of the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the second product as the total resource consumption.
In one embodiment, the method further comprises:
calculating the area occupied by the total capacitor based on the number of capacitors and the type of capacitors;
inputting the area occupied by the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the capacitor types into the preset resource optimization model, calculating a third product of the area occupied by the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the capacitor types through the preset resource optimization model, and taking the third product as the total resource consumption.
In one embodiment, the resource consumption component further comprises a time resource; the inputting the resource consumption components into the preset resource optimization model, calculating a total product of the resource consumption components through the preset resource optimization model, and taking the product as a total resource consumption amount includes:
inputting the time resource, the area occupied by the total capacitor, the number of capacitors, the average resource consumption of capacitors and the capacitor type into the preset resource optimization model, calculating a fourth product of the time resource, the area occupied by the total capacitor, the number of capacitors, the average resource consumption of capacitors and the capacitor type through the preset resource optimization model, and taking the fourth product as the total resource consumption.
In one embodiment, the resource consumption component comprises the capacitance quantity and the capacitance type; the method further comprises the following steps:
and inputting the capacitance quantity and the capacitance type into the preset resource optimization model, calculating the occupied area of the total capacitance through the preset resource optimization model, and taking the occupied area of the total capacitance as the total resource consumption.
In one embodiment, the method further comprises:
inputting the adjusted resource consumption component into the power integrity simulation model, and outputting a secondary simulation performance parameter;
and if the secondary simulation performance parameters meet the requirement standard, taking the adjusted resource consumption component as an optimal decoupling capacitor combination result.
In one embodiment, the method further comprises:
if the secondary simulation performance parameter does not meet the requirement standard, continuing to adjust the capacitor device parameter until the finally adjusted capacitor device parameter enables the capacitor simulation performance parameter to meet the requirement standard, and the corresponding resource consumption component enables the total resource consumption to meet the preset resource range;
and taking the resource consumption component corresponding to the finally adjusted capacitor device parameter as an optimal decoupling capacitor combination result.
In a second aspect, the application further provides a device for optimizing the decoupling simulation of the chip power supply. The device comprises:
the circuit board design drawing acquisition module is used for acquiring an initial printed circuit board design drawing of a chip to be designed and acquiring initial circuit parameters based on the initial printed circuit board design drawing;
the power integrity simulation module is used for inputting the initial circuit parameters and the parameters of the capacitor device into a power integrity simulation model and adjusting the parameters of the capacitor device until the power simulation performance parameters output by the power integrity simulation model meet a preset requirement standard;
the resource consumption component adjusting module is used for calculating a resource consumption component based on the adjusted parameter of the capacitor device, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
and the resource consumption component output module is used for outputting the adjusted resource consumption component.
According to the chip power decoupling simulation optimization method and device, initial circuit parameters are acquired based on an initial printed circuit board design drawing of a chip to be designed by obtaining the initial printed circuit board design drawing; inputting initial circuit parameters and capacitance device parameters into a power supply integrity simulation model, and adjusting the capacitance device parameters until power supply simulation performance parameters of the power supply integrity simulation model meet preset requirement standards; calculating a resource consumption component based on the adjusted parameter of the capacitor device, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range; and outputting the adjusted resource consumption component. According to the method, the decoupling capacitor device parameters meeting the quality standard are designed through the power integrity simulation model, and then the resource optimization model adjusts and optimizes the decoupling capacitor device parameters, so that the number and the type of the optimized decoupling capacitors can meet the preset resource range.
Drawings
FIG. 1 is a schematic flow chart of a simulation optimization method for decoupling chip power supply in one embodiment;
FIG. 2 is a graph of the operating characteristics of a single capacitor in one embodiment;
FIG. 3 is a graph of the operating characteristics of a plurality of capacitors in one embodiment;
FIG. 4 is a schematic flow chart of a simulation optimization method for decoupling chip power supply in another embodiment;
fig. 5 is a block diagram of a simulation optimization apparatus for power decoupling of a chip according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The chip power decoupling simulation optimization method provided by the embodiment of the application can be applied to terminal equipment or a server. The terminal device can be but not limited to various personal computers, notebook computers, smart phones, tablet computers, internet of things devices and portable wearable devices, and the internet of things devices can be smart sound boxes, smart televisions, smart air conditioners, smart vehicle-mounted devices and the like. The portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, and the like. The server may be implemented as a stand-alone server or as a server cluster consisting of a plurality of servers.
In an embodiment, as shown in fig. 1, a method for optimizing a power decoupling simulation of a chip is provided, which is described by taking an example that the method is applied to the terminal, and includes the following steps:
step S101, obtaining an initial printed circuit board design drawing of a chip to be designed, and collecting initial circuit parameters based on the initial printed circuit board design drawing;
the chip is a generic term of a semiconductor device product, and may be, for example, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or a microchip (microchip) of an automatic control system in a computer device, and generally, the chip is composed of an integrated circuit and an O-S-D device (i.e., an Optoelectronic device, a Sensor, and a Discrete device), where the integrated circuit accounts for about 80%, and the integrated circuit is mainly composed of a transistor. The chip type is not limited herein. The chip to be designed refers to a target chip to be designed, and the target chip may be of different types according to different actual application scenarios, for example, a chip in a vehicle-mounted system or a central processing unit in a computer device. In the chip design process, the design of an initial PCB (printed circuit board) is first completed according to the system principle, and the initial PCB is the above-mentioned initial PCB design drawing. The initial circuit parameters refer to the working voltage, current, load size, load frequency of the chip to be designed, and impedance, parasitic inductance and the like generated by routing in the initial PCB design drawing.
Specifically, after the initial design of the chip is completed and a system schematic diagram and an initial PCB design diagram are formed, the computer device may count circuit components used by the chip based on the initial PCB design diagram and form a Bill of Material (BOM), and extract initial circuit parameters affecting a power layer (a power part may be referred to as a power layer or as a power module) in the chip to be designed according to the system schematic diagram, the initial PCB design diagram and the Bill of Material (BOM), wherein the power module may be more than one block, and each power module may be analyzed separately.
Step S102, inputting initial circuit parameters and capacitor device parameters into a power integrity simulation model, and adjusting the capacitor device parameters until the output power simulation performance parameters of the power integrity simulation model meet preset requirement standards.
The Power Integrity (PI) simulation refers to designing a proper power decoupling circuit by simulating and analyzing various parameters of a chip in a circuit design stage, so that a power distribution system can provide stable and reliable electric energy, and the performance of the system is ensured. The power integrity simulation model may be a software model that is set in advance. The parameters of the capacitor device include the self-resonant frequency and impedance of the capacitor, etc. The capacitor device parameters refer to capacitance values, packaging attributes and the like of the capacitor.
The working principle of power decoupling is described here first. As is well known, a power module (or called power distribution module) is a circuit that transmits power from a power source end to a load, and a current flows from the power source end to the load end through the power distribution module and then flows back to the power source end through the power distribution module. In an ideal model, wires in a circuit are all impedance-free, parasitic inductance-free and parasitic capacitance-free, an ideal power supply can stably maintain required voltage and can provide transient response current when load demand current suddenly becomes large, but in practical application, the wires are also impedance-containing, and the load demand fluctuates at any time, so that the power supply cannot achieve the effect of the ideal power supply, and the output waveform of the power supply has more noises. In order to maintain a stable supply of power, it has been found that connecting enough capacitors to the power supply pins can filter out unwanted noise, so that the power supply is more perfect, i.e. the power supply is not affected by wires or loads (also called decoupling), the capacitors are also referred to as decoupling capacitors, and the basic requirement for decoupling the power supply module is to make the impedance of the equivalent power supply sufficiently small.
For a single capacitor, the operating characteristic curve is shown in fig. 2, the horizontal axis represents the operating frequency f, the vertical axis represents the impedance z of the capacitor, and each capacitor has a self-resonance point (also called resonance point) at which the impedance of the capacitor is minimum, so that the impedance can be reduced by adding a capacitor to the power module, and the decoupling (filtering) effect can be realized.
However, since only one self-resonance point of a single capacitor is determined, which is an inherent property of the capacitor, and is determined by the capacitance value, material and packaging type of the capacitor, the self-resonance point cannot be changed at will, and the power module cannot adapt to a wide range of operating frequencies by using a single capacitor, a plurality of capacitors are required to be used in combination. At present, a common practice is to use a plurality of capacitors with different capacitance values to form a low-impedance frequency band, as shown in fig. 3, so as to ensure that a power supply can work in a wide low-impedance frequency band range, and ensure stable operation of the system.
Specifically, in step S102, initial circuit parameters, such as load size, load frequency, and the like, and capacitance device parameters, such as capacitance value, and the like, are input into the power integrity simulation model to obtain power simulation performance parameters, such as impedance, parasitic inductance, and the like, and the final power simulation performance parameters are obtained by adjusting the capacitance device parameters, such as increasing capacitance type, number, and the like, and performing multiple simulations, and meet a preset requirement standard, which is not unique, and can be flexibly set according to a chip application scenario and actual requirements of a user. At the moment, the simulation of the integrity of the power supply is completed, and the chip power supply module can stably work under the action of the adjusted parameters of the capacitor device.
Step S103, calculating a resource consumption component based on the adjusted parameter of the capacitor device, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range.
The resource consumption component refers to resources consumed in the power decoupling process, such as the number of capacitors, the type of capacitors, the time spent, the PCB area, and other cost factors. The total resource consumption is the total result of the resource consumption consumed in the whole chip power supply optimization process under the comprehensive influence of the resource consumption components, and practice shows that the total result is not the simple superposition of the components. The resource optimization model refers to an optimization method that enables the overall result of reducing the above-described resource consumption. The resource optimization model may be the total product of the individual resource consumption components.
Specifically, resource consumption components are calculated according to the adjusted parameters of the capacitor device, for example, the total amount of capacitors consumed in the optimization process, the types of capacitors, the total area of used capacitors in the PCB, the time spent on the used capacitors, and other resource consumption components, and the components are input into the preset resource optimization model, and the sizes of the components are continuously adjusted until the final total product (i.e., the total resource consumption) of the components meets a preset resource range, wherein the preset resource range refers to the preset total cost of the input resources, and can be flexibly set according to actual requirements.
Further, the adjustment of the resource consumption component is not adjusted at will, and it is also required to consider that the adjusted component can enable the integrity of the power supply to meet a preset requirement standard, and the time spent, the total area of the PCB occupied by the capacitor, and the like can be adjusted.
And step S104, outputting the adjusted resource consumption component.
Specifically, the adjusted resource consumption components are output, and further processing is performed according to the capacitance type and the capacitance number corresponding to each component, for example, starting to purchase and put into board production.
According to the embodiment, the decoupling capacitor device parameters meeting the quality standard are designed through the power integrity simulation model, and then the resource optimization model adjusts and optimizes the decoupling capacitor device parameters, so that the number and the type of the optimized decoupling capacitors can meet the preset resource range.
In an embodiment, the step S103 includes: inputting the resource consumption components into a preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption; and adjusting each resource consumption component until the total resource consumption meets a preset range.
Through calculation, the total resource consumption is directly related to the total product of the resource consumption components, so that the total product of the resource consumption components can be used as the total resource consumption.
Specifically, the resource consumption components, such as the total amount of the used capacitors and the types of the used capacitors, are input into the resource optimization model, and the size of the model input components is adjusted until the total product of the resource consumption components meets a preset resource range, such as within the range of [10, 25 ].
According to the embodiment, the relation between the total resource consumption and each component is obtained through empirical analysis, so that the resource optimization model can be constructed to realize automatic optimization of resource investment, and the efficiency of resource optimization is improved.
In an embodiment, the resource consumption components include a capacitance number and a capacitance average resource consumption amount, and the step S103 includes: and inputting the capacitance quantity and the capacitance average resource consumption into a preset resource optimization model, calculating a first product of the capacitance quantity and the capacitance average resource consumption through the preset resource optimization model, and taking the first product as the total resource consumption.
Specifically, the calculation manner of the total resource consumption may be set as shown in the following formula (1):
Decoupling Cap Total Cost＝Quantity×Mean Vlue (1)
wherein Quantity represents the number of capacitors; mean value represents the average consumed resource using capacitance (which may be, for example, the average unit price or the average manufacturing time, etc.); the counting Cap Total Cost represents the Total resource consumption, i.e. the first product of the capacitance and the average resource consumption of the capacitance.
According to the embodiment, the correlation between the total resource consumption and the quantity of the capacitors and the correlation between the total resource consumption and the average consumed resources of the capacitors are obtained through empirical analysis, so that a proper resource optimization model is constructed to realize automatic optimization of resource investment, and the efficiency of resource optimization is improved.
In an embodiment, the resource consumption component further includes a capacitance type, and the step S103 includes: and inputting the quantity of the capacitors, the average resource consumption of the capacitors and the capacitor types into a preset resource optimization model, calculating a second product of the quantity of the capacitors, the average resource consumption of the capacitors and the capacitor types through the preset resource optimization model, and taking the second product as the total resource consumption.
Specifically, the calculation manner of the total resource consumption may be set as shown in the following formula (2):
Decoupling Cap Total Cost＝Quantity×Mean Vlue×Kinds (2)
wherein Quantity represents the number of capacitors; mean value represents the average consumed resource (which may be, for example, the average unit price or the average manufacturing time, etc.) using the capacitance; kinds represents the capacitance type; the counting Cap Total Cost represents the Total amount of the resource consumption, namely the second product of the capacitance quantity, the average resource consumption of the capacitance and the capacitance type.
According to the embodiment, the correlation between the total resource consumption amount and the number of the capacitors, the type of the capacitors and the average consumed resource of the capacitors is obtained through empirical analysis, so that a proper resource optimization model is constructed to realize automatic optimization of resource input, and the efficiency of resource optimization is improved.
In an embodiment, the step S103 includes: calculating the area occupied by the total capacitor based on the number and the type of the capacitors; and inputting the area occupied by the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the capacitor types into a preset resource optimization model, calculating a third product of the area occupied by the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the capacitor types through the preset resource optimization model, and taking the third product as the total resource consumption.
Specifically, the capacitors have different bottom areas according to different types, so that the bottom Area of each type of capacitor can be inquired based on the type of the capacitor, and the Area of the PCB Area occupied by the total capacitor is calculated according to the number of the capacitors and the type of the capacitors; on the basis of the above formula (2), the calculation method of the total resource consumption amount can be set as shown in the following formula (3):
Decoupling Cap Total Cost＝Quantity×Mean Vlue×Kinds×PCB Area (3)
wherein Quantity represents the number of capacitors; mean value represents the average consumed resource (which may be, for example, the average unit price or the average manufacturing time, etc.) using the capacitance; kinds represents the capacitance type; the PCB Area represents the Area occupied by the total capacitance; the counting Cap Total Cost represents the Total resource consumption, namely the third product of the capacitance quantity, the average capacitance resource consumption, the capacitance type and the Total capacitance occupied area.
According to the embodiment, the correlations between the total resource consumption and the capacitance quantity, the average resource consumption of the capacitance, the capacitance types and the occupied area of the total capacitance are obtained through empirical analysis, so that a proper resource optimization model is constructed to realize the automatic optimization of resource investment, and the efficiency of resource optimization is improved.
In an embodiment, the resource consumption component further includes a time resource, and the step S103 includes: inputting the time resource, the occupied area of the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the types of the capacitors into a preset resource optimization model, calculating a fourth product of the time resource, the occupied area of the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the types of the capacitors through the preset resource optimization model, and taking the fourth product as the total resource consumption.
Specifically, we conclude the way in which the total amount of resource consumption is calculated as shown in the following equation (4):
Decoupling Cap Total Cost＝Quantity×Kinds×Mean Vlue×PCB Area×Time (4)
wherein Quantity represents the total number of capacitances used; kinds: indicates the kind of capacitor used; mean value represents the average consumed resource (e.g., average unit price) using the capacitance; the PCB Area represents the total Area of the PCB occupied by the capacitor; time denotes elapsed Time; the counting Cap Total Cost represents the Total amount of resource consumption, i.e., the fourth product of the above components.
According to the embodiment, the correlations between the total resource consumption and the capacitance quantity, the average resource consumption of the capacitance, the capacitance type, the occupied area of the total capacitance and the time spent are obtained through empirical analysis, so that the method is beneficial to constructing a proper resource optimization model to realize the automatic optimization of resource investment, and the efficiency of resource optimization is improved.
In an embodiment, the resource consumption component includes a capacitance number and a capacitance type; the method further comprises the following steps: and inputting the quantity and the type of the capacitors into a preset resource optimization model, calculating the occupied area of the total capacitors through the preset resource optimization model, and taking the occupied area of the total capacitors as the total resource consumption.
Specifically, the resource optimization model may obtain a bottom Area corresponding to the type according to the type query of the input capacitors, calculate the Area PCB Area occupied by the total capacitor according to the number of each type of capacitor, and use the Area PCB Area occupied by the total capacitor as the total resource consumption amount.
According to the embodiment, the relevance of the occupied area of the total capacitor is calculated, the subsequent adjustment of the type and the quantity of the capacitors is facilitated, the occupied area of the total capacitor is introduced, and precious PCB area resources are saved.
In an embodiment, the method further includes: inputting the adjusted resource consumption component into a power integrity simulation model, and outputting a secondary simulation performance parameter; and if the secondary simulation performance parameters meet the requirement standard, taking the adjusted resource consumption component as the optimal decoupling capacitor combination result.
Specifically, as shown in fig. 4, fig. 4 shows another schematic flow chart of the chip power decoupling simulation optimization method, which includes:
in the first step, the system is designed primarily. The method mainly completes the design of a system schematic diagram and a PCB, and lists a bill of material (BOM) for the calculation of the subsequent steps;
second, power integrity emulation (PI). The designed PCB carries out power integrity simulation, decoupling is carried out through a redundant capacitor, and good simulation performance is guaranteed.
And thirdly, substituting any one of the formulas (1) to (4) for calculation, and optimizing. And if the total resource consumption is within the preset resource range, carrying out next PCB board feeding and upper piece production.
Further, if the total resource consumption is too high, secondary PI simulation is performed after parameters such as the number of capacitors and capacitance values of the capacitors need to be modified, secondary simulation performance parameters output by simulation meet the preset requirement standard, and the adjusted resource consumption component is used as an optimal decoupling capacitor combination result.
And fourthly, putting the PCB into production.
Fifthly, mass production of PCBs.
According to the embodiment, the optimized capacitor device parameters are subjected to secondary PI simulation, so that the optimized device parameters can meet the requirement on the integrity of a power supply and can be ensured to be saved in resource investment.
In an embodiment, as shown in fig. 4, the method further includes: if the secondary simulation performance parameters do not meet the requirement standards, continuing to adjust the parameters of the capacitor device until the finally adjusted parameters of the capacitor device enable the parameters of the capacitor simulation performance to meet the preset requirement standards, and enabling the total resource consumption amount to meet the preset resource range through the corresponding resource consumption components; and taking the resource consumption component corresponding to the finally adjusted capacitor device parameter as an optimal decoupling capacitor combination result.
According to the embodiment, the optimized capacitor device parameters are subjected to PI simulation repeatedly, so that the optimized device parameters can meet the requirement on the integrity of a power supply and can be guaranteed to save resource investment.
The technical effect brought by the method is clarified by a specific application, and the method is applied to the power supply integrity optimization process of the vehicle-mounted chip:
firstly, comparing an optimized scheme of a CORE power supply VDD _ CORE of the CPU with an original scheme, and accounting BOM (bill of material) cost and total cost by using a formula (4). The optimized and original schemes for memory cell VDD _ MEM are then compared and the BOM cost and the total cost are accounted using equation (4).
The optimized and original schemes for the CORE power supply VDD _ CORE of the CPU are compared as shown in Table 1 below
TABLE 1 VDD _ CORE optimized solution vs. original solution BOM
It can be seen from table 1 that, although the number of capacitors used in the scheme is the same before and after optimization, the same decoupling and filtering effect can be achieved by replacing materials due to different unit prices of different capacitors, and the types are reduced, so that the cost of the BOM is reduced, and the cost of the upper parts is indirectly reduced.
Table 2 below lists the relative BOM cost and the relative total cost before and after VDD _ CORE optimization.
TABLE 2 VDD _ CORE optimized solution vs. original solution cost
1 notes: the relative BOM cost is obtained by uniformizing the purchase unit prices of all capacitor costs with the price of the Murata GRM 100nF capacitor as 1. In the calculation of this scheme, the relative BOM cost of 100nF is 1.0, 330nF is 4.6, 4.7 μ F is 5.2, and 10 μ F is 6.1.
Note 2: the relative total cost means that the total relative BOM cost is superposed by considering the formula (4) and simultaneously considering the factors of the capacitor quantity, the single cost, the type, the occupied board area and the time and 5.
As can be seen from Table 2, the optimized scheme, only one term of VDD _ CORE, can compress the corresponding cost to-9.7%.
The optimized and original schemes of the power supply VDD _ MEM for the memory are compared with the following table 3:
| scheme(s) | 100nF capacitor | 4.7 muF capacitor | 10 muF capacitance |
| Original plan | 23 | 5 | 0 |
| Optimization scheme | 11(-12) | 0(-5) | 4(+4) |
Table 3 VDD _ MEM optimization scheme versus original scheme
It can be seen from the table that before and after VDD _ MEM is optimized, the number of capacitors used in the scheme is reduced by 13, the types of capacitors are reduced from 3 to 2, the optimized scheme achieves better effects through simulation and actual measurement, and meanwhile, the optimization brings obvious improvements to the design of material preparation, purchase and PCB. The synthesis results in a reduction in BOM cost.
Table 4 below lists the relative BOM cost and the relative total cost before and after VDD _ CORE optimization.
| Scheme(s) | Relative BOM cost*1 | Relative total cost*2 |
| Original plan | 49.0 | 49.0 |
| Optimization scheme | 35.4(-27.8％) | 29.1(-40.6％) |
Table 4 VDD _ MEM optimization scheme versus original scheme
1 notes: the relative BOM cost is obtained by uniformizing the purchase unit prices of all capacitor costs with the price of the Murata GRM 100nF capacitor as 1. In the calculation of this scheme, the relative BOM cost of 100nF is 1.0, 330nF is 4.6, 4.7 uF is 5.2, and 10 uF is 6.1.
Note 2: the relative total cost means that the total relative BOM cost is superposed by considering the formula (4) and simultaneously considering the factors of the capacitor quantity, the single cost, the type, the occupied board area and the time and 5.
As can be seen from table 4, the optimized scheme, only one term of VDD _ MEM, can compress the corresponding total cost to-40.6%.
Therefore, by integrating the capacitance optimization scheme of the CPU core power supply and the memory power supply, the total cost can be actually compressed by more than 25% after optimization. Experiments show that the scheme can achieve good effects, not only can the development cost be compressed, but also the system development flow can be improved, the research and development progress is accelerated, and the overall stability is ensured.
It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.
Based on the same inventive concept, the embodiment of the application also provides a chip power decoupling simulation optimization device for realizing the chip power decoupling simulation optimization method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the method, so the specific limitations in one or more embodiments of the chip power decoupling simulation optimization device provided below can refer to the limitations on the chip power decoupling simulation optimization method in the above, and are not described herein again.
In one embodiment, as shown in fig. 5, there is provided a chip power decoupling simulation optimizing device 500, including: a circuit board design drawing obtaining module 501, a power integrity simulation module 502, a resource consumption component adjusting module 503 and a resource consumption component output module 504, wherein:
the circuit board design drawing acquisition module is used for acquiring an initial printed circuit board design drawing of a chip to be designed and acquiring initial circuit parameters based on the initial printed circuit board design drawing;
the power integrity simulation module is used for inputting the initial circuit parameters and the parameters of the capacitor device into a power integrity simulation model, and adjusting the parameters of the capacitor device until the output power simulation performance parameters of the power integrity simulation model meet preset requirement standards;
the resource consumption component adjusting module is used for calculating a resource consumption component based on the adjusted parameter of the capacitor device, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
and the resource consumption component output module is used for outputting the adjusted resource consumption component.
In an embodiment, the resource consumption component adjusting module 503 is further configured to:
inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption; and adjusting each resource consumption component until the total resource consumption amount meets the preset range.
In an embodiment, the resource consumption component comprises a capacitance amount and a capacitance average resource consumption amount; the resource consumption component adjusting module 503 is further configured to:
inputting the capacitance quantity and the capacitance average resource consumption into the preset resource optimization model, calculating a first product of the capacitance quantity and the capacitance average resource consumption through the preset resource optimization model, and taking the first product as the total resource consumption.
In an embodiment, the resource consumption component further includes a capacitance type, and the resource consumption component adjusting module 503 is further configured to:
inputting the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a second product of the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the second product as the total resource consumption.
In an embodiment, the resource consumption component adjusting module 503 is further configured to:
calculating the area occupied by the total capacitor based on the number of capacitors and the type of capacitors; inputting the area occupied by the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the capacitor types into the preset resource optimization model, calculating a third product of the area occupied by the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the capacitor types through the preset resource optimization model, and taking the third product as the total resource consumption.
In an embodiment, the resource consumption component further comprises a time resource; the resource consumption component adjusting module 503 is further configured to:
inputting the time resource, the area occupied by the total capacitor, the number of capacitors, the average resource consumption of capacitors and the capacitor type into the preset resource optimization model, calculating a fourth product of the time resource, the area occupied by the total capacitor, the number of capacitors, the average resource consumption of capacitors and the capacitor type through the preset resource optimization model, and taking the fourth product as the total resource consumption.
In one embodiment, the resource consumption component includes a capacitance number and a capacitance type; the resource consumption component adjusting module 503 is further configured to:
and inputting the capacitance quantity and the capacitance type into the preset resource optimization model, calculating the occupied area of the total capacitance through the preset resource optimization model, and taking the occupied area of the total capacitance as the total resource consumption.
In an embodiment, the power integrity simulation module 502 is further configured to:
inputting the adjusted resource consumption component into the power integrity simulation model, and outputting a secondary simulation performance parameter; and if the secondary simulation performance parameters meet the preset requirement standard, taking the adjusted resource consumption component as an optimal decoupling capacitor combination result.
In an embodiment, the resource consumption component adjusting module 503 is further configured to:
if the secondary simulation performance parameter does not meet the preset requirement standard, continuing to adjust the capacitor device parameter until the finally adjusted capacitor device parameter enables the capacitor simulation performance parameter to meet the preset requirement standard, and the corresponding resource consumption component enables the total resource consumption to meet the preset resource range; and taking the resource consumption component corresponding to the finally adjusted capacitor device parameter as an optimal decoupling capacitor combination result.
All or part of each module in the chip power decoupling simulation optimization device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
It should be noted that, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (10)
1. A method for optimizing the decoupling simulation of a chip power supply is characterized by comprising the following steps:
acquiring an initial printed circuit board design drawing of a chip to be designed, and acquiring initial circuit parameters based on the initial printed circuit board design drawing;
inputting the initial circuit parameters and the parameters of the capacitor device into a power integrity simulation model, and adjusting the parameters of the capacitor device until power simulation performance parameters output by the power integrity simulation model meet preset requirement standards;
calculating a resource consumption component based on the adjusted parameter of the capacitor device, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
and outputting the adjusted resource consumption component.
2. The method according to claim 1, wherein the inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model satisfies a preset resource range comprises:
inputting the resource consumption components into the preset resource optimization model, calculating the total product of the resource consumption components through the preset resource optimization model, and taking the product as the total resource consumption;
and adjusting each resource consumption component until the total resource consumption amount meets the preset range.
3. The method of claim 2, wherein the resource consumption components include a capacitance amount and a capacitance average resource consumption amount; the inputting the resource consumption components into the preset resource optimization model, calculating a total product of the resource consumption components through the preset resource optimization model, and taking the product as a total resource consumption amount includes:
inputting the capacitance quantity and the capacitance average resource consumption into the preset resource optimization model, calculating a first product of the capacitance quantity and the capacitance average resource consumption through the preset resource optimization model, and taking the first product as the total resource consumption.
4. The method of claim 3, wherein the resource consumption component further comprises a capacitance class; the inputting the resource consumption components into the preset resource optimization model, calculating a total product of the resource consumption components through the preset resource optimization model, and taking the product as a total resource consumption amount includes:
inputting the capacitance quantity, the capacitance average resource consumption and the capacitance type into the preset resource optimization model, calculating a second product of the capacitance quantity, the capacitance average resource consumption and the capacitance type through the preset resource optimization model, and taking the second product as the total resource consumption.
5. The method of claim 4, further comprising:
calculating the area occupied by the total capacitor based on the number of capacitors and the type of capacitors;
inputting the area occupied by the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the capacitor types into the preset resource optimization model, calculating a third product of the area occupied by the total capacitor, the number of capacitors, the average resource consumption of the capacitors and the capacitor types through the preset resource optimization model, and taking the third product as the total resource consumption.
6. The method of claim 5, wherein the resource consumption component further comprises a time resource; the step of inputting the resource consumption components into the preset resource optimization model, calculating a total product of the resource consumption components through the preset resource optimization model, and taking the product as a total resource consumption amount includes:
inputting the time resource, the area occupied by the total capacitor, the number of capacitors, the average resource consumption of capacitors and the capacitor type into the preset resource optimization model, calculating a fourth product of the time resource, the area occupied by the total capacitor, the number of capacitors, the average resource consumption of capacitors and the capacitor type through the preset resource optimization model, and taking the fourth product as the total resource consumption.
7. The method of claim 2, wherein the resource consumption components include a number of capacitors, a type of capacitor; the method further comprises the following steps:
and inputting the capacitance quantity and the capacitance type into the preset resource optimization model, calculating the occupied area of the total capacitance through the preset resource optimization model, and taking the occupied area of the total capacitance as the total resource consumption.
8. The method of claim 1, further comprising:
inputting the adjusted resource consumption component into the power integrity simulation model, and outputting a secondary simulation performance parameter;
and if the secondary simulation performance parameters meet the preset requirement standard, taking the adjusted resource consumption component as an optimal decoupling capacitor combination result.
9. The method of claim 8, further comprising:
if the secondary simulation performance parameter does not meet the preset requirement standard, continuing to adjust the capacitor device parameter until the finally adjusted capacitor device parameter enables the capacitor simulation performance parameter to meet the preset requirement standard, and the corresponding resource consumption component enables the total resource consumption to meet the preset resource range;
and taking the resource consumption component corresponding to the finally adjusted capacitor device parameter as an optimal decoupling capacitor combination result.
10. A device for optimizing simulation of power decoupling on a chip, the device comprising:
the circuit board design drawing acquisition module is used for acquiring an initial printed circuit board design drawing of a chip to be designed and acquiring initial circuit parameters based on the initial printed circuit board design drawing;
the power integrity simulation module is used for inputting the initial circuit parameters and the parameters of the capacitor device into a power integrity simulation model and adjusting the parameters of the capacitor device until the power simulation performance parameters output by the power integrity simulation model meet a preset requirement standard;
the resource consumption component adjusting module is used for calculating a resource consumption component based on the adjusted parameter of the capacitor device, inputting the resource consumption component into a preset resource optimization model, and adjusting the resource consumption component until the total resource consumption output by the preset resource optimization model meets a preset resource range;
and the resource consumption component output module is used for outputting the adjusted resource consumption component.
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