CN111563356A - PDN impedance flattening simulation method, device, equipment and medium - Google Patents
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Abstract
The invention discloses a PDN impedance flattening simulation method, which comprises the following steps: converting the decoupling capacitance model into an equivalent series RLC circuit; respectively calculating the variation of the IC end impedance of the decoupling capacitor of the nodes to be placed of the different decoupling capacitors through simulation; configuring the node to be placed of the decoupling capacitor corresponding to the maximum variation of the IC terminal impedance as a first position node; calculating the variable quantity of the IC end impedance of the nodes to be placed of other decoupling capacitors again and sequentially acquiring the sequence of the nodes to be placed of all the decoupling capacitors; obtaining a capacitance value corresponding to a curve interleaving point of the target impedance and the PDN impedance, and placing a decoupling capacitor with the capacitance value adjacent to and larger than the capacitance value corresponding to the interleaving point on a first position node; the previous step is repeated for all the location nodes in turn to place decoupling capacitances. The invention also discloses a device, equipment and a medium. The PDN impedance flattening simulation method, device, equipment and medium provided by the invention can flatten the PDN impedance.
Description
Technical Field
The present invention relates to the field of circuit design technologies, and in particular, to a method, an apparatus, a device, and a medium for simulating PDN impedance planarization.
Background
In the design of a server PCB (Printed circuit board), a power plane and a ground plane, such as a resonant cavity, have resonant modes in different sizes or shapes, fig. 1 shows a schematic diagram of a power distribution network in the prior art, as shown in fig. 1, in the design of a Power Distribution Network (PDN), it is simply designed whether a power path between a power end and a pumping capacitor meets a requirement of a Target Impedance (Target Impedance) within an effective bandwidth, and if a frequency point of the Target Impedance is exceeded, a power ripple caused by power pumping jumps to a frequency point of the PCB, which may cause a radiation problem. If the PDN (Power Distribution Network) impedance in the IC Power pins is too high, the switching current will generate a voltage that is observable in the signal itself when all the regulator modules switch simultaneously.
How much the target impedance (Z) should be set can be defined based on what interval the ripple of the desired pumping voltage is expected to suppress to, or how much peak current it is expected to carry.
The target impedance (Z) may be calculated according to method as follows: z ═ Δ V ÷ Δ I.
The target impedance is calculated based on the following two assumptions:
1. the impedance of the whole concerned frequency band interval is flat;
PDN is linear and time invariant.
In fact, the PDN of the server cannot operate according to both of the above assumptions.
Fig. 2 is a diagram illustrating the relationship between the magnitude and phase of the impedance and the current in the prior art, and as shown in fig. 2, if the response diagram of the single step current is observed alone, there are three resonance points on the impedance diagram.
Fig. 3 is a schematic diagram showing the relationship between the magnitude and phase of impedance and current in the very bad case of the prior art, and as shown in fig. 3, if there are multiple step current responses, it is possible that the responses will be superimposed at a certain time point to cause a very large resonance, which is called rogue wave (rogue wave), as the operation time advances. This is also why PDN impedance planarization needs to be designed for the purpose.
Disclosure of Invention
In view of the above, an embodiment of the present invention provides a PDN impedance simulation scheme, which can select a proper decoupling capacitance value by locating a decoupling capacitor in a PCB, so as to achieve the design goal of planarizing the PDN impedance and reduce the influence of the ripple voltage of the wild dog.
Based on the above object, an aspect of the present invention provides a PDN impedance flattening simulation method, including: converting the model of the decoupling capacitor into an equivalent series RLC circuit; on the basis of an equivalent series RLC circuit, the variation of the IC end impedance of the decoupling capacitor of the nodes to be placed of different decoupling capacitors is calculated through simulation; configuring the node to be placed of the decoupling capacitor corresponding to the maximum variation of the IC terminal impedance as a first position node; calculating the variation of the IC end impedance of the nodes to be placed of other decoupling capacitors again, and configuring the node to be placed of the decoupling capacitor corresponding to the maximum variation of the IC end impedance as a next position node; repeating the previous step to sequentially obtain the sequence of nodes to be placed of all decoupling capacitors; obtaining a capacitance value corresponding to a curve interleaving point of the target impedance and the PDN impedance, and placing a decoupling capacitor with the capacitance value adjacent to and larger than the capacitance value corresponding to the interleaving point on a first position node; the previous step is repeated for all the location nodes in turn to place decoupling capacitances.
In some embodiments of the PDN impedance flattening simulation method of the present invention, transforming the model of decoupling capacitance into an equivalent series RLC circuit further comprises: a VRM (Voltage Regulator Module) and a polar electrolytic capacitor model are placed in an equivalent series RLC circuit.
In some embodiments of the PDN impedance flattening simulation method of the present invention, calculating, based on the equivalent series RLC circuit, a variation amount of an IC end impedance of each of the different decoupling capacitance nodes to be placed with or without a decoupling capacitance by simulation further includes: calculating the impedance of the IC end when the decoupling capacitor is placed on the node where the decoupling capacitor is to be placed through a simulation calculation formula; and calculating the variation of the IC end impedance when the node to be placed of the decoupling capacitor is short-circuited according to a simulation calculation formula and the IC end impedance.
In some embodiments of the PDN impedance planarization simulation method of the present invention, the method further comprises: before simulation, a model database of decoupling capacitors is sorted according to different direct current bias voltages.
In some embodiments of the PDN impedance flattening simulation method of the present invention, obtaining a capacitance value corresponding to a curve intersection of the target impedance and the PDN impedance, and placing a decoupling capacitance having a capacitance value close to and greater than the capacitance value corresponding to the intersection at the first location node further includes: and acquiring the frequency corresponding to the curve interleaving point of the target impedance and the PDN impedance, and acquiring the capacitance value according to the frequency.
In another aspect of the embodiments of the present invention, a PDN impedance flattening simulation apparatus is further provided, where the apparatus includes: a conversion module configured to convert the model of the decoupling capacitance into an equivalent series RLC circuit; the simulation calculation module is configured to calculate the variation of the IC end impedance of the decoupling capacitor of the nodes to be placed of different decoupling capacitors through simulation based on the equivalent series RLC circuit; the first position node module is configured to configure a decoupling capacitance node to be placed corresponding to the maximum variation of the IC terminal impedance as a first position node; the next position node configuration module is configured to calculate the variation of the impedance of the IC end of the node to be placed of other decoupling capacitors again, and configure the node to be placed of the decoupling capacitor corresponding to the maximum variation of the impedance of the IC end as the next position node; the sequence acquisition module is configured to repeat the previous step to sequentially acquire the sequence of the nodes to be placed of all the decoupling capacitors; the capacitance value calculation module is configured to acquire capacitance values corresponding to curve interleaving points of the target impedance and the PDN impedance, and a decoupling capacitor, which is adjacent to the capacitance values and is larger than the capacitance values corresponding to the interleaving points, is placed at the first position node; a sequential computation module configured to repeat a previous step sequentially for all of the location nodes to place decoupling capacitances.
In some embodiments of the PDN impedance flattening simulation apparatus of the present invention, the transformation module is further configured to: and putting the power supply adjusting module and the polar electrolytic capacitor model into an equivalent series RLC circuit.
In some embodiments of the PDN impedance flattening simulation apparatus of the present invention, the simulation calculation module further includes: calculating the impedance of the IC end when the decoupling capacitor is placed on the node where the decoupling capacitor is to be placed through a simulation calculation formula; and calculating the variation of the IC end impedance when the node to be placed of the decoupling capacitor is short-circuited according to a simulation calculation formula and the IC end impedance.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory, wherein the memory stores a computer program capable of running on the processor, and the processor executes the PDN impedance flattening simulation method when executing the program.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, where a computer program is stored, and is characterized in that when being executed by a processor, the computer program performs the aforementioned PDN impedance flattening simulation method.
The invention has at least the following beneficial technical effects: the influence of the wave voltage surge of the mad dog on the power plane and the ground plane can be avoided. Avoid noise interference and significantly improve the design quality of server PDN and power integrity.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 illustrates a schematic diagram of a prior art power distribution network;
FIG. 2 is a diagram illustrating the magnitude and phase of impedance versus current in the prior art;
FIG. 3 is a diagram showing the magnitude of impedance and phase versus current for a very poor condition in the prior art;
figure 4 shows a schematic block diagram of an embodiment of a PDN impedance planarization simulation method according to the present invention;
figure 5 shows a schematic diagram of a PDN simulation node of an embodiment of a PDN impedance flattening simulation method according to the present invention;
figure 6 shows a schematic diagram of a first ordering of the rate of change of Z11 for an embodiment of a PDN impedance planarization simulation method in accordance with the present invention;
figure 7 shows a schematic diagram of the first two orderings of the rate of change of Z11 for an embodiment of a PDN impedance planarization simulation method in accordance with the present invention;
FIG. 8 shows a schematic diagram of a target impedance (red line) versus a PDN impedance for an embodiment of a PDN impedance flattening simulation method in accordance with the present invention;
fig. 9 is a schematic diagram illustrating a capacitance selection manner requiring placement according to an embodiment of the PDN impedance planarization simulation method of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it is understood that "first" and "second" are only used for convenience of description and should not be construed as limiting the embodiments of the present invention, and the descriptions thereof in the following embodiments are omitted.
In view of the foregoing, a first aspect of the embodiments of the present invention provides an embodiment of a PDN impedance planarization simulation method. Fig. 1 shows a schematic diagram of an embodiment of a PDN impedance planarization simulation method according to the present invention. In the embodiment shown in fig. 1, the method comprises at least the following steps:
s100, converting the model of the decoupling capacitor into an equivalent series RLC circuit;
s200, respectively calculating the variation of the IC end impedance of the decoupling capacitors of the nodes to be placed of the different decoupling capacitors through simulation based on the equivalent series RLC circuit;
s300, configuring a node to be placed with decoupling capacitance corresponding to the maximum variation of the IC end impedance as a first position node;
s400, calculating the variation of the IC end impedance of the nodes to be placed of other decoupling capacitors again, and configuring the node to be placed of the decoupling capacitor corresponding to the maximum variation of the IC end impedance as a next position node;
s500, repeating the previous step to sequentially obtain the sequence of nodes to be placed of all decoupling capacitors;
s600, capacitance values corresponding to curve interleaving points of the target impedance and the PDN impedance are obtained, and decoupling capacitors, which are adjacent to the capacitance values and are larger than the capacitance values corresponding to the interleaving points, are placed on the first position nodes;
s700, repeating the previous step for all position nodes in sequence to place decoupling capacitance.
In some embodiments of the present invention, fig. 4 is a schematic block diagram illustrating an embodiment of a PDN impedance flattening simulation method according to the present invention, as illustrated in fig. 4, power plane impedance design flattening may be achieved through two main approaches:
firstly, relatively important node placing capacitors on a power plane and a ground plane are searched.
And secondly, finding out the capacitance value suitable for placement through screening of the capacitance database.
Wherein, mode one includes:
the preparation work before simulation needs to prepare a model (S2P) of decoupling capacitance, and the model is converted into an equivalent series RLC circuit for accelerating simulation software calculation; fig. 5 is a schematic diagram of a PDN simulation node according to an embodiment of the PDN impedance planarization simulation method of the present invention, as shown in fig. 5, where P1 is an observation node at the IC end, and P2 is a decoupling capacitor node to be placed; and calculating the change Delta Z11 of the decoupling capacitance to Z11, and sequentially performing the arrangement position of the decoupling capacitance of each node, wherein the more important the change of the node Z11 is, the larger the change is. If there is a node between the power plane and the ground plane at which the capacitor is to be placed, a model simulation result can be obtained. Fig. 6 is a schematic diagram showing a first ordering of the rates of change of Z11 according to an embodiment of the PDN impedance flattening simulation method of the present invention, as shown in fig. 6 with P3 being the first significant node. After the P3 is placed on the decoupling capacitor, after one operation is repeated, the operations of P2, P4, P5, P6, P7 and P8 are simulated again to obtain the delta Z11. Figure 7 shows a schematic diagram of the first two orderings of the rate of change of Z11 for an embodiment of a PDN impedance planarization simulation method in accordance with the present invention; as shown in fig. 7, P6 is the second important node. After the decoupling capacitor is placed in the P6, after one operation is repeated, the operations of P2, P4, P5, P7 and P8 are simulated again to obtain the delta Z11. Until the priority of each node is sorted out.
The second mode comprises the following steps:
finding the intersection point of the target impedance and the PDN impedance, fig. 8 shows a schematic diagram of the target impedance (red line) and the PDN impedance according to an embodiment of the PDN impedance planarization simulation method of the present invention, as shown in fig. 8, the curve of the target impedance is a gray curve in fig. 8, and the curve of the PDN impedance is a black curve in fig. 8; frequency on the horizontal axis of the graph represents Frequency, Impedance on the vertical axis represents Impedance value, and capacitors are placed in the order of priority of the capacitors obtained in the first mode; as shown in fig. 9, the capacitance value selection can first find the capacitance value Cx at the intersection point, and the capacitance value to be placed needs to be adjacent to and greater than Cx, so as to achieve the purpose of suppressing the PDN impedance from being lower than the target impedance; the PDN impedance can be lower than the target impedance and the planarization can be achieved by repeating the steps. In one embodiment, the capacitance values that need to be placed are greater than Cx and less than 110% Cx.
According to some embodiments of the PDN impedance flattening simulation method of the present invention, transforming the model of the decoupling capacitance into an equivalent series RLC circuit further comprises:
and putting the power supply adjusting module and the polar electrolytic capacitor model into an equivalent series RLC circuit.
In some embodiments of the present invention, the pre-simulation preparation requires that the model of the decoupling capacitance (S2P) be prepared and converted to an esr circuit to speed up the simulation software calculations. And first, the power supply adjusting module and the polar electrolytic capacitor model are embedded. As shown in FIG. 5, P1 is the observation node of the IC terminal, and P2 is the node where the decoupling capacitor is to be placed.
According to some embodiments of the PDN impedance flattening simulation method of the present invention, based on the equivalent series RLC circuit, calculating, through simulation, a variation amount of an IC terminal impedance of a decoupling capacitor of a node to be placed of a different decoupling capacitor, respectively, further includes:
calculating the impedance of the IC end when the decoupling capacitor is placed on the node where the decoupling capacitor is to be placed through a simulation calculation formula;
and calculating the variation of the IC end impedance when the node to be placed of the decoupling capacitor is short-circuited according to a simulation calculation formula and the IC end impedance.
In some embodiments of the present invention, when P2 has a placement capacitance, Z11 can be calculated through simulation as follows:
when P2 is short-circuited, Zd is 0, and the variation Δ Z11 of the decoupling capacitance to Z11 can be calculated as follows according to the formula:
according to some embodiments of the PDN impedance planarization simulation method of the present invention, the method further comprises:
before simulation, a model database of decoupling capacitors is sorted according to different direct current bias voltages.
In some embodiments of the present invention, the preparation before simulation requires that the model database of decoupling capacitors be sorted according to different dc bias voltages.
According to some embodiments of the PDN impedance flattening simulation method of the present invention, obtaining a capacitance value corresponding to a curve intersection of the target impedance and the PDN impedance, and placing a decoupling capacitance having a capacitance value close to and greater than the capacitance value corresponding to the intersection at the first location node further includes:
and acquiring the frequency corresponding to the curve interleaving point of the target impedance and the PDN impedance, and acquiring the capacitance value according to the frequency.
In some embodiments of the present invention, the capacitance value can be selected by first finding the capacitance value Cx at the cross point as follows, where f is the frequency of the cross point, and obtaining the capacitance value by the following formula:
in another aspect of the embodiments of the present invention, an embodiment of a PDN impedance flattening simulation apparatus is provided. The device includes:
a conversion module configured to convert the model of the decoupling capacitance into an equivalent series RLC circuit;
the simulation calculation module is configured to calculate the variation of the IC end impedance of the decoupling capacitor of the nodes to be placed of different decoupling capacitors through simulation based on the equivalent series RLC circuit;
the first position node module is configured to configure a decoupling capacitance node to be placed corresponding to the maximum variation of the IC terminal impedance as a first position node;
the next position node configuration module is configured to calculate the variation of the impedance of the IC end of the node to be placed of other decoupling capacitors again, and configure the node to be placed of the decoupling capacitor corresponding to the maximum variation of the impedance of the IC end as the next position node;
the sequence acquisition module is configured to repeat the previous step to sequentially acquire the sequence of the nodes to be placed of all the decoupling capacitors;
the capacitance value calculation module is configured to acquire capacitance values corresponding to curve interleaving points of the target impedance and the PDN impedance, and a decoupling capacitor, which is adjacent to the capacitance values and is larger than the capacitance values corresponding to the interleaving points, is placed at the first position node;
a sequential computation module configured to repeat a previous step sequentially for all of the location nodes to place decoupling capacitances.
According to some embodiments of the PDN impedance flattening simulation apparatus of the present invention, the transformation module is further configured to:
and putting the power supply adjusting module and the polar electrolytic capacitor model into an equivalent series RLC circuit.
According to some embodiments of the PDN impedance flattening simulation apparatus of the present invention, the simulation calculation module further includes:
calculating the impedance of the IC end when the decoupling capacitor is placed on the node where the decoupling capacitor is to be placed through a simulation calculation formula;
and calculating the variation of the IC end impedance when the node to be placed of the decoupling capacitor is short-circuited according to a simulation calculation formula and the IC end impedance.
In view of the above object, another aspect of the embodiments of the present invention further provides a computer device, including: at least one processor; and a memory, wherein the memory stores a computer program capable of running on the processor, and the processor executes the PDN impedance flattening simulation method when executing the program.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is further provided, where a computer program is stored, and is characterized in that when being executed by a processor, the computer program performs the aforementioned PDN impedance flattening simulation method.
As such, those skilled in the art will appreciate that all of the embodiments, features and advantages set forth above with respect to the PDN impedance flattening simulation method according to the present invention apply equally well to the apparatus, the computer device and the medium according to the present invention. For the sake of brevity of the present disclosure, no repeated explanation is provided herein.
It should be particularly noted that, the steps in the above-mentioned PDN impedance flattening simulation method, apparatus, device and medium embodiments may be mutually intersected, replaced, added or deleted, and therefore, these reasonable permutation and combination transformations for the PDN impedance flattening simulation method, apparatus, device and medium should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the PDN impedance planarization simulation method can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A PDN impedance flattening simulation method is characterized by comprising the following steps:
converting the model of the decoupling capacitor into an equivalent series RLC circuit;
on the basis of the equivalent series RLC circuit, the variation of the IC end impedance of the decoupling capacitor of different nodes to be placed of the decoupling capacitor is calculated through simulation;
configuring the node to be placed of the decoupling capacitance corresponding to the maximum variation of the IC terminal impedance as a first position node;
calculating the variation of the IC end impedance of other nodes with decoupling capacitance to be placed again, and configuring the node with decoupling capacitance to be placed corresponding to the maximum variation of the IC end impedance as a next position node;
repeating the previous step to sequentially obtain the sequence of the nodes to be placed of the decoupling capacitors;
obtaining a capacitance value corresponding to a curve interleaving point of a target impedance and a PDN impedance, and placing a decoupling capacitor with the capacitance value adjacent to and larger than the capacitance value corresponding to the interleaving point at the first position node;
repeating the previous step for all location nodes in turn to place the decoupling capacitance.
2. The PDN impedance planarization simulation method of claim 1, wherein the transforming the model of decoupling capacitance into an equivalent series RLC circuit further comprises:
and putting a power supply adjusting module and a polar electrolytic capacitor model into the equivalent series RLC circuit.
3. The PDN impedance flattening simulation method according to claim 1, wherein the calculating, based on the equivalent series RLC circuit, a variation of an IC end impedance of each of nodes where different decoupling capacitors are to be placed by simulation for presence or absence of the decoupling capacitor further includes:
calculating the IC end impedance when the decoupling capacitor is placed on the node where the decoupling capacitor is to be placed through a simulation calculation formula;
and calculating the variation of the IC end impedance when the node to be placed of the decoupling capacitor is short-circuited according to the simulation calculation formula and the IC end impedance.
4. The PDN impedance planarization simulation method of claim 1, wherein the method further comprises:
before simulation, the model database of the decoupling capacitor is sorted according to different direct current bias voltages.
5. The PDN impedance planarization simulation method of claim 1, wherein the obtaining a capacitance value corresponding to a curve intersection of the target impedance and the PDN impedance, placing a decoupling capacitance at the first location node with a capacitance value adjacent to and greater than the capacitance value corresponding to the intersection further comprises:
and acquiring the frequency corresponding to the curve interleaving point of the target impedance and the PDN impedance, and acquiring the capacitance value according to the frequency.
6. An apparatus for PDN impedance flattening emulation, the apparatus comprising:
a translation module configured to translate a model of decoupling capacitance to an equivalent series RLC circuit;
the simulation calculation module is configured to calculate the variation of the IC end impedance of the decoupling capacitor of the nodes to be placed of different decoupling capacitors through simulation based on the equivalent series RLC circuit;
a first position node module configured to configure the decoupling capacitance node to be placed corresponding to the largest variation of the IC terminal impedance as a first position node;
a next position node configuration module, configured to calculate again the variation of the IC terminal impedance of the other nodes where the decoupling capacitor is to be placed, and configure the node where the decoupling capacitor is to be placed corresponding to the largest variation of the IC terminal impedance as a next position node;
a sequence acquisition module configured to repeat a previous step to sequentially acquire a sequence of all the nodes where the decoupling capacitors are to be placed;
a capacitance value calculation module configured to obtain a capacitance value corresponding to a curve intersection of a target impedance and a PDN impedance, and place a decoupling capacitance having a capacitance value adjacent to and greater than the capacitance value corresponding to the intersection at the first position node;
a sequential computation module configured to repeat a previous step sequentially for all position nodes to place the decoupling capacitance.
7. The PDN impedance flattening simulation apparatus of claim 6, wherein the conversion module is further configured to:
and putting a power supply adjusting module and a polar electrolytic capacitor model into the equivalent series RLC circuit.
8. The PDN impedance flattening simulation apparatus of claim 6, wherein the simulation computation module further comprises:
calculating the IC end impedance when the decoupling capacitor is placed on the node where the decoupling capacitor is to be placed through a simulation calculation formula;
and calculating the variation of the IC end impedance when the node to be placed of the decoupling capacitor is short-circuited according to the simulation calculation formula and the IC end impedance.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor, when executing the program, performs the method of any of claims 1-5.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the method of any one of claims 1 to 5.
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