TWI761177B - Method for flattening impedance of power deliver network - Google Patents
Method for flattening impedance of power deliver network Download PDFInfo
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本發明關於一種平坦化電源遞送網路之阻抗的方法,尤指一種可選擇適宜的去耦電容以平坦化電源遞送網路之阻抗的方法。 The present invention relates to a method for flattening the impedance of a power delivery network, and more particularly, to a method for selecting a suitable decoupling capacitor to flatten the impedance of the power delivery network.
電源遞送網路(Power Distribution Network,PDN)為電壓源提供直流電源至負載的傳遞媒介,且於印刷電路板上,通常為電壓調節模組(Voltage Regulator Module,VRM)至負載電路的傳遞路徑。電源遞送網路可組成於印刷電路板之電源層及接地層,且與電源層及接地層電連接之纜線、連接器、電容等元件,皆可屬於電源遞送網路之一部分。 A power distribution network (PDN) provides a transmission medium for a voltage source to transmit DC power to a load, and is usually a transmission path from a voltage regulator module (VRM) to a load circuit on a printed circuit board. The power delivery network can be composed of the power supply layer and the ground layer of the printed circuit board, and components such as cables, connectors, and capacitors that are electrically connected to the power supply layer and the ground layer can be part of the power delivery network.
由於電源遞送網路的寄生效應可造成並聯諧振,故導致負載電路之位置的高自阻抗(self-impedance)。於負載電路之位置,因為負載電流的變化及電源遞送網路的高自阻抗,而會產生電壓擾動之問題。 Since parasitics of the power delivery network can cause parallel resonance, high self-impedance at the location of the load circuit results. At the position of the load circuit, the problem of voltage disturbance will arise due to the variation of the load current and the high self-impedance of the power delivery network.
此外,當電源遞送網路之自阻抗對頻率的曲線不平坦時,電壓擾動相互重疊造成的畸波(rouge wave)問題,將使電壓擾動問題更趨嚴重。伺服器為一種包含印刷電路板的電子裝置,其印刷電路板的電源層及接地層可構成電源遞送網路之一部分,因此,伺服器在印刷電路板的電源遞送網路的設計上除需考慮降低阻抗以避免雜訊干擾外,還需考慮阻抗平坦化的問題,以避免發生畸波現象。 In addition, when the self-impedance versus frequency curve of the power delivery network is not flat, the problem of rouge waves caused by overlapping voltage disturbances will make the voltage disturbance problem even more serious. A server is an electronic device including a printed circuit board. The power supply layer and the ground layer of the printed circuit board can form a part of the power delivery network. Therefore, the server needs to be considered in the design of the power delivery network of the printed circuit board. In addition to reducing the impedance to avoid noise interference, it is also necessary to consider the issue of impedance flattening to avoid distortion.
實施例提供一種平坦化電源遞送網路之阻抗的方法,包含擷取該電源遞送網路之一組阻抗參數;根據該組阻抗參數求得該電源遞送網路之阻抗;定義目標阻抗;執行重要性計算以決定埠位;根據該目標阻抗及該電源遞送網路之該阻抗,求得交點頻率;根據該交點頻率,選擇去耦電容;及設置該去耦電容於該埠位。 An embodiment provides a method for flattening the impedance of a power delivery network, including acquiring a set of impedance parameters of the power delivery network; obtaining the impedance of the power delivery network according to the set of impedance parameters; defining a target impedance; according to the target impedance and the impedance of the power delivery network, obtain the intersection frequency; according to the intersection frequency, select a decoupling capacitor; and set the decoupling capacitor at the port.
100:方法 100: Method
110至199,310,320,410至450,510至530:步驟 110 to 199, 310, 320, 410 to 450, 510 to 530: Steps
Z11,Z11',Z11’a,Z11’b,Z11’c:阻抗 Z11, Z11', Z11'a, Z11'b, Z11'c: Impedance
Fh:預定頻率 Fh: predetermined frequency
Fx,Fx’,Fx1,Fx2,Fx3:交點頻率 Fx, Fx', Fx1, Fx2, Fx3: Intersection frequency
第1圖為實施例中,平坦化電源遞送網路之阻抗的方法之流程圖。 FIG. 1 is a flowchart of a method for flattening the impedance of a power delivery network in an embodiment.
第2圖為實施例中,阻抗及頻率之關係曲線圖。 Fig. 2 is a graph showing the relationship between impedance and frequency in the embodiment.
第3圖至第5圖為第1圖中,選擇去耦電容之流程圖。 Figures 3 to 5 are the flow charts of the selection of decoupling capacitors in Figure 1.
第6圖為執行第5圖之流程之曲線圖。 FIG. 6 is a graph of executing the process of FIG. 5 .
為了處理前述的難題,可置放去耦合電容以降低電源遞送網路之自阻抗。然而,如此雖可使電源遞送網路之阻抗被降至目標阻抗,但仍未將電源遞送網路之阻抗予以平坦化及最佳化。實施例提供之方法可用以將電源遞送網路之阻抗予以平坦化及最佳化,如下所述。 To address the aforementioned challenges, decoupling capacitors can be placed to reduce the self-impedance of the power delivery network. However, although the impedance of the power delivery network can be reduced to the target impedance, the impedance of the power delivery network has not been flattened and optimized. Embodiments provide methods for planarizing and optimizing the impedance of a power delivery network, as described below.
第1圖為實施例中,平坦化電源遞送網路之阻抗的方法100之流程圖。第2圖為實施例中,阻抗及頻率之關係曲線圖。如第1圖及第2圖所示,方法100可包含以下步驟:步驟110:擷取電源遞送網路之一組阻抗參數;步驟120:根據該組阻抗參數產生電源遞送網路之阻抗Z11;
步驟130:定義目標阻抗Ztarget;步驟140:執行重要性計算,以決定埠位;步驟150:跟據目標阻抗Ztarget及電源遞送網路之阻抗Z11,求得交點頻率Fx;步驟160:根據交點頻率Fx,選擇去耦電容;步驟170:設置去耦電容於埠位;步驟180:執行並聯運算以產生電源遞送網路之調整後阻抗Z11’;步驟190:觀察調整後阻抗Z11’是否符合目標阻抗Ztarget;若是,進入步驟199;若否,進入步驟140;步驟199:結束。
FIG. 1 is a flow diagram of a
以下以舉例方式,描述第1圖之步驟。步驟110中,可擷取電源遞送網路的散射參數(Scattering parameters,又稱S-parameters),且根據散射參數,以計算方式求得阻抗參數,其中阻抗參數可為電源遞送網路之阻抗矩陣(impedance matrix,又稱Z-matrix)的元素(elements)。
The steps of FIG. 1 are described below by way of example. In
步驟120中,可根據該組阻抗參數求得電源遞送網路之阻抗Z11,阻抗Z11之曲線如第2圖所示,阻抗Z11之曲線可呈現此時電源遞送網路於各頻率之自阻抗。第2圖僅為舉例,而非限制實施例之樣態。第2圖中,1e+05可表示1×105,1e+06可表示1×106,以此類推。
In
電源遞送網路可包含多個埠位,阻抗Z11可為耦接於負載裝置(例如積體電路)之埠位的輸入阻抗,且其他埠位可用以設置去耦電容,從而平坦化阻抗Z11,如下所述。 The power delivery network can include multiple ports, the impedance Z11 can be the input impedance of the port coupled to the load device (such as an integrated circuit), and other ports can be used to set decoupling capacitors to flatten the impedance Z11, as described below.
步驟130中,可根據實際需求及產品規格,定義目標阻抗Ztarget,如第2圖所示,目標阻抗Ztarget之曲線可對應於各頻率之目標阻抗值,舉例而言,於低於預定頻率Fh之頻段,目標阻抗Ztarget可實質上為定值。步驟130可獨立於
步驟110及120,舉例而言,亦可先執行步驟130,再執行步驟110及120。
In
根據實施例,如步驟140至170所述,可於電源遞送網路之多個埠位,選擇重要性最高的埠位,再於多個候選電容中,選擇最適宜的電容作為去耦電容,以設置於所選定之埠位。
According to an embodiment, as described in
步驟140中,可分別計算電源遞送網路之複數個埠位被設置電容後,所降低之複數個電感特性值,且挑選複數個電感特性值之最高者所對應的埠位,作為所選之埠位。換言之,於多個埠位中,被設置電容後,電感特性下降最多之埠位,可為重要性最高的埠位。
In
舉例而言,若電源遞送網路為2埠(2-port)網路,具有第一埠位(例如耦接於負載裝置,如積體電路)及第二埠位(例如耦接於去耦電容),則可執行算式eq-1及eq-2之計算:
於表1之舉例中,可見當去耦電容設置於埠位P2時,電感特性降低最多,故埠位P2之重要性最高,且可於步驟140挑選埠位P2。表1之埠位數量及數值僅為舉例,實施例不限於此。
In the example in Table 1, it can be seen that when the decoupling capacitor is set at the port P2, the inductance characteristic decreases the most, so the port P2 is the most important, and the port P2 can be selected in
步驟150中,如第2圖所示,可跟據目標阻抗Ztarget之曲線及此時電源遞送網路之自阻抗Z11之曲線,於阻抗對頻率之曲線圖上,求得交點頻率Fx。
In
步驟160中,可於去耦電容資料庫(library)挑選去耦電容,再於步驟170將所挑選的去耦電容設置於步驟140所決定的埠位。
In
執行步驟170後,電源遞送網路的等效阻抗矩陣之各元素,可因去耦電容之設置而改變,故須重新計算電源遞送網路之自阻抗。
After
舉例而言,若電源遞送網路具有100個埠位及一個耦接於負載裝置(例如積體電路)之埠位,則原本的阻抗矩陣之維度可為101×101,執行步驟170而設置一個去耦電容後,則阻抗矩陣之維度可為100×100,且矩陣之各元素皆可能改變,故須重新產生阻抗矩陣及據以計算自阻抗。
For example, if the power delivery network has 100 ports and one port coupled to a load device (such as an integrated circuit), the dimension of the original impedance matrix can be 101×101, and
步驟180中,可根據步驟170設置的去耦電容,執行並聯運算,以產生電源遞送網路之調整後阻抗Z11’之曲線。所述的並聯運算,可如可如算式eq-5所示:Z11’=Z11-(Z1i×Zi1)/Z11+Zd...eq-5;其中Z11可為調整前之電源遞送網路之自阻抗,Z11’可為設置去耦電容後的調整後之電源遞送網路之自阻抗,Z1i及Zi1可為阻抗矩陣之元素,若矩陣維度為n×n,則i及n為正整數且0<in。Zd可為所設置的去耦電容之阻抗。
In
步驟190中,可觀察調整後阻抗Z11’是否符合目標阻抗Ztarget,若是,可進入步驟199結束流程;若否,則可進入步驟140,再度選擇埠位,及根據調整後交點頻率Fx’選擇及設置適宜的去耦電容於所選的埠位,以使電源遞送網路之阻抗的曲線,於阻抗-頻率坐標上更接近目標阻抗Ztarget的曲線,且更為平坦。
In
步驟190中,可至少根據調整後阻抗Z11’於特定頻段內是否小於目標阻抗Ztarget,以判斷調整後自阻抗Z11’是否符合目標阻抗Ztarget。又,可根據調整後阻抗Z11’於特定頻段內的標準差及平均值,以判斷平坦度是否夠好。舉例而言,可將調整後阻抗Z11’於特定頻段內的標準差及平均值相除後,以百分比表示,以得到平坦度。
In
關於步驟140至190,舉例而言,於步驟140可執行第一重要性計算以決定第一埠位,並如第1圖所示,執行步驟150至180,以設置第一去耦電容於第一埠位及求得調整後阻抗;若於步驟190中,調整後阻抗Z11’尚未符合目標阻抗Ztarget,可再執行步驟140以執行第二重要性計算而決定第二埠位,且再執行執
行步驟150至180以設置第二去耦電容於第二埠位及求得調整後阻抗;如此,可用迴圈方式改善調整後阻抗Z11’之平坦度。此處提及的第一重要性計算及第二重要性計算,僅為舉例,用以描述可用迴圈方式執行第1圖之步驟,然而實施例不限於此,若有須要,第1圖之步驟可用迴圈方式執行更多次(例如多於兩次)重要性計算,從而改善調整後阻抗Z11’之平坦度。於此舉例中,如上述,第一重要性計算可包含分別計算電源遞送網路之複數個埠位被設置電容後,所降低之複數個電感特性值,且挑選複數個電感特性值之最高者所對應的埠位,作為第一埠位;同理,第二重要性計算可包含分別計算電源遞送網路之複數個埠位被設置電容後,所降低之複數個電感特性值,且挑選複數個電感特性值之最高者所對應的埠位,作為第二埠位;若有第三重要性計算、第四重要性計算等,則可依此類推。
Regarding
第3圖為第1圖之步驟160中,選擇去耦電容之流程圖。根據實施例,第1圖之步驟160,可包含以下步驟:步驟310:選擇一組電容,該組電容之每一電容之自諧振頻率(self-resonant frequency,SRF)係介於第一值及第二值之間;步驟320:選擇該組電容之一者為去耦電容。
FIG. 3 is a flowchart of selecting a decoupling capacitor in
第3圖提及之第一值可為交點頻率Fx之A倍,第二值可為交點頻率Fx之B倍,A及B為正參數,且0<A<B。 The first value mentioned in Figure 3 may be A times the intersection frequency Fx, and the second value may be B times the intersection frequency Fx, A and B are positive parameters, and 0<A<B.
舉例來說,若資料庫有200個電容可供選用,其中30個電容的自諧振頻率介於A×Fx至B×Fx之間,則可選用該30個電容之一者作為去耦電容。根據實施例,0.5<A<B<5。根據實施例,A實質上可為1.5,且B實質上可為3。 For example, if there are 200 capacitors for selection in the database, and the self-resonant frequency of 30 capacitors is between A×Fx and B×Fx, one of the 30 capacitors can be selected as the decoupling capacitor. According to the embodiment, 0.5<A<B<5. According to an embodiment, A may be substantially 1.5 and B may be substantially 3.
第4圖為第1圖之步驟160中,選擇去耦電容之流程圖。根據實施例,
第1圖之步驟160,可包含以下步驟:步驟410:選擇k個電容;步驟420:分別計算k個電容之每一電容及電源遞送網路之自阻抗之並聯值,以求得k個並聯阻抗值;步驟430:k個並聯阻抗值中,是否有介於特定範圍之並聯阻抗值?若是,進入步驟440;若否,進入步驟460;步驟440:挑選k個並聯阻抗值中,介於特定範圍之m個並聯阻抗值;步驟450:選擇m個並聯阻抗值對應之m個電容之一者為去耦電容;及步驟460:調整特定範圍,進入步驟430。
FIG. 4 is a flowchart of selecting a decoupling capacitor in
第4圖中,m及k為正整數,且0<mk。步驟430之特定範圍介於目標阻抗Ztarget之α倍至β倍之間,且0<α<β。
In Figure 4, m and k are positive integers, and 0<m k. The specific range of
舉例來說,若將100個候選電容分別設置於第1圖之步驟140決定之埠位,則可求得100個並聯阻抗值,亦即100個電源遞送網路之調整後自阻抗Z11’。而這100個調整後自阻抗Z11’中,若有40個調整後自阻抗可落入α×Ztarget至β×Ztarget之區間,則可將挑選該40調整後自阻抗對應之40個候選電容之一者為去耦電容,而不選擇其餘60個候選電容。
For example, if 100 candidate capacitors are respectively set at the port positions determined in
舉例而言,α可為0.9,且β可為1,若步驟430中,無並聯阻抗值介於特定範圍內,則可將α減小,以增大步驟430所述的特定範圍,從而於步驟430可選到介於特定範圍之並聯阻抗值。舉例而言,可將α由0.9,逐步調整為0.85、0.8、0.75...等,以逐漸增大特定範圍。根據另一實施例,亦可調整α及β,使步驟460調整後的特定範圍相異於調整前的特定範圍。
For example, α can be 0.9, and β can be 1. If in
第5圖為第1圖之步驟160中,選擇去耦電容之流程圖。根據實施例,
第1圖之步驟160,可包含以下步驟:步驟510:分別計算複數個電容之每一電容及電源遞送網路之自阻抗Z11之並聯值,以求得複數條參考阻抗曲線;步驟520:根據複數條參考阻抗曲線及目標阻抗,產生複數個參考交點頻率;及步驟530:選擇複數個參考交點頻率之最高者所對應的電容為去耦電容。
FIG. 5 is a flowchart of selecting a decoupling capacitor in
第6圖可為執行第5圖之流程之曲線圖。第6圖僅為舉例,而非限制實施例之樣態。舉例而言,當三個候選電容分別設置於第1圖之步驟140決定的埠位後,可求得三個參考阻抗Z11’a、Z11’b及Z11’c及其參考阻抗曲線。如第6圖所示,根據目標阻抗Ztarget之曲線及參考阻抗曲線,可得到參考交點頻率Fx1、Fx2及Fx3,其中參考交點頻率Fx3為三個參考交點頻率之最高者。因此,三個候選電容中,對應於參考交點頻率Fx3及參考阻抗Z11’c之曲線之電容,可被選為去耦電容。
FIG. 6 is a graph of executing the process of FIG. 5 . FIG. 6 is only an example, rather than limiting the aspect of the embodiment. For example, after the three candidate capacitors are respectively set at the ports determined in
第3圖、第4圖及第5圖之流程,可用以於電容資料庫逐步選出去耦電容。舉例而言,若有100個候選電容,可先以第3圖之流程,選出30個電容,再以第4圖之流程從該30個電容選出10個電容,之後再以第5圖之流程從該10個電容選出1個電容,作為第1圖之步驟160所選之去耦電容。然而,此僅為舉例,執行第3圖、第4圖及第5圖之流程的順序不限於此。
The process shown in Figure 3, Figure 4, and Figure 5 can be used to select decoupling capacitors step by step from the capacitor database. For example, if there are 100 candidate capacitors, you can first select 30 capacitors using the process in Figure 3, then select 10 capacitors from the 30 capacitors using the process in Figure 4, and then use the process in Figure 5 to select 10 capacitors. One capacitor is selected from the ten capacitors as the decoupling capacitor selected in
綜上,藉由實施例提供的方法,可有效地選擇重要性最高的埠位,及選擇適宜的去耦電容,以設置於所選之埠位。藉由第1圖之迴圈方式,於適宜的埠位設置適宜的去耦電容後,可有利於平坦化電源遞送網路之自阻抗。根據實驗,實施例之方法所得的調整後阻抗Z11’於阻抗-頻率坐標之曲線,可較為接近目標阻抗Ztarget之曲線,亦即具有更佳的平坦度。因此,實施例之方法可有效 避免畸波現象。因此,對於處理本領域之難題,實有助益。 In conclusion, with the method provided by the embodiments, the most important port position can be effectively selected, and an appropriate decoupling capacitor can be selected to be set at the selected port position. With the loop method shown in Figure 1, after setting a suitable decoupling capacitor at a suitable port position, it can help to flatten the self-impedance of the power delivery network. According to experiments, the curve of the adjusted impedance Z11' on the impedance-frequency coordinate obtained by the method of the embodiment can be closer to the curve of the target impedance Ztarget, that is, has better flatness. Therefore, the method of the embodiment can be effective Avoid distortion. Therefore, it is helpful to deal with the problems in this field.
本發明之方法可應用在伺服器的印刷電路板的設計上,讓伺服器具有高品質的電源遞送網路,以增進伺服器的穩定性,使伺服器能應用在人工智慧(Artificial Intelligence,簡稱AI)運算、邊緣運算(Edge Computing),亦可當作5G伺服器、雲端伺服器或車聯網伺服器使用。 The method of the present invention can be applied to the design of the printed circuit board of the server, so that the server has a high-quality power delivery network, so as to improve the stability of the server, so that the server can be applied to artificial intelligence (Artificial Intelligence, referred to for short). AI) computing, edge computing (Edge Computing), can also be used as 5G server, cloud server or car networking server.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
100:方法 100: Method
110至199:步驟 110 to 199: Steps
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