CN108666315A - A kind of flash memory and its manufacturing method - Google Patents
A kind of flash memory and its manufacturing method Download PDFInfo
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- CN108666315A CN108666315A CN201710207737.4A CN201710207737A CN108666315A CN 108666315 A CN108666315 A CN 108666315A CN 201710207737 A CN201710207737 A CN 201710207737A CN 108666315 A CN108666315 A CN 108666315A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
The embodiment of the invention discloses a flash memory and its manufacturing methods, are related to technical field of semiconductor memory, and wherein manufacturing method includes：Semi-conductive substrate is provided, it includes gate regions, source area and drain region that semiconductor substrate, which has isolated area and active area, active area, has the floating boom and control gate of stacking insulation set on gate regions；Doped ions are injected in source area；Separation layer is formed on the side wall of the floating boom and control gate of isolated area and stacking insulation set；Isolated area in source area and source area both sides forms doped polysilicon layer.Flash memory provided in an embodiment of the present invention and its manufacturing method, conductive trench using doped polysilicon layer as source area, instead of the ion implanting conductive trench easily influenced by photoresist, solves influences of the photoresist remnants in source electrode etching to source resistance, improve the reliability of device.
Description
Technical field
The present embodiments relate to technical field of semiconductor memory more particularly to a kind of flash memory and its manufacturing methods.
Background technology
Using self-aligned source (Self Aligned Source, SAS) technique make flash memory (floating gate type device) although
It is simple for process at low cost, but since the depth-to-width ratio in formation source electrode when institute etching groove is very high, cause in source electrode etching process
Photoresist (Photo Resist) remnants Hen Nan Cheongju it is clean, and these remaining photoresists can hinder subsequent source ion injection
(Source Implant), causes the electric current of certain storage units in flash memory relatively low, the electric current of the storage unit in this flash memory
The inhomogeneities of distribution will seriously affect the operational efficiency and reliability of flash memory, such as read-write number.With storage unit volume
It further reduces, the drawback of this photoresist remnants can be increasingly severe.
Therefore it provides a kind of flash memory that can solve above-mentioned photoresist residual defect is necessary.
Invention content
A kind of flash memory of offer of the embodiment of the present invention and its manufacturing method, can lead to certain in flash memory deposit to solve photoresist remnants
The relatively low problem of the electric current of storage unit.
In a first aspect, an embodiment of the present invention provides a kind of manufacturing methods of flash memory, including：Semi-conductive substrate is provided,
The semiconductor substrate has isolated area and active area, and the active area includes gate regions, source area and drain region, the grid
There is the floating boom and control gate of stacking insulation set in area；Doped ions are injected in the source area；In the isolated area and
Separation layer is formed on the floating boom of the stacking insulation set and the side wall of control gate；In the source area and the source area two
The isolated area of side forms doped polysilicon layer.
Optionally, described before the source area injects Doped ions in above-mentioned manufacturing method, including：Using dry
Method etching technics removes the megohmite insulant filled in the isolated area.
Optionally, in above-mentioned manufacturing method, it is described in the isolated area and it is described stacking insulation set floating boom and
Separation layer is formed on the side wall of control gate includes：In the groove of the isolated area and it is described stacking insulation set floating boom
Separating film layer is formed on the side wall of control gate and surface；The separating film layer of the control gate upper surface is removed so that the control
Expose the upper surface of grid.
Optionally, in above-mentioned manufacturing method, the isolated area shape in the source area and the source area both sides
Include at doped polysilicon layer：Doped polycrystalline silicon film is formed on the semiconductor substrate；Made using flatening process described
Doped polycrystalline silicon film is concordant with the upper surface of the separation layer and the control gate；Remove the drain region and the drain electrode
The doped polycrystalline silicon film formed in the isolated area of area both sides, makes the surface of the drain region expose.
Optionally, in above-mentioned manufacturing method, the drain region and the drain region are removed using dry etch process
Doped polycrystalline silicon film in the isolated area of both sides.
Optionally, in above-mentioned manufacturing method, the separation layer is the oxide skin(coating) and nitride layer sequentially formed.
Optionally, it in above-mentioned manufacturing method, is insulated in the isolated area and the stacking using high temperature oxidation process
The oxide skin(coating) is formed on the floating boom of setting and the side wall of control gate；It is formed in the oxide layer surface using furnace process
The nitride layer.
Optionally, in above-mentioned manufacturing method, the thickness of the oxide skin(coating) isThe nitride layer
Thickness be
Optionally, in above-mentioned manufacturing method, the doped polysilicon layer is formed using low-pressure chemical vapor deposition process.
Second aspect, an embodiment of the present invention provides a kind of flash memories, including：Semiconductor substrate, the semiconductor substrate tool
It includes gate regions, source area and drain region to have isolated area and active area, the active area, has stacking insulation on the gate regions
The floating boom and control gate of setting；Source area is injected with Doped ions；Separation layer is formed in the isolated area and the stacking
On the floating boom of insulation set and the side wall of control gate；Doped polysilicon layer is formed in the source area and the source area two
In the isolated area of side.
Flash memory provided in an embodiment of the present invention and its manufacturing method, first source area inject Doped ions, then every
Separation layer is formed on side wall from the floating boom and control gate of area and stacking insulation set, then in source area and source area
The isolated areas of both sides forms doped polysilicon layer, the conductive trench using doped polysilicon layer as source area, instead of easily by
The ion implanting conductive trench that photoresist influences solves influences of the photoresist remnants in source electrode etching to source resistance, improves
The reliability of device.
Description of the drawings
Fig. 1 is a kind of flow diagram of the manufacturing method for flash memory that the embodiment of the present invention one provides；
Fig. 2 is a kind of structural schematic diagram for flash memory that the embodiment of the present invention one provides；
Fig. 3 A be in Fig. 2 flash memory after forming control gate along the cross-sectional view of hatching A-A'；
Fig. 3 B be in Fig. 2 flash memory after forming control gate along the cross-sectional view of hatching B-B'；
Fig. 3 C be in Fig. 2 flash memory source area inject Doped ions after along hatching A-A' cross-sectional view；
Fig. 3 D be in Fig. 2 flash memory source area inject Doped ions after along hatching B-B' cross-sectional view；
Fig. 3 E be in Fig. 2 flash memory after forming separation layer along the cross-sectional view of hatching A-A'；
Fig. 3 F be in Fig. 2 flash memory after forming separation layer along the cross-sectional view of hatching B-B'；
Fig. 3 G be in Fig. 2 flash memory after forming doped polysilicon layer along the cross-sectional view of hatching A-A'；
Fig. 3 H be in Fig. 2 flash memory after forming doped polysilicon layer along the cross-sectional view of hatching B-B'；
Fig. 4 is that flash memory forms the section along hatching A-A' after separating film layer on the side wall of control gate and surface in Fig. 2
Structural schematic diagram；
Fig. 5 A are that flash memory forms the section knot along hatching A-A' after doped polycrystalline silicon film on a semiconductor substrate in Fig. 2
Structure schematic diagram；
Fig. 5 B are that flash memory removes the cross-sectional view along hatching A-A' after extra doped polycrystalline silicon film in Fig. 2；
Fig. 5 C are the cross-sectional views after flash memory formation mask plate along hatching A-A' in Fig. 2；
Fig. 6 is a kind of structural schematic diagram of flash memory provided by Embodiment 2 of the present invention.
Specific implementation mode
The embodiment of the present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this
The described specific embodiment in place is only used for explaining the embodiment of the present invention, rather than the restriction to the embodiment of the present invention.In addition it also needs
It is noted that illustrating only for ease of description, in attached drawing and the relevant part of the embodiment of the present invention rather than entire infrastructure.
Embodiment one
Fig. 1 is a kind of flow diagram of the manufacturing method for flash memory that the embodiment of the present invention one provides.With reference to figure 1, this hair
The manufacturing method for the flash memory that bright embodiment provides specifically comprises the following steps：
Step 110 provides semi-conductive substrate, and semiconductor substrate has isolated area and active area, and active area includes grid
Area, source area and drain region have the floating boom and control gate of stacking insulation set on gate regions.
Fig. 2 is a kind of structural schematic diagram for flash memory that the embodiment of the present invention one provides, and with reference to figure 2, flash memory includes control in Fig. 2
Grid 11 and active area 12 processed, active area 12 include drain region 121, source area 122 and gate regions 123.For arbitrary neighborhood two
Region between active area 12, the region for being located at 122 both sides of source area are the isolated area 131 adjacent with source area 122, are located at leakage
The region of 121 both sides of polar region is the isolated area 131 adjacent with drain region 121.
Fig. 3 A are that flash memory is illustrated after forming control gate along the cross-sectional view of hatching A-A', Fig. 3 A in Fig. 2
The structures such as the floating boom 15 for drawing two adjacent flash cells and control gate 11 of property, the active area in Fig. 3 A in semiconductor substrate 13
12 include drain region 121, source area 122 and gate regions 123, has floating boom 15 and the control of stacking insulation set on gate regions 123
Grid 11 processed.In addition, tunnel oxide 14 is usually provided between gate regions 123 and floating boom 15, between control gate 11 and floating boom 15
It is usually provided with insulating layer 16.Fig. 3 B be in Fig. 2 flash memory after forming control gate along the cross-sectional view of hatching B-B',
There is in Fig. 3 B in semiconductor substrate 13 source area 122 and isolated area 131.
Step 120 injects Doped ions in source area.Fig. 3 C are flash memory edges after source area injects Doped ions in Fig. 2
The cross-sectional view of hatching A-A', Fig. 3 D be in Fig. 2 flash memory source area inject Doped ions after along hatching B-B'
Cross-sectional view source ion injection is carried out in source area 122 with reference to figure 3C and 3D.It should be noted that in source
When polar region 122 injects Doped ions, Doped ions can be also injected into the isolated area 131 of 122 both sides of source area or can also
Doped ions are not injected into, Fig. 3 D are the schematic diagram for injecting Doped ions.
Step 130 forms separation layer on the side wall of the floating boom and control gate of isolated area and stacking insulation set.Figure
3E is that for flash memory along the cross-sectional view of hatching A-A' after forming separation layer, Fig. 3 F are that flash memory is being formed in Fig. 2 in Fig. 2
Along the cross-sectional view of hatching B-B' after separation layer, it is being isolated after completing source ion injection with reference to figure 3E and 3F
Area 131 and stacking insulation set floating boom 15 and control gate 11 side wall on be formed with separation layer 17.
Step 140, the isolated area in source area and source area both sides form doped polysilicon layer.Fig. 3 G are dodged in Fig. 2
In the presence of the cross-sectional view formed after doped polysilicon layer along hatching A-A', Fig. 3 H are that flash memory is adulterated being formed in Fig. 2
Along the cross-sectional view of hatching B-B' after polysilicon layer, with reference to figure 3G and 3H, in source area 122 and source area 122
The isolated area 131 of both sides forms doped polysilicon layer 18, is drawn source electrode using doped polysilicon layer 18.
The manufacturing method of flash memory provided in an embodiment of the present invention is injected Doped ions in source area first, is then being isolated
Separation layer is formed on the side wall of the floating boom and control gate of area and stacking insulation set, then in source area and source area two
The isolated area of side forms doped polysilicon layer, the conductive trench using doped polysilicon layer as source area, instead of easy light
The ion implanting conductive trench influenced is hindered, influences of the photoresist remnants in source electrode etching to source resistance is solved, improves device
The reliability of part.
Optionally, on the basis of the above embodiments, described before the source area injects Doped ions, including：It adopts
The megohmite insulant filled in the isolated area is removed with dry etch process.Dry etch process is preferably used in the present embodiment
The megohmite insulant filled in removal isolated area.
Optionally, on the basis of the above embodiments, it is described in the isolated area and the stacking insulation set it is floating
Separation layer is formed on the side wall of grid and control gate includes：In the groove of the isolated area and the stacking insulation set
Separating film layer is formed on the side wall and surface of floating boom and control gate；The separating film layer of the control gate upper surface is removed so that described
Expose the upper surface of control gate.Fig. 4 is that flash memory is formed after separating film layer on the side wall of control gate and surface along hatching in Fig. 2
The cross-sectional view of A-A', with reference to figure 4, the shape on the floating boom 15 of stacking insulation set and the side wall of control gate 11 and surface
After separating film layer 171, need to remove the separating film layer 171 on 11 surface of control gate.After removing extra separating film layer 171,
With reference to figure 3E and 3F, remaining separating film layer is in the groove of isolated area 131 and on the side wall of floating boom 15 and control gate 11
For separation layer 17.
Optionally, on the basis of the above embodiments, the isolation in the source area and the source area both sides
Area forms doped polysilicon layer：Doped polycrystalline silicon film is formed on the semiconductor substrate；Made using flatening process
The doped polycrystalline silicon film is concordant with the upper surface of the separation layer and the control gate；Remove the drain region and described
The doped polycrystalline silicon film formed in the isolated area of drain region both sides, makes the surface of the drain region expose.
Fig. 5 A are that flash memory forms the section knot along hatching A-A' after doped polycrystalline silicon film on a semiconductor substrate in Fig. 2
Structure schematic diagram forms doped polycrystalline silicon film 181, doped polycrystalline silicon film 181 with reference to figure 5A first in semiconductor substrate 13
The surface of covering semiconductor substrate 13, separation layer 17 and control gate 11, preferably uses low-pressure chemical vapor deposition process shape
It is about at thicknessDoped polycrystalline silicon film 181.
Fig. 5 B are that flash memory removes the cross-sectional view along hatching A-A' after extra doped polycrystalline silicon film in Fig. 2,
With reference to figure 5B, using flatening process processing doped polycrystalline silicon film 181, separation layer 17 and control gate 11, so that remaining
The upper surface of doped polycrystalline silicon film 181, separation layer 17 and control gate 11 is concordant.
Fig. 5 C are the cross-sectional views in Fig. 2 after flash memory formation mask plate along hatching A-A' to be made with reference to figure 5C
After the upper surface of doped polycrystalline silicon film 181, separation layer 17 and control gate 11 is concordant, mask layer 19 is utilized to remove drain region
121 and 121 both sides of drain region isolated area on the doped polycrystalline silicon film 181 that is formed；With reference to figure 3G and 3H, it is not required in removal
After the doped polycrystalline silicon film 181 wanted, the doped polycrystalline silicon fiml in the isolated area 131 of 122 both sides of source area 122 and source area
Layer 181 is doped polysilicon layer 18.
Optionally, on the basis of the above embodiments, with reference to figure 5C, the drain region is removed using dry etch process
121 and 121 both sides of the drain region isolated area 131 on doped polycrystalline silicon film 181.
Optionally, on the basis of the above embodiments, the separation layer is the oxide skin(coating) and nitride layer sequentially formed.
In the present embodiment, separation layer is made of the oxide skin(coating) and nitride layer sequentially formed, compared with simple oxide skin(coating), energy
Play better buffer action.
Optionally, it in above-mentioned manufacturing method, is insulated in the isolated area and the stacking using high temperature oxidation process
The oxide skin(coating) is formed on the floating boom of setting and the side wall of control gate；It is formed in the oxide layer surface using furnace process
The nitride layer.In the present embodiment, it is preferred to use high temperature oxidation process forms oxide skin(coating), it is preferred to use furnace process shape
At nitride layer.
Optionally, on the basis of the above embodiments, the thickness of the oxide skin(coating) isThe nitridation
The thickness of nitride layer isSpecifically, the thickness of oxide skin(coating) and nitride layer needs to carry out according to actual needs
It determines, for example needs to consider the size of flash cell, the factors such as isolation effect.In the present embodiment, oxide skin(coating) is excellent
The thickness is selected to beThe preferred thickness of nitride layer is
Optionally, on the basis of the above embodiments, the doped polycrystalline is formed using low-pressure chemical vapor deposition process
Silicon layer.
Embodiment two
Fig. 6 is a kind of structural schematic diagram of flash memory provided by Embodiment 2 of the present invention, on the basis of the above embodiments, ginseng
Fig. 6 is examined, which includes：Semiconductor substrate 61, floating boom 64, control gate 66, separation layer 67 and doped polysilicon layer 68.
With reference to figure 6, flash memory provided in this embodiment specifically includes：
Semiconductor substrate 61, the semiconductor substrate 61 has isolated area (being not shown in Fig. 6) and active area 62, described to have
Source region 62 includes drain region 621, source area 622 and gate regions 623, has the floating of stacking insulation set on the gate regions 623
Grid 64 and control gate 66；Source area 622, is injected with Doped ions；Separation layer 67 is formed in the isolated area and the stacking
On the floating boom 64 of insulation set and the side wall of control gate 66；Doped polysilicon layer 68 is formed in the source area 622 and described
In the isolated area of 622 both sides of source area.
It should be noted that with reference to figure 6, tunnel oxide would generally be provided between semiconductor substrate 61 and floating boom 64
63, insulating layer 65 would generally be provided between floating boom 64 and control gate 66.
Flash memory provided in an embodiment of the present invention injects Doped ions in source area first, then in isolated area and stacking
Separation layer is formed on the floating boom of insulation set and the side wall of control gate, then in the isolated area shape of source area and source area both sides
At doped polysilicon layer, the conductive trench using doped polysilicon layer as source area, instead of the ion easily influenced by photoresist
Conductive trench is injected, influences of the photoresist remnants in source electrode etching to source resistance is solved, improves the reliability of device.
Since the flash memory of the present embodiment can be made by the manufacturing method of the flash memory provided in the various embodiments described above, so can
With the content in reference the various embodiments described above, in order to be easier to understand the structure of the flash memory provided in the present embodiment.
Note that above are only preferred embodiment and the institute's application technology principle of the embodiment of the present invention.Those skilled in the art
It will be appreciated that the embodiment of the present invention is not limited to specific embodiment described here, can carry out for a person skilled in the art each
The protection domain that kind significantly changes, readjusts and substitutes without departing from the embodiment of the present invention.Therefore, although more than passing through
Embodiment is described in further detail the embodiment of the present invention, but the embodiment of the present invention is not limited only to the above implementation
Example can also include other more equivalent embodiments in the case where not departing from design of the embodiment of the present invention, and the present invention is implemented
The range of example is determined by scope of the appended claims.
Claims (10)
1. a kind of manufacturing method of flash memory, which is characterized in that including：
Semi-conductive substrate is provided, the semiconductor substrate has isolated area and active area, and the active area includes gate regions, source
Polar region and drain region have the floating boom and control gate of stacking insulation set on the gate regions；
Doped ions are injected in the source area；
Separation layer is formed on the side wall of the floating boom and control gate of the isolated area and the stacking insulation set；
Isolated area in the source area and the source area both sides forms doped polysilicon layer.
2. manufacturing method according to claim 1, which is characterized in that it is described the source area injection Doped ions it
Before, including：
The megohmite insulant filled in the isolated area is removed using dry etch process.
3. manufacturing method according to claim 2, which is characterized in that described in the isolated area and the stacking is exhausted
Forming separation layer on the floating boom of edge setting and the side wall of control gate includes：
It is formed in the groove of the isolated area and on the side wall and surface of the floating boom of the stacking insulation set and control gate
Separating film layer；
The separating film layer of the control gate upper surface is removed so that the upper surface of the control gate is exposed.
4. manufacturing method according to claim 3, which is characterized in that described in the source area and the source area two
The isolated area of side forms doped polysilicon layer：
Doped polycrystalline silicon film is formed on the semiconductor substrate；
Keep the doped polycrystalline silicon film concordant with the upper surface of the separation layer and the control gate using flatening process；
The doped polycrystalline silicon film formed in the isolated area of the drain region and the drain region both sides is removed, is made described
Expose on the surface of drain region.
5. manufacturing method according to claim 4, which is characterized in that use dry etch process remove the drain region with
And the doped polycrystalline silicon film in the isolated area of the drain region both sides.
6. manufacturing method according to claim 1, which is characterized in that the separation layer be the oxide skin(coating) that sequentially forms and
Nitride layer.
7. manufacturing method according to claim 6, which is characterized in that using high temperature oxidation process in the isolated area and
The oxide skin(coating) is formed on the floating boom of the stacking insulation set and the side wall of control gate；
The nitride layer is formed in the oxide layer surface using furnace process.
8. manufacturing method according to claim 6, which is characterized in that the thickness of the oxide skin(coating) is
The thickness of the nitride layer is
9. manufacturing method according to claim 1, which is characterized in that formed using low-pressure chemical vapor deposition process described
Doped polysilicon layer.
10. a kind of flash memory, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate have isolated area and active area, the active area include gate regions, source area and
Drain region has the floating boom and control gate of stacking insulation set on the gate regions；
Source area is injected with Doped ions；
Separation layer is formed on the floating boom of the isolated area and the stacking insulation set and the side wall of control gate；
Doped polysilicon layer is formed in the isolated area of the source area and the source area both sides.
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Address after: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee before: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |