CN105826272B - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN105826272B CN105826272B CN201510012071.8A CN201510012071A CN105826272B CN 105826272 B CN105826272 B CN 105826272B CN 201510012071 A CN201510012071 A CN 201510012071A CN 105826272 B CN105826272 B CN 105826272B
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Abstract
The present invention provides a kind of semiconductor devices and forming method thereof, wherein, the forming method of semiconductor devices includes: after forming FGS floating gate structure on a semiconductor substrate, ion doping is carried out to the FGS floating gate structure surface, to form the first insulating layer, covering forms second insulating layer on first insulating layer later, and forms control grid structure on the second insulating layer.First insulating layer and second insulating layer can be improved FGS floating gate structure and control the insulation effect between grid structure, reduces FGS floating gate structure and controls the leaky between grid structure, and then promotes the performance of the device of such as nand memory.
Description
Technical field
The present invention relates to field of semiconductor manufacture technologies, in particular to semiconductor devices and forming method thereof.
Background technique
Nonvolatile memory is a kind of semiconductor memory, when power supply is removed, still sustainable storage data.
Wherein, the common a kind of nonvolatile memory of nand memory, the storage of memory cell small with memory cell area
It measures the advantages that big, thus is widely used in MP3 player, digital camera, digital video camera-recorder and mobile phone etc. just
In the storage card for taking formula electronic product.
Fig. 1 is a flat surface floating gate NAND structural schematic diagram.With reference to Fig. 1, including floating gate over the semiconductor substrate 10 is arranged
11, the control gate 13 above floating gate, and the metal plug 12 on floating gate.Wherein, floating gate 11 is used to store electronics,
To realize reading and writing data；Metal plug is set on the control gate 13, to import external voltage, the shape in the nand memory
At electric field, enter or leave floating gate 11 for controlling electronics.
It is the enlarged structure schematic diagram of floating gate 11 and 13 convergence part of control gate in Fig. 1 in conjunction with reference Fig. 2, Fig. 2.In floating gate 11
Dielectric layer 14 is set between control gate 13, to play the role of electronic isolation.In the prior art, the dielectric layer 14 is mostly to aoxidize
Object-Nitride Oxide (Oxide-Nitride-Oxide, abbreviation ONO) structure.
But with semiconductor device development, the characteristic dimension of semiconductor devices constantly reduces, the thickness of injected media layer 14
Also constantly reduce.In the nand memory use process formed using prior art, between floating gate 11 and control gate 13 often
Often there is leaky, to influence nand memory performance.
How to reduce in nand memory thus, the leaky between floating gate 11 and control gate 13 is those skilled in the art
The problem of member's urgent need to resolve.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, to effectively reduce floating gate and control
Leaky between grid.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising:
Semiconductor substrate is provided；
FGS floating gate structure is formed on the semiconductor substrate；
Ion doping is carried out to the surface of the FGS floating gate structure, forms the first insulating layer；
Second insulating layer is formed on the first insulating layer；
Control grid structure is formed over the second dielectric.
Optionally, the step of forming FGS floating gate structure on the semiconductor substrate includes: shape on the semiconductor substrate
At there are multiple FGS floating gate structures, formed between adjacent FGS floating gate structure fluted；
Before the surface doping ion of the FGS floating gate structure the step of, the forming method further include: in the groove-bottom
Portion forms barrier layer, and the barrier layer surface is lower than the FGS floating gate structure surface；
After the step of surface to the FGS floating gate structure carries out ion doping, before forming the second insulating layer, institute
State the forming method of semiconductor devices further include: remove the barrier layer.
Optionally, the barrier layer is photoresist layer.
Optionally, the step of forming the barrier layer includes: to cover the semiconductor substrate with diluted photoresist solution；
Heating process is carried out later, removes partial solvent, and the barrier layer surface in the groove is made to be lower than the FGS floating gate structure surface, with
Form the photoresist layer for covering the bottom portion of groove.
Optionally, the temperature of the heating process is 120~180 DEG C.
Optionally, after carrying out heating process, the photoresist layer of segment thickness is removed, with the described floating of exposed portion thickness
Grid structure.
Optionally, the photoresist layer of segment thickness is removed, includes: with the step of FGS floating gate structure of exposed portion thickness
Using ammonium hydroxide, hydrogen peroxide aqueous solution as wet etchant, part photoresist layer is removed with wet-etching technology；The wet process
In etching agent, the volume ratio of ammonium hydroxide, hydrogen peroxide and water is 1:1~5:10~50.
Optionally, the step of removing the barrier layer includes: using the solution for containing ozone as wet etchant, with wet
Method etching technics removes the barrier layer；The concentration of ozone is 10~100ppm in the wet etchant.
Optionally, the barrier layer with a thickness of
Optionally, after carrying out ion doping to the surface of the FGS floating gate structure, the forming method further include: moved back
Fire process, to promote the FGS floating gate structure to react with the ion.
Optionally, the temperature of the annealing process is 800~900 DEG C, and the time is 20~60 minutes.
Optionally, the ion is Nitrogen ion.
Optionally, first insulating layer with a thickness of
Optionally, the method for the ion doping is ion implanting；In the step of ion implanting: implantation dosage 10 ×
1015~20 × 1015atom/cm2, power is 1500~2000W.
Optionally, the step of forming second insulating layer includes: to sequentially form the first silica on the first insulating layer
Layer, silicon nitride layer and the second silicon oxide layer.
The present invention also provides a kind of semiconductor devices, comprising:
Semiconductor substrate；
FGS floating gate structure in the semiconductor substrate；
The first insulating layer on the FGS floating gate structure, first insulating layer are to carry out ion to the FGS floating gate structure
What doping was formed；
Positioned at the second insulating layer of first surface of insulating layer；
Control grid structure in the second insulating layer.
Optionally, first insulating layer is covered on the surface of the FGS floating gate structure and the part side of the FGS floating gate structure
Wall；
The second insulating layer is covered in the FGS floating gate structure that on first insulating layer and first insulating layer exposes
On side wall.
Selection of land, first insulating layer with a thickness of
Optionally, first insulating layer is silicon nitride layer.
Optionally, the second insulating layer includes the first oxide skin(coating), the nitride being sequentially located on the FGS floating gate structure
Layer and the second oxide skin(coating).
Compared with prior art, technical solution of the present invention has the advantage that
After forming FGS floating gate structure on a semiconductor substrate, in the FGS floating gate structure surface doping ion, to form first absolutely
Edge layer, covering forms second insulating layer on first insulating layer later, and forms control on the second insulating layer
Grid structure.First insulating layer and second insulating layer can be improved in the devices such as the nand memory being subsequently formed,
Insulation effect between FGS floating gate structure and control grid structure reduces FGS floating gate structure and controls the leaky between grid structure；And
First insulating layer is formed using ion implanting mode, can effectively reduce and form blocking on the FGS floating gate structure using depositional mode
Generated stress effect when layer, and then promote the performance of semiconductor device formed.
Further, in the forming method of semiconductor devices, to before FGS floating gate structure surface doping ion, first in semiconductor
Bottom portion of groove covering barrier layer on substrate between each FGS floating gate structure.Subsequent to the FGS floating gate structure surface doping ion process
In, the barrier layer can protect each FGS floating gate structure bottom portion of groove, avoid causing the groove-bottom between FGS floating gate structure during ion doping
Portion is damaged, to further increase the device performances such as the nand memory being subsequently formed.
Detailed description of the invention
Fig. 1 is the electron microscope of existing plane floating gate NAND；
Fig. 2 is the enlarged structure schematic diagram of floating gate and control gate convergence part in Fig. 1；
Fig. 3 to Figure 11 is the structural schematic diagram of one embodiment of forming method of semiconductor devices of the present invention.
Specific embodiment
It can be seen from background technology that it is existing that electric leakage occurs between floating gate and control gate in the nand memory that the prior art is formed
As to influence the performance of nand memory.Its reason is analyzed, is the discovery that floating gate and control as dimensions of semiconductor devices reduces
Dielectric layer (ONO) thickness between grid processed reduces and affects the insulating properties of dielectric layer, so as to cause between floating gate and control gate
Leaky.
But directly increase the ONO layer thickness being deposited on floating gate according to the prior art, because ONO layer is larger to answer masterpiece
With will affect the structure of floating gate and control gate, to influence the performance of NAND to be formed.
For this purpose, the present invention provides a kind of semiconductor devices and forming method thereof, the forming method of the semiconductor devices
Include:
After forming multiple FGS floating gate structures on a semiconductor substrate, ion doping, shape are carried out to the surface of the FGS floating gate structure
At the first insulating layer；Second insulating layer is formed on the first insulating layer, forms control gate knot on the second insulating layer
Structure.
In the FGS floating gate structure surface doping ion, to form the first insulating layer, later on first insulating layer
Covering forms second insulating layer, and controls grid structure in being formed in the second insulating layer.First insulating layer and second is absolutely
Edge layer can be improved it is described be subsequently formed in nand memory, insulation effect between floating gate and control gate reduces FGS floating gate structure and control
Leaky between grid structure processed；And the first insulating layer is formed using ion implanting mode, it can effectively reduce using deposition
Mode generated stress effect when forming barrier layer on the FGS floating gate structure, and then promote the property of the semiconductor devices formed
Energy.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 11 is the semiconductor device in each step of forming method for the semiconductor devices that one embodiment of the invention provides
The schematic diagram of the section structure of part.
Referring to FIG. 3, providing semiconductor substrate 100.
In the present embodiment, the semiconductor substrate 100 is silicon substrate, in other embodiments the semiconductor substrate 100
It can also be that germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate, common semiconductor substrate can be used as in the present embodiment
Semiconductor substrate.
In addition, the structures such as several epitaxial interface layers or strained layer can also be formed in the semiconductor substrate surface to improve
The electric property of semiconductor devices.Above structure does not influence protection scope of the present invention
With continued reference to Fig. 3, FGS floating gate structure is formed on the surface of the semiconductor substrate 100, is used to form nand memory
Floating gate.
In the present embodiment, the FGS floating gate structure includes the tunnel layer 110 being formed in semiconductor substrate 100, is located at described
Floating gate layer 120 on tunnel layer 110.
Optionally, the material of the tunnel layer 110 is silica；The material of the floating gate layer 120 is polysilicon.
In the present embodiment, be formed with multiple FGS floating gate structures in the semiconductor substrate 100, adjacent FGS floating gate structure it
Between form fluted 140.
Optionally, in the semiconductor substrate 100, shallow trench isolation is formed between two neighboring FGS floating gate structure
Structure (STI) 130, to electrically isolate two neighboring FGS floating gate structure.
The step of forming the FGS floating gate structure and fleet plough groove isolation structure include:
Silicon oxide layer (to form tunnel layer) first is covered on 100 surface of semiconductor substrate, in the silicon oxide layer
Upper formation polysilicon layer (to form floating gate layer)；
Form mask graph on the polysilicon layer, and using the mask graph as polysilicon layer described in mask etching,
Silicon oxide layer and semiconductor substrate 100 form the floating gate layer 120 and tunnel layer 110 on the semiconductor substrate with shape
It is formed at the FGS floating gate structure, and in the semiconductor substrate between two neighboring FGS floating gate structure to form shallow trench isolation knot
The groove of structure；
The insulating layer materials such as silica or silicon nitride are filled in the groove of the semiconductor substrate, described in being formed
Fleet plough groove isolation structure 130 removes the mask graph later.
In the present embodiment, the upper surface of the fleet plough groove isolation structure 130 is higher than 100 surface of semiconductor substrate, i.e.,
Higher than the lower surface of the FGS floating gate structure, effect is electrically isolated between two neighboring FGS floating gate structure to improve.
The silicon oxide layer, polysilicon layer formation process include chemical vapor deposition, physical vapour deposition (PVD) or atomic layer
Depositing operation；The method for etching the polysilicon layer, silicon oxide layer and semiconductor substrate 100 includes dry etching；To described half
The method of the filling insulating layer materials such as silica or silicon nitride is chosen as the side such as chemical vapor deposition in the groove of conductor substrate
Method；The material of the mask graph is chosen as silicon nitride；The method for removing the mask graph can be use phosphoric acid solution for
The wet-etching technology of wet etchant, above steps are this field mature technology, and details are not described herein.
In conjunction with reference Fig. 4 to Fig. 8, later, ion doping is carried out on the surface of the FGS floating gate structure, to form first absolutely
Edge layer.
In the present embodiment, the ion is nitrogen (N) ion.
First insulating layer is to react shape with the floating gate layer 120 behind 120 surface of floating gate layer described in the N ion implanting
At silicon nitride layer.
In the present embodiment, the method for carrying out ion doping to 120 surface of floating gate layer is ion implanting, optionally, institute
Ion implanting is stated as using plasma injection.Specific steps include: that reaction gas (such as nitrogen) is passed through plasma
In device, formed comprising after Nitrogen ion plasma, the plasma to be injected to the surface of the floating gate layer 120.
In plasma implantation process, if plasma enters 140 bottom of groove between each FGS floating gate structure (i.e.
Each 130 surface of fleet plough groove isolation structure), it causes to will cause the damage of fleet plough groove isolation structure 130, the NAND being subsequently formed is caused to tie
There is leaky in structure, to influence the nand memory performance being subsequently formed.
In the present embodiment, after forming the FGS floating gate structure, ion doping technique is carried out to the surface of the FGS floating gate structure
Before, first barrier layer 220 is formed on 140 bottom of groove between each FGS floating gate structure.The FGS floating gate structure surface is carried out subsequent
During ion doping, the barrier layer 220 can protect bottom portion of groove between each FGS floating gate structure, avoid causing during ion doping
Bottom portion of groove (i.e. sti structure) between each FGS floating gate structure is damaged.
In the present embodiment, the barrier layer 220 is photoresist layer.
In conjunction with reference Fig. 4~6, in the present embodiment, the forming step on the barrier layer 220 includes:
With reference to Fig. 4, diluted photoresist solution first is covered on the surface of the semiconductor substrate 100, forms the first photoetching
Glue-line 200.
Optionally, methyl proxitol (PGME) or propylene glycol methyl ether acetate can be built into conventional lithographic glue
(PGMEA) etc. organic solvents form diluted photoresist solution to dilute photoresist.Wherein, the organic solvent of merging and often
Volume ratio between the photoresist of rule is 5:1~10:1.
Contain more solvent in first photoresist layer 200, and covers the FGS floating gate structure.
Fig. 5 is referred to later, is carried out heating process, is removed the partial solvent in the photoresist 200, make first photoetching
The thickness of glue-line is thinned, and forms the second photoresist layer 210, so that being located at the second photoresist layer of part 210 in the groove 140
Surface is lower than 120 upper surface of floating gate layer.
In the present embodiment, the temperature of the heating process is 120~180 DEG C, thus effectively removing the first photoresist layer
Solvent in 200, the thickness to reduce the first photoresist layer 200 simultaneously, avoid high temperature from damaging semiconductor devices.
With continued reference to Fig. 5, after forming second photoresist layer 210, still there is the photoresist overlay of part described floating
The surface of grid layer 120, the second photoresist layer 210 being covered on the floating gate layer 120 will affect subsequent to the floating gate layer 120
The effect of interior Doped ions.
Thus, with reference to Fig. 6, after forming second photoresist layer 210, remove second photoresist of segment thickness
Layer 210 forms third photoresist layer 220.Third photoresist layer 220 is covered on 140 bottom of groove, and makes the floating gate layer
120 are exposed to 220 surface of third photoresist layer, consequently facilitating subsequent ion adulterates.
In removal covering part in 120 second photoresist layer of surface of floating gate layer, the second light described in strict control is obtained
The removal rate of photoresist layer removes too fast and causes the photoresist quilt in the groove 140 to avoid second photoresist layer
Too fast removal and influence the thickness of third photoresist layer 220 being subsequently formed.
In the present embodiment, method of the removal covering part in 120 second photoresist layer of surface of floating gate layer are as follows: use ammonia
Water, hydrogen peroxide aqueous solution as wet etchant, the second photoresist layer 210 described in wet etching, to remove segment thickness
Second photoresist layer 210.Wherein, in the wet etchant, the volume ratio of ammonium hydroxide, hydrogen peroxide and water is 1:1~5:10
~50, i.e. V (ammonium hydroxide): V (hydrogen peroxide): V (water)=1:1~5:10~50.
Still optionally further, the temperature of the wet etchant is 25~50 DEG C.
It can control the removal rate of second photoresist layer 210 using above-mentioned etching agent, process controllability improved, to keep away
Exempt from the second photoresist layer 210 by too fast removal.
If the thickness on the barrier layer 220 is too small, it will affect barrier layer 220 and ion prevented to enter 140 bottom of groove
Effect, cause the technique for carrying out ion doping to the FGS floating gate structure surface that 140 bottom of groove is caused to damage；If described
The thickness on barrier layer 220 is excessive, can improve the subsequent barrier layer 220 and remove difficulty.
In the present embodiment, further optional, the thickness on the barrier layer is greater than or equal toFurther optionally,
The thickness on the barrier layer is less than or equal to
Referring again to Fig. 7, after forming the barrier layer (i.e. third photoresist) 220, using ion implanting, to the floating of exposing
The surface doping ion of grid layer 120 forms ion doped layer 300, N ion and floating gate layer 120 in the ion doped layer 300
For the polycrystalline pasc reaction on surface to form silicon nitride, the ion doped layer 300 is used as the first insulating layer.
The ion doped layer 300 covers in upper surface and the partial sidewall of the floating gate layer 120, exposes the floating gate
The partial sidewall of 120 lower section of layer.
Optionally, in the step of carrying out ion implanting to the FGS floating gate structure, the dosage 10 × 10 of plasma15~20 ×
1015atom/cm2, power is 1500~2000W.While to inject appropriate ion in the floating gate layer 120, half is reduced
The damage at other positions of conductor device.
Still optionally further, the temperature of ion implanting is 100~500 DEG C, to improve the effect of ion doping.
In optinal plan, the barrier layer 220 is removed after forming the ion doped layer 300 in conjunction with reference Fig. 8, is revealed
The bottom of the groove 140 out.
In the present embodiment, use ozone solution as wet etchant with the barrier layer 220；The ozone solution it is dense
Degree is 10~100ppm (ppm, full name parts per million, parts per million concentration are mass concentration unit).To mention
High 220 removal efficiency of barrier layer simultaneously, avoids semiconductor devices from being damaged.
In other embodiments, OK73 solution or SPM solution also can be used as wet etchant, to remove
State barrier layer 220.The OK73 solution is the mixed solution of propylene glycol monomethyl ether and propylene glycol methyl ether acetate, the propylene glycol first
The volume ratio of ether acetate and propylene glycol monomethyl ether is 7:3 or so, and the SPM solution is diluted sulfuric acid solution, sulfuric acid and water
Volume ratio is 2:1~5:1.
Optionally, the temperature of the wet etchant is 120~130 DEG C, to improve the etching speed on the barrier layer 220
Rate, while reducing the consumption of semiconductor devices other parts.
Referring next to Fig. 9, after removing the barrier layer 220, annealing process is carried out, to promote the ion doped layer 300
The polycrystalline pasc reaction of interior N ion and 120 surface of floating gate layer is to form silicon nitride, the first insulating layer 310 after forming annealing, with
Improve the performance of first insulating layer.
If the thickness of the first insulating layer 310 after the annealing is much, the performance of floating gate being subsequently formed is influenced, if described
How small the thickness of first insulating layer 310 is, can reduce its insulation effect.
In the present embodiment, the first insulating layer 310 after annealing with a thickness of
In the present embodiment, the temperature of the annealing process is 800~900 DEG C, and duration is 20~60 minutes.
In the present embodiment, first insulating layer 310 is covered in upper surface and the partial sidewall of the floating gate layer 120,
Expose the partial sidewall of 120 lower section of floating gate layer.
It is worth noting that, the ion doping only forms the ion on the surface of the floating gate layer 120 in the present invention
Doped layer 300, the parameters such as dosage of ion doping are determined according to the thickness on subsequent barrier layer to be formed, to improve subsequent
At the devices such as nand memory performance.
And then combine and refer to Fig. 9 and 10, the is sequentially formed on the FGS floating gate structure and first insulating layer 310
Monoxide layer 321, nitride layer 322 and the second silicon oxide layer 323.First oxide skin(coating) 321, nitride layer 322,
With the second silicon oxide layer 323 composition second insulating layer 320 (that is, the second insulating layer 320 is ONO structure).It is subsequent described
After forming control gate on FGS floating gate structure, 320 collective effect of first insulating layer 310 and second insulating layer, using as floating gate knot
Insulating layer between structure and control gate.
In the present embodiment, the second insulating layer 320 is covered on first insulating layer 310 and first insulating layer
On the side wall of 310 FGS floating gate structures exposed.
The forming method of first silicon oxide layer 321, silicon nitride layer 322 and the second silicon oxide layer 323 includes chemical gas
Phase sedimentation, atomic layer deposition method or physical vapour deposition (PVD) etc..Formation side of the present invention to each layer in the second insulating layer
Method is not specifically limited.
Optionally, first oxide skin(coating) with a thickness ofLeft and right, oxynitride layer with a thickness ofLeft and right, the
Dioxide layer with a thickness ofLeft and right.
Referring again to Figure 11, control grid structure 400 is formed in the semiconductor substrate 100.
The forming method of the control grid structure 400 is this field mature technology, and details are not described herein.
In the present embodiment, the forming method of the semiconductor devices includes: to form multiple floating gate knots on a semiconductor substrate
After structure, ion doping is carried out to the FGS floating gate structure surface, the ion and the FGS floating gate structure surface in incorporation FGS floating gate structure are anti-
Ion doped layer should be formed, as the first insulating layer；Annealing process is carried out, later to promote the ion in ion doped layer and float
Grid structure reaction, promotes the performance of first insulating layer；Covering forms the second insulation on first insulating layer later
Layer, first insulating layer and second insulating layer can be improved it is described be subsequently formed in the devices such as nand memory, floating gate knot
Insulation effect between structure and control grid structure.In the present embodiment, the first insulating layer is formed using ion doping mode, compared to adopting
Insulating layer is formed on the FGS floating gate structure with depositional mode, stress effect caused by first insulating layer can be effectively reduced
Influence for FGS floating gate structure, to improve the performance at devices such as nand memories being subsequently formed.
In the present embodiment, ion doping technique is first carried out, forms ion doped layer 300 on 120 surface of floating gate layer, it
After carry out annealing process, to promote the polycrystalline pasc reaction of ion and floating gate layer surface in ion doped layer, form the to improve
The performance of one insulating layer；And then in forming second insulating layer on the FGS floating gate structure.Above-mentioned technique can avoid annealing process shadow
Ring the performance of the second insulating layer.
But in another embodiment of the invention, after 120 surface of floating gate layer forms the ion doped layer 300,
The second insulating layer first can be formed on the ion doped layer 300, carry out annealing process (the annealing process item again later
Part is as described above, details are not described herein), to improve the performance for the first insulating layer for being formed in the FGS floating gate structure surface.The skill
The purpose of the present invention still may be implemented in art scheme, these simple changes are within the scope of the invention.
The present embodiment additionally provides the semiconductor devices of the forming method formation using above-mentioned semiconductor device, but this implementation
The forming method for the semiconductor devices that example provides is not limited to the forming method of above-mentioned semiconductor device.
1 can be continued to refer to figure 1, in the present embodiment, the semiconductor devices includes:
Semiconductor substrate 100.
FGS floating gate structure in the semiconductor substrate 100.
The FGS floating gate structure includes the tunnel layer being formed in semiconductor substrate 100 and the floating gate on the tunnel layer
Layer 120.The FGS floating gate structure is this field mature technology, and details are not described herein.
The first insulating layer 310 on the FGS floating gate structure, first insulating layer 310 be to the FGS floating gate structure into
What row ion doping was formed.
In the present embodiment, the ion is Nitrogen ion, and first insulating layer 310 is silicon nitride layer.
Optionally, first insulating layer 310 with a thickness of
In the present embodiment, first insulating layer 310 is covered on surface and the floating gate layer 120 of the floating gate layer 120
Partial sidewall on.
The content in the forming method of the process parameters above-mentioned semiconductor device of ion doping is carried out to the FGS floating gate structure,
Details are not described herein.
The semiconductor devices further include: the second insulating layer 320, Yi Jiwei positioned at 310 surface of the first insulating layer
Control grid structure 400 in the second insulating layer 320.
In the present embodiment, the second insulating layer 320 includes the first oxide skin(coating) being sequentially located on the FGS floating gate structure
321, nitride layer 322 and the second oxide skin(coating) 323.
And the second insulating layer 320 is covered on first insulating layer 310 and first insulating layer 310 exposes
FGS floating gate structure side wall on.
First insulating layer 310 and second insulating layer 320 can be improved between the FGS floating gate structure and control grid structure 400
Insulation effect, reduce FGS floating gate structure and control grid structure 400 between leaky；And it is formed using ion implanting mode
First insulating layer 310 can effectively reduce using depositional mode the generated stress when forming barrier layer on the FGS floating gate structure
Effect, and then promote performance of semiconductor device.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (14)
1. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided；
FGS floating gate structure is formed on the semiconductor substrate, specifically: it is formed with multiple floating gate knots on the semiconductor substrate
Structure is formed between adjacent FGS floating gate structure fluted；
Barrier layer is formed in the bottom portion of groove, the barrier layer surface is lower than the FGS floating gate structure surface；
Ion doping is carried out to the surface of the FGS floating gate structure, forms the first insulating layer；First insulating layer is covered on described
The partial sidewall on the surface of FGS floating gate structure and the FGS floating gate structure；
Remove the barrier layer；
Second insulating layer is formed on the first insulating layer；The second insulating layer is covered on first insulating layer and institute
On the side wall for stating the FGS floating gate structure of the first insulating layer exposing；
Control grid structure is formed over the second dielectric.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the barrier layer is photoresist layer.
3. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that the step of forming barrier layer packet
It includes: the semiconductor substrate is covered with diluted photoresist solution；Heating process is carried out later, removes partial solvent, is made described
Barrier layer surface in groove is lower than the FGS floating gate structure surface, to form the photoresist layer for covering the bottom portion of groove.
4. the forming method of semiconductor devices as claimed in claim 3, which is characterized in that the temperature of the heating process is 120
~180 DEG C.
5. the forming method of semiconductor devices as claimed in claim 4, which is characterized in that after carrying out heating process, removal portion
Divide the photoresist layer of thickness, with the FGS floating gate structure of exposed portion thickness.
6. the forming method of semiconductor devices as claimed in claim 5, which is characterized in that the photoresist layer of segment thickness is removed,
Using the step of FGS floating gate structure of exposed portion thickness include: using ammonium hydroxide, hydrogen peroxide aqueous solution as wet etchant,
Part photoresist layer is removed with wet-etching technology.
7. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that the step of removing barrier layer packet
It includes: using the solution for containing ozone as wet etchant, the barrier layer being removed with wet-etching technology；The wet etching
The concentration of ozone is 10~100ppm in agent.
8. the forming method of semiconductor devices as described in claim 1, which is characterized in that the barrier layer with a thickness of
9. the forming method of semiconductor devices as described in claim 1, which is characterized in that carried out to the surface of the FGS floating gate structure
After ion doping, the forming method further include: annealing process is carried out, to promote the FGS floating gate structure and the ion to occur
Reaction.
10. the forming method of semiconductor devices as claimed in claim 9, which is characterized in that the temperature of the annealing process is 800
~900 DEG C, the time is 20~60 minutes.
11. the forming method of semiconductor devices as described in claim 1, which is characterized in that the ion is Nitrogen ion.
12. the forming method of semiconductor devices as described in claim 1, which is characterized in that first insulating layer with a thickness of
13. the forming method of semiconductor devices as described in claim 1, which is characterized in that the method for the ion doping be from
Son injection；In the step of ion implanting: implantation dosage 10 × 1015~20 × 1015atom/cm2, power be 1500~
2000W。
14. the forming method of semiconductor devices as described in claim 1, which is characterized in that the step of forming second insulating layer is wrapped
It includes: sequentially forming the first silicon oxide layer, silicon nitride layer and the second silicon oxide layer on the first insulating layer.
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| CN110544739A (en) * | 2019-09-02 | 2019-12-06 | 闽南师范大学 | Flip red light chip and manufacturing method thereof |
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| US20030153149A1 (en) * | 2002-02-08 | 2003-08-14 | Zhong Dong | Floating gate nitridation |
| KR20100127154A (en) * | 2009-05-25 | 2010-12-03 | 주식회사 하이닉스반도체 | Gate pattern for nonvolatile memory device and manufacturing method of the same |
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