CN104347514B - A kind of preparation method of embedded flash memory - Google Patents
A kind of preparation method of embedded flash memory Download PDFInfo
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- CN104347514B CN104347514B CN201310325281.3A CN201310325281A CN104347514B CN 104347514 B CN104347514 B CN 104347514B CN 201310325281 A CN201310325281 A CN 201310325281A CN 104347514 B CN104347514 B CN 104347514B
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Abstract
The invention discloses a kind of preparation method of embedded flash memory, including there is provided Semiconductor substrate, the Semiconductor substrate has flash cell region and logic region；On the semiconductor substrate deposition of gate material layer；Bottom anti-reflection layer and the first photoresist layer are formed in the gate material layers；Remove first photoresist layer positioned at the logic region；Processing is located at first photoresist layer in the flash cell region and the bottom antireflective coating in the logic region, to form barrier layer on the surface of first photoresist layer and the bottom anti-reflection layer；The second photoresist layer is formed on the barrier layer.According to the method for making embedded flash memory proposed by the present invention, to avoid the damage in the technical process for forming logic gate loop to the control gate in flash cell region, the overall performance of embedded flash memory and the yields of embedded flash memory are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of preparation method of embedded flash memory.
Background technology
Memory is used to store a large amount of digital informations, shows according to investigations recently, worldwide, memory chip is about
The 30% of semiconductor transaction is account for, for many years, the progress of technology and the market demand expedite the emergence of more and more highdensity various
Type memory, such as RAM (random access memory), SRAM (SRAM), DRAM (dynamic RAM) and FRAM
(ferroelectric memory) etc..
Random access memory, such as DRAM deposit the problem of data storage is lost after a power failure in use with SRAM.For
Overcome this problem, people have designed and developed a variety of nonvolatile memories.Recently, based on floating grid concept
Flash memory, because it has small unit size and good service behaviour has turned into most general nonvolatile memory.
Nonvolatile memory mainly includes two kinds of basic structures：Gate stack (stack gate) structure and separated grid
Formula (split gate) structure.
Gate stack structure formula memory include being sequentially formed at tunnel oxide skin(coating) on substrate, storage electronics it is floating
Gate polysilicon layer, oxide/nitride/oxide (oxide-nitride-oxide, ONO) lamination and control Electronic saving
With the control gate polysilicon layer of release.
Also tunnel oxide skin(coating), the floating grid of storage electronics including being formed on substrate are more for separate grid type memory
Crystal silicon layer, oxide/nitride/oxide (oxide-nitride-oxide, ONO) lamination and control Electronic saving and release
Control gate polysilicon layer.
But from unlike gate stack formula memory, separate grid type memory is also in the side shape of gate stack structure
Into the polysilicon layer as erasing grid (erase gate).Meanwhile, separate grid type flash memory memory is to realize certain function,
Surrounding can have peripheral circuit (Periphery Circuit), including logic transistor.
If separate grid type flash memory memory, logic transistor are all made in single integrated chip, whole storage
The speed of service of device can be limited by the signal transmission bandwidth between flash memories and peripheral circuit.At present, in the prior art
There is the integrated circuit that logic transistor is embedded in separate grid type flash memory memory.
Flash memories are FLASH, and it turns into the main flow of non-volatile semiconductor storage technology, various
In FLASH devices, embedded flash memory is on-chip system (SOC) one kind, while integrated logic circuit in a piece of integrated circuit
Module and flash memory circuit module, have been widely used in the products such as smart card, microcontroller.In the flash memory of embedded logic circuit
Memory technology is gradually in the ripe, evolution that storage speed is constantly accelerated, cost is gradually reduced, and people start to make it
Method proposes new requirement.
During making application of logic circuit module and flash memory circuit module in integrated circuit, Fig. 1 is embedding in the prior art
Enter the cross-sectional view of formula flush memory device.From figure 1 it appears that on a semiconductor substrate 100 in logic region I
Logic circuit gate material layers 101 and the control gate in the II of flash cell region material layer 101 ' between ladder it is high
Degree (Step height) is larger, is deposited in the technical process for forming logic circuit gate loop (logic gate loop)
The thickness of bottom antireflective coating (BARC) 102 and photoresist layer 103 (PR) above the material layer 101 ' of control gate is smaller
The gate material layers of control gate below can not be protected, cause embedded when etching forms the grid of logic region
The damage problem of control gate in flash memory.
Traditional solution to the problems described above is：(1) photoresist layer or/and bottom antireflective coating in increase etching process
Thickness, but this will influence the resolution ratio of photoresist layer and bottom antireflective coating logic circuit grid formed below, example
Such as, the target critical dimension of influence grid line width and grid spacing；(2) it is initially formed flowing before bottom antireflective coating is formed
Material layer, then, method (the tri-layer patterning transferring shifted using three layer patterns
Approach logic gate) is formed.However, traditional solution can produce new technological problemses, other impurities are readily incorporated,
Manufacture craft is set to complicate.
Accordingly, it would be desirable to a kind of new method, to avoid in the technical process for forming logic gate loop to flash cell
The damage of control gate in region, to improve the overall performance of embedded flash memory and the yields of embedded flash memory.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in embodiment part
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to solve problems of the prior art, the present invention proposes a kind of method for making embedded flash memory, wraps
The following steps are included there is provided Semiconductor substrate, the Semiconductor substrate has flash cell region and logic region, the sudden strain of a muscle
Floating grid and the gate dielectric layer on the floating grid are formed with memory cell region；Sink on the semiconductor substrate
Product gate material layers, wherein the gate material layers in the logic region are used to form logic circuit grid, are located at
Gate material layers in the flash area are used to form control gate；Bottom anti-reflection layer is formed in the gate material layers
With the first photoresist layer；First photoresist layer positioned at the logic region is removed, to retain the flash cell
First photoresist layer in region；Processing be located at the flash cell region in first photoresist layer and positioned at described
The bottom antireflective coating in logic region, with the table of first photoresist layer and the bottom anti-reflection layer
Face forms barrier layer；The second photoresist layer is formed on the barrier layer.
Preferably, it is described to be processed as handling first photoresist layer and institute using injection technology or dry etch process
State bottom anti-reflection layer.
Preferably, the etching gas that the dry etching is used are for the gas based on nitrogen or based on nitrogen and hydrogen
Mixed gas.
Preferably, the pressure of the dry etching is 5-50mT, and source power is 2-1000W, and bias power is 0W, during reaction
Between be 1-15 seconds.
Preferably, the injection technology is that hydrogen injects or carbon injection.
Preferably, the ion beam energy of the injection technology is 20Kev~100Kev, and the ion dose of injection is 1e10~
1e16Atom/cm2。
Preferably, the thickness on the barrier layer is 50 angstroms to 500 angstroms.
Preferably, in addition to patterning positioned at the logic region second photoresist layer the step of.
Preferably, using the second photoresist layer of the patterning described in mask etch gate material layers to form described patrol
Collect circuitry gate.
To sum up shown, method of the invention using ion implantation technology or dry etching by first handling the first photoresist
Then layer forms the second photoresist layer on the first photoresist layer, and double photoresist layers cover the control gate, to solve carving
The damage problem to the control gate in flash cell region in the technical process for forming logic gate loop is lost, to improve insertion
The overall performance and the yields of embedded flash memory of formula flash memory.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.In the accompanying drawings,
Fig. 1 is the cross-sectional view of the embedded flash memory device structure made according to prior art；
Fig. 2A -2E are obtained to make the correlation step of embedded flash memory device structure according to one embodiment of the present invention
Device cross-sectional view；
Fig. 3 is the process chart that embedded flash memory device structure is made according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it will be apparent to one skilled in the art that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to illustrate the present invention be as
What, which uses process of surface treatment, solves the problems, such as the loss to control gate in flash cells region to deposit two layers of photoresist layer.
Obvious presently preferred embodiments of the present invention being described as follows in detail, but remove these and be described in detail outer, the present invention can also have
Other embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that, when in this manual use term "comprising" and/or " comprising "
When, it indicates there is the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or many
Other individual features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and these exemplary are implemented
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make identical element is presented with like reference characters, thus description of them will be omitted.
In the present invention in order to solve defect present in prior art, in the present invention using double photoresist layers and surface
The method of processing, use in the technique that etching forms logic gate loop double photoresist layers cover mating surface handling process with
The first photoresist layer and the second photoresist layer are formed, the drawbacks of by methods described to solve to exist in the prior art.
The preparation method of embedded flash memory memory of the present invention is described in detail below in conjunction with Fig. 2A -2E,
Fig. 2A -2E be according to the present embodiment make embedded flash memory during memory structural section figure.
As shown in Figure 2 A there is provided Semiconductor substrate 200, Semiconductor substrate may include any semi-conducting material, this semiconductor
Material may include but be not limited to：Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or II-
VI compound semiconductor.
By Semiconductor substrate, 200 points are two regions, are respectively：First area I for forming logical device, logic electricity
Road region I；The two region II for forming flash memories, flash cell region II.It should be noted that logic region
I is peripherally located circuit region in true layout, therefore, the figure that logical device position relationship is not provided by the present embodiment
Limitation.
Grid oxic horizon is formed on a semiconductor substrate, Semiconductor substrate and the flash memories that are subsequently formed are floating
Grid, logical device gate isolation.Grid oxic horizon can pass through thermal oxide, chemical vapor deposition (CVD) or oxynitridation process
Formed.Grid oxic horizon can include following any conventional dielectric：SiO2、SiON、SiON2And including Ca-Ti ore type oxygen
Other similar oxides of compound.Wherein, the material of grid oxic horizon preferably uses silica, and generation type uses thermal oxidation method.
Floating grid 201 is formed on the grid oxic horizon in flash cell region, floating grid can include each material,
Each described material including but not limited to：Some metals, metal alloy, metal nitride and metal silicide, and its lamination system
Part and its compound.Gate electrode can also include the polysilicon and polysilicon-Ge alloy material and polycrystalline silicon metal of doping
Silicide material (polysilicon of doping/metal silicide laminated material).Similarly, it would however also be possible to employ any the one of several methods
Individual formation previous materials.Non-limiting examples include self-aligned metal silicate method, process for chemical vapor deposition of materials and physics vapour
Phase deposition process.
Gate dielectric layer 202 is formed on floating grid 201.As shown in Figure 2 A, specifically, gate dielectric layer 202 can be oxygen
Compound, nitride, oxide altogether three layers of ONO sandwich structures, those skilled in the art it should be appreciated that gate dielectric layer
202 can also be the gate dielectric layer such as one layer of oxide of formation on one layer of nitride or one layer of oxide or one layer of nitride
Structure.It can use including but not limited to：The method formation gate dielectric layer 202 of chemical vapor deposition and PVD.
The one of the present invention is specifically in embodiment, and gate dielectric layer structure is oxide, nitride, oxide three layers (ONO) altogether
Sandwich structure.
Floating grid is removed in logic region to expose grid oxic horizon, specifically, according to the light shield of patterning
(reticle) floating grid in logic region is removed.Floating grid, dry etching work can be removed using dry etching
Skill includes but is not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Then, exist
Deposition of gate material layer in the Semiconductor substrate, the preferred polysilicon of material of gate material layers, wherein positioned at logic electricity
Gate material layers 203 in the region of road are used to form logic circuit grid, the gate material layers in the flash area
203 ' are used to form control gate, specifically, gate material layers are formed on the grid oxic horizon in logic region,
Gate material layers are formed on gate dielectric layer 202 in flash cell region, the material of gate material layers is polysilicon.
The forming method of polysilicon can select low-pressure chemical vapor phase deposition (LPCVD) technique.Form the work of the polysilicon
Skill condition includes：Reacting gas is silane (SiH4), the range of flow of the silane can be 100~200 cc/mins
(sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；It can be 250~350 to react cavity pressure
Milli millimetres of mercury (mTorr), such as 300mTorr；Buffer gas is may also include in the reacting gas, the buffer gas can be
Helium or nitrogen, the range of flow of the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
As shown in Figure 2 A, logic gate material layer 203 is formed in logic region on semiconductor substrate 200, is being dodged
Floating grid 201, gate dielectric layer 202 and gate material layers 203 ' are formed in memory cell region, wherein, for forming logic gate
Gate material layers and being used on floating grid 201, gate dielectric layer 202 form the grid material of control gate material layer
Gradient altitude range between layer 203 ' is 500 angstroms to 1500 angstroms, and the gate material layers of control gate are higher than logic circuit grid
Gate material layers.
In of the invention one specifically embodiment, the gate material layers of control gate and the grid of logic circuit grid
What material layer was simultaneously formed.
As shown in Figure 2 B, it is sequentially depositing to form bottom anti-reflection layer 204 and photoresist layer 205 on semiconductor substrate 200,
Bottom anti-reflection layer 204 and photoresist layer 205 cover the gate material layers 203.
Other substrate materials, which can include being selected from, includes positive-tone photo glue material, negative photo glue material and mixing photoresist material
Other substrate materials in the group of material.Generally, mask layer includes the positive-tone photo with from about 2000 to about 5000 angstroms of thickness
Glue material or negative photo glue material.
Bottom antireflective coating is coated in the bottom of photoresist to reduce the reflection of bottom light.There are two kinds of coating materials：
Organic antireflective coating (Organic), in silicon chip surface spin coating, incident ray is directly received by organic layer；Inorganic anti-reflective
Coating (Inorganic) is penetrated, plasma reinforced chemical vapour deposition (PECVD) formation is utilized in silicon chip surface.General material is：
TiN or SiN.Worked by specific wavelength phase cancellation, most important parameter has：Refractive Index of Material, film thickness etc..Bottom
The use of portion's ARC is than wide.
Then, using with removing the floating grid identical light shield in logic region, the step such as exposed and developed
Afterwards, the photoresist layer in logic region in gate material layers is removed, to expose bottom antireflective coating.Such as Fig. 2 C institutes
Show, without introducing or increase during the photoresist layer being located in logic region on bottom antireflective coating is removed
The mask layer of other materials.
As shown in Figure 2 C, the thickness of the bottom antireflective coating above the gate material layers in flash area compares position
The thickness of the bottom antireflective coating above gate material layers in logic region is small, therefore retains positioned at flash cell
Photoresist layer in region
Then, as shown in Figure 2 D, processing be located at flash cell region in photoresist layer 205 and positioned at logic region
In bottom antireflective coating 204 to form barrier layer 206, on photoresist layer 205 and bottom antireflective coating 204 formed resistance
Barrier 206.The thickness range on barrier layer 206 is 50 angstroms to 500 angstroms.Barrier layer 206 can prevent between double photoresist layers
Dissolving, to prevent the thickness of photoresist layer from reducing.
In the embodiment of the present invention, processing is located at the photoresist layer 205 in flash cell region and patrolled
The method for collecting the bottom antireflective coating 204 in circuit region can be to carry out hydrogen note to photoresist layer and bottom antireflective coating
Enter to form barrier layer 206 on photoresist layer 205 and bottom antireflective coating 204.Specifically, being pointed to flash cells region
In photoresist layer and logic region in bottom antireflective coating carry out hydrogen injection, it is anti-in photoresist layer 205 and bottom
Barrier layer 206 is formed on reflectance coating 204.The technique of injection is：Injection ion beam energy is 20Kev~100Kev, ionic agent
Measure as 1e10~1e16Atom/cm2.Wherein, the surface of photoresist layer and bottom antireflective coating is handled using hydrogen injection technology
Condition is preferably that injection ion beam energy is 50Kev, and ion dose is 1e13Atom/cm2.Or, work can be injected using carbon
Skill handles photoresist layer 205 and bottom antireflective coating 204, to be formed on photoresist layer 205 and bottom antireflective coating 204
Barrier layer 206.
In another specifically embodiment of the present invention, processing is located at the He of photoresist layer 205 in flash cell region
The method of bottom antireflective coating 204 in logic region can be dry etching with anti-in photoresist layer 205 and bottom
Barrier layer 206 is formed on reflectance coating 204.Specifically, the photoresist layer being pointed in flash cells region and logic circuit area
Bottom antireflective coating in domain carries out dry etching, and barrier layer is formed on photoresist layer and bottom antireflective coating.Dry method
Etching includes but is not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Preferably lead to
Cross one or more RIE step and carry out dry etching.Photoresist layer 205 and bottom antireflective coating are handled using dry etching
204, the etching pressure is 5~50mT in this step, and source power is 2~1000W, and bias power is 0W, and the reaction time is 1
~15 seconds, wherein, it is 50mTorr preferably to etch pressure, and source power is 500W；The preferred 0W of bias power, the reaction time is 15 seconds；
Etching gas can use and be based on nitrogen (N2- based) gas or mixed gas (N based on nitrogen and hydrogen2/H2-
based)。
As an example, using plasma etching, etching gas can use the gas based on nitrogen.Specifically,
Using relatively low RF energy and it can produce low pressure and highdensity plasma gas and realize the dry etching of polysilicon.Adopt
Etching gas are the gas based on nitrogen, and the flow of etching gas is：100~200 cc/mins (sccm)；Instead
It can be 30~50mTorr to answer room pressure, and the time of etching is 10~15 seconds, and power is 40~50W, and bias power is 0W.
As shown in Figure 2 E, revolved on bottom antireflective coating 204 expose, surface treated and photoresist layer 205
Resist coating layer 207, specifically, processing is located at the photoresist layer 205 in flash cell region and the bottom in logic region
Portion's ARC 204 then forms photoresist layer 207, patterning logic electricity over the barrier layer 206 to form barrier layer 206
The photoresist layer on barrier layer in the region of road is to form the photoresist layer 208 of patterning, wherein according to the logic that will be formed
The figure of grid is exposed and developed etc. step to form the photoresist layer 208 of patterning to photoresist layer.In flash cell
The bottom antireflective coating 204 in gate material layers 203, photoresist layer 205, barrier layer 206 and photoresist layer 207 in region
The pellicular cascade 209 of composition, the pellicular cascade 209 has appropriate thickness.Patrolled according to the photoresist layer 208 of patterning etching
Pellicular cascade 209 can protect the grid of control gate below when collecting the gate material layers of the logic gate in circuit region
Material layer.Gate material layers are to form the logic circuit grid according to the photoresist layer 208 of patterning is mask etch.
The photoresist layer for forming patterning is that technological means well known to those skilled in the art is not just discussed in detail herein.
Reference picture 3, illustrated therein is to make the technique stream of embedded flash memory device according to one embodiment of the present invention
Cheng Tu.Flow for schematically illustrating whole manufacturing process.
In step 301 there is provided Semiconductor substrate, Semiconductor substrate is divided into two regions, is respectively：Dodged for being formed
Deposit the second area of memory, flash cell region；First area for forming logical device, logic region.Half
Grid oxic horizon is formed on conductor substrate.Floating grid is formed on the grid oxic horizon in flash cell region, in floating grid
Upper formation gate dielectric layer.Floating grid is removed in logic region to expose grid oxic horizon, in the Semiconductor substrate
Upper deposition of gate material layer；
In step 302, it is sequentially depositing to form bottom anti-reflection layer and the first photoresist layer in gate material layers；
In step 303, the first photoresist layer being located in logic region is removed, to expose bottom anti-reflective painting
Layer, retains first photoresist layer in the flash cell region；
In step 304, the bottom handled in the first photoresist layer and logic region in the flash cell region resists
Reflectance coating, is hindered with being formed on the bottom antireflective coating in the first photoresist layer and logic region in flash cells region
Barrier；The method of processing can be injection technology or dry etch process；
In step 305, the spin coating on bottom antireflective coating expose, surface treated and the first photoresist layer
Second photoresist layer, specifically, processing is located at the photoresist layer in flash cell region and the bottom in logic region resists
Reflectance coating forms the second photoresist layer to form barrier layer, over the barrier layer, and patterning is located at the bottom in logic region
The second photoresist layer on portion's anti-reflecting layer is to form the second photoresist layer of patterning.
To sum up shown, method of the invention using injection technology or dry etching by first handling the first photoetching exposed
Glue-line and bottom antireflective coating, then form the second photoresist layer on the first photoresist layer and bottom antireflective coating, double
Photoresist layer covers the control gate, to solve in the technical process that etching forms logic gate loop to flash cell area
The damage problem of control gate in domain, to improve the overall performance of embedded flash memory and the yields of embedded flash memory.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member it is understood that the invention is not limited in above-described embodiment, according to the present invention can also make more kinds of modifications and
Modification, these variants and modifications are all fallen within scope of the present invention.
Claims (9)
1. a kind of method for making embedded flash memory, including：
Semiconductor substrate is provided,
The Semiconductor substrate has flash cell region and logic region,
Floating grid and the gate dielectric layer on the floating grid are formed with the flash cell region；
Deposition of gate material layer on the semiconductor substrate, wherein gate material layers in the logic region are used
In forming logic circuit grid, the gate material layers in the flash area are used to form control gate；
Bottom anti-reflection layer and the first photoresist layer are formed in the gate material layers；
First photoresist layer positioned at the logic region is removed, to retain described the of the flash cell region
One photoresist layer；
Processing is located at first photoresist layer in the flash cell region and the institute in the logic region
Bottom antireflective coating is stated, to form barrier layer on the surface of first photoresist layer and the bottom anti-reflection layer；
The second photoresist layer is formed on the barrier layer.
2. the method as described in claim 1, it is characterised in that described to be processed as using injection technology or dry etch process
Handle first photoresist layer and the bottom anti-reflection layer.
3. method as claimed in claim 2, it is characterised in that the etching gas that the dry etching is used is based on nitrogen
Gas or the mixed gas based on nitrogen and hydrogen.
4. method as claimed in claim 2, it is characterised in that the pressure of the dry etching is 5-50mT, and source power is 2-
1000W, bias power is 0W, and the reaction time is 1-15 seconds.
5. method as claimed in claim 2, it is characterised in that the injection technology is that hydrogen injects or carbon injection.
6. method as claimed in claim 2, it is characterised in that the ion beam energy of the injection technology be 20Kev~
100Kev, the ion dose of injection is 1e10~1e16Atom/cm2。
7. the method as described in claim 1, it is characterised in that the thickness on the barrier layer is 50 angstroms to 500 angstroms.
8. the method as described in claim 1, it is characterised in that be also located at including patterning described in the logic region
The step of second photoresist layer.
9. method as claimed in claim 8, it is characterised in that using the second photoresist layer of the patterning as mask etch institute
Gate material layers are stated to form the logic circuit grid.
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| US6258667B1 (en) * | 1999-08-10 | 2001-07-10 | United Microelectronics Corp. | Method for implementing embedded flash |
| US6265751B1 (en) * | 1999-10-29 | 2001-07-24 | Advanced Micro Devices, Inc. | Method and system for reducing ARC layer removal by condensing the ARC layer |
| CN101842899A (en) * | 2007-10-29 | 2010-09-22 | 飞思卡尔半导体公司 | Method for integrating NVM circuitry with logic circuitry |
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| US6258667B1 (en) * | 1999-08-10 | 2001-07-10 | United Microelectronics Corp. | Method for implementing embedded flash |
| US6265751B1 (en) * | 1999-10-29 | 2001-07-24 | Advanced Micro Devices, Inc. | Method and system for reducing ARC layer removal by condensing the ARC layer |
| CN101842899A (en) * | 2007-10-29 | 2010-09-22 | 飞思卡尔半导体公司 | Method for integrating NVM circuitry with logic circuitry |
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