CN108597433B - Display device - Google Patents
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- CN108597433B CN108597433B CN201810394138.2A CN201810394138A CN108597433B CN 108597433 B CN108597433 B CN 108597433B CN 201810394138 A CN201810394138 A CN 201810394138A CN 108597433 B CN108597433 B CN 108597433B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
A display device includes: the source driver, the multiplexer and the controller are connected in series. The source driver is used for outputting a first data voltage and a second data voltage in sequence according to a trigger signal. The multiplexer is used for receiving the first data voltage and the second data voltage and sequentially outputting the first data voltage and the second data voltage to different data lines according to a first multiplexing signal and a second multiplexing signal. The controller generates a control signal to control a stop time point of the first multiplexing signal and a start time point of the second multiplexing signal to be substantially equal to each other, and controls the source driver to stop outputting the first data voltage in response to the control signal. The invention can reduce noise and avoid providing data voltage for wrong data line.
Description
Technical Field
The present application relates to an electronic device. In particular, the present application relates to a display device.
Background
With the development of science and technology, display devices have been widely used in the life of people.
A typical display device may include a gate driver, a source driver, and a pixel circuit. The gate driver is used for providing a gate signal to the pixel circuit so as to open a switch of the pixel circuit. The source driver is used for providing data voltage to the pixel circuit with the switch turned on so as to enable the pixel circuit to display corresponding to the data voltage.
Disclosure of Invention
One embodiment of the present application relates to a display device. According to an embodiment of the present application, a source driver of a display device includes: the source driver, the multiplexer and the controller are connected in series. The source driver is used for outputting a first data voltage and a second data voltage in sequence according to a trigger signal. The multiplexer is used for receiving the first data voltage and the second data voltage and sequentially outputting the first data voltage and the second data voltage to different data lines according to a first multiplexing signal and a second multiplexing signal. The controller generates a control signal to control a stop time point of the first multiplexing signal and a start time point of the second multiplexing signal to be substantially equal to each other, and controls the source driver to stop outputting the first data voltage in response to the control signal.
Another embodiment of the present application relates to a display device. According to an embodiment of the present application, a source driver includes a source driver, a multiplexer, a controller, and a switching circuit. The source driver is used for outputting a first data voltage and a second data voltage in sequence according to a trigger signal. The multiplexer is used for receiving the first data voltage and the second data voltage and sequentially outputting the first data voltage and the second data voltage to a first data line and a second data line according to a first multiplexing signal and a second multiplexing signal. The controller is configured to generate a control signal to control a time point of a falling edge of the first multiplex signal and a time point of a rising edge of the second multiplex signal to be substantially the same as each other, or to control a time point of a rising edge of the first multiplex signal and a time point of a falling edge of the second multiplex signal to be substantially the same as each other. The switching circuit is used for switching according to the control signal so as to prevent the first data voltage from being provided to the second data line.
By applying the above-mentioned embodiment, the noise caused by the first multiplexing signal and the second multiplexing signal can be reduced, and the first data voltage is prevented from being provided to the wrong data line.
Drawings
FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a multiplexer according to an embodiment of the present application;
FIG. 3 is a signal diagram illustrating a display device according to an exemplary embodiment of the present application;
FIG. 4 is a diagram illustrating a source driver according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a switching circuit according to an embodiment of the present application;
FIG. 6 is a diagram illustrating a source driver according to another embodiment of the present application;
FIG. 7 is a schematic diagram illustrating a switching circuit according to another embodiment of the present application;
FIG. 8 is a schematic diagram of a display device according to another embodiment of the present application; and
fig. 9 is a schematic diagram illustrating a display device according to another embodiment of the present application.
Description of reference numerals:
10: display device
40: gate driver
100: controller
106: pixel circuit
SD: source driver
And MUX: multiplexer
P1, P2: output pin
DL1-DL 6: data line
GL1, GL 2: gate line
G1, G2: grid signal
VD1, VD 2: data voltage
VD1_ R, VD1_ G, VD1_ B: data voltage
VD2_ R, VD2_ G, VD2_ B: data voltage
CTL: control signal
XSTB: trigger signal
SL1-SL 3: multiplexing signals
t0-t 8: point in time
DR: data register
LT: latch device
OT: output circuit
OTC: output time controller
SW: switching circuit
STB: trigger signal
And HiZ: high impedance state
Detailed Description
While the spirit of the present disclosure will be described in detail and with reference to the drawings, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure.
As used herein, "first," "second," … …, etc., are not specifically intended to be sequential or in-line in meaning and are not intended to limit the present invention, but merely to distinguish one element or operation from another element or operation described in the same technical language.
As used herein, "electrically coupled" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and "electrically coupled" may mean that two or more elements are in operation or act with each other.
As used herein, the terms "comprising," "including," "having," "containing," and the like are open-ended terms that mean including, but not limited to.
As used herein, "and/or" includes any and all combinations of the described items.
With respect to the term (terms) used herein, it is generally understood that each term has its ordinary meaning in the art, in the disclosure herein, and in the specific context, unless otherwise indicated. Certain words used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the disclosure.
Fig. 1 is a schematic diagram of a display device 10 according to an embodiment of the present application. In the present embodiment, the display device 10 includes a controller 100, a pixel circuit 106, a source driver SD, a gate driver 40, data lines DL1-DL6, gate lines GL1, GL2, and a multiplexer MUX. In the present embodiment, the pixel circuits 106 are arranged in a matrix form. In one embodiment, the controller 100 is electrically connected to the source driver SD, the gate driver 40, and the multiplexer MUX. In one embodiment, the multiplexer MUX is electrically connected between the data lines DL1-DL6 and the output pins P1 and P2 of the source driver SD.
It should be noted that, although the display device 10 of 2 × 6 size is taken as an example for description in the present embodiment, the number of the elements and the lines in the display device 10 is not limited thereto, and other numbers of the elements and the lines are also within the scope of the present application.
In one embodiment, the gate driver 40 is configured to provide the gate signals G1 and G2 to the pixel circuits 106 row by row through the gate lines GL1 and GL2 to turn on the switches of the pixel circuits 106 in the pixel circuits 106 row by row.
In one embodiment, the source driver SD is configured to provide data voltages VD1 (including data voltages VD1_ R, VD1_ G, VD1_ B) and VD2 (including data voltages VD2_ R, VD2_ G, VD2_ B) to the multiplexer MUX through the output pins P1 and P2, respectively, according to the trigger signal XSTB. In addition, the source driver SD is further configured to stop outputting the data voltages VD1, VD2 to the multiplexer MUX according to the control signal CTL.
In one embodiment, the multiplexer MUX is configured to selectively turn on the output pin P1 to a corresponding one of the data lines DL1-DL6 and turn on the output pin P2 to another corresponding one of the data lines DL1-DL6 according to the multiplexing signals SL1-SL3 to provide the data voltages VD1 and VD2 to the corresponding one of the pixel circuits 106.
For example, referring to fig. 2, when the source driver SD outputs the data voltage VD1_ R (e.g., a data voltage corresponding to a red subpixel) through the output pin P1 and outputs the data voltage VD2_ R (e.g., a data voltage corresponding to a red subpixel) through the output pin P2, the multiplexer MUX may provide the data voltage VD1_ R to the data line DL1 and the connected pixel circuit 106 (e.g., a red subpixel circuit) and the data voltage VD2_ R to the data line DL4 and the connected pixel circuit 106 (e.g., a red subpixel circuit) according to the multiplexing signal SL 1.
Then, when the source driver SD outputs the data voltage VD1_ G (e.g., a data voltage corresponding to a green sub-pixel) through the output pin P1 and outputs the data voltage VD2_ G (e.g., a data voltage corresponding to a green sub-pixel) through the output pin P2, the multiplexer MUX may provide the data voltage VD1_ G to the data line DL5 and the connected pixel circuit 106 (e.g., a green sub-pixel circuit) and provide the data voltage VD2_ G to the data line DL2 and the connected pixel circuit 106 (e.g., a green sub-pixel circuit) according to the multiplexing signal SL 2.
Then, when the source driver SD outputs the data voltage VD1_ B (e.g., a data voltage corresponding to a blue subpixel) through the output pin P1 and outputs the data voltage VD2_ B (e.g., a data voltage corresponding to a blue subpixel) through the output pin P2, the multiplexer MUX may provide the data voltage VD1_ B to the data line DL5 and the connected pixel circuit 106 (e.g., a blue subpixel circuit) thereof and provide the data voltage VD2_ B to the data line DL2 and the connected pixel circuit 106 (e.g., a blue subpixel circuit) thereof according to the multiplexing signal SL 3.
Therefore, the pixel circuit 106 with the switch turned on by the gate signals G1 and G2 can perform display operation according to the data voltages VD1 and VD 2.
It should be noted that the connection manner of the multiplexer MUX is only an example, and the application is not limited thereto, and other connection manners are also within the scope of the application.
In one embodiment, the controller 100 is configured to generate the control signal CTL, the trigger signal XSTB, and the multiplexing signals SL1-SL 3. The controller 100 utilizes the control signal CTL to adjust a start time point (e.g., one of a rising edge and a falling edge) and/or an end time point (e.g., the other of a rising edge and a falling edge) of the multiplexed signals SL1-SL3, thereby reducing noise caused by the multiplexed signals SL1-SL 3. In addition, the controller 100 further uses the control signal CTL to make the source driver SD stop outputting the data voltages VD1, VD2 accordingly, so as to avoid erroneous output of the data voltages VD1, VD2 caused by adjusting the start time point and/or the stop time point of the multiplexing signals SL1-SL 3.
In one embodiment, the controller 100 receives a video signal from a host and generates the control signal CTL, the trigger signal XSTB, and the multiplexing signals SL1-SL3 according to the video signal. In one embodiment, the controller 100 generates the pulse of the control signal CTL at a predetermined time point corresponding to the video signal, thereby adjusting the multiplexing signals SL1-SL 3. In one embodiment, the predetermined time point may be determined according to a charging speed of the pixel circuit 106.
In an embodiment, the controller 100 may be implemented by a timing controller (timing controller), but the present application is not limited thereto. In one embodiment, the functions of the controller 100 may be implemented by a Programmable Logic Device (PLD) and/or other hardware circuits, which is not limited in this application.
The following description will be given with reference to fig. 1 to 3 for details of an operation example of the present application, but the present application is not limited to the operation example described below.
Referring to fig. 3, at a time point t0, the gate signal G1 starts to be output to turn on the switches of the pixel circuits 106 of the first row.
At time t1, trigger signal XSTB is at a falling edge. At this time, the source driver SD starts to output the data voltage VD1_ R to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB. At this time, the controller 100 starts outputting the multiplexing signal SL1, i.e., the time point t1 is substantially the starting time point of the multiplexing signal SL1, and the multiplexing signal SL1 is at the rising edge.
From time t1 to time t2, the multiplexer MUX turns on the output pin P1 and the data line DL1 according to the multiplexing signal SL1, so that the data line DL1 receives the data voltage VD1_ R from the source driver SD, and thus one of the pixel circuits 106 in the first row corresponding to the data line DL1 (e.g., the pixel circuits 106 in the first row and the first column) receives the data voltage VD1_ R.
At time point t2, control signal CTL is at a rising edge. At this time, the source driver SD stops outputting the data voltage VD1_ R according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplexing signal SL1 in response to the rising edge of the control signal CTL, i.e., the time t2 is substantially the stopping time of the multiplexing signal SL1, and the multiplexing signal SL1 is at the falling edge. In addition, the controller 100 starts outputting the multiplexing signal SL2 corresponding to the rising edge of the control signal CTL, i.e. the time point t2 is substantially the starting time point of the multiplexing signal SL2, and the multiplexing signal SL2 is at the rising edge.
At time t3, control signal CTL is at a falling edge and trigger signal XSTB is at a rising edge.
At time t4, trigger signal XSTB is at a falling edge. At this time, the source driver SD starts outputting the data voltage VD1_ G to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB.
From time t4 to time t5, the multiplexer MUX turns on the output pin P1 and the data line DL5 according to the multiplexing signal SL2, so that the data line DL5 receives the data voltage VD1_ G from the source driver SD, and thus one of the pixel circuits 106 in the first row corresponding to the data line DL1 (e.g., the pixel circuits 106 in the fifth column and the first row) receives the data voltage VD1_ G.
At time point t5, control signal CTL is at a rising edge. At this time, the source driver SD stops outputting the data voltage VD1_ G according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplexing signal SL2 in response to the rising edge of the control signal CTL, i.e., the time t5 is substantially the stopping time of the multiplexing signal SL2, and the multiplexing signal SL2 is at the falling edge. In addition, the controller 100 starts outputting the multiplexing signal SL3 corresponding to the rising edge of the control signal CTL, i.e. the time point t5 is substantially the starting time point of the multiplexing signal SL3, and the multiplexing signal SL3 is at the rising edge.
At time t6, trigger signal XSTB is on a rising edge.
At time t7, trigger signal XSTB is at a falling edge. At this time, the source driver SD starts to output the data voltage VD1_ B to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB.
From time t7 to time t8, the multiplexer MUX turns on the output pin P1 and the data line DL3 according to the multiplexing signal SL3, so that the data line DL3 receives the data voltage VD1_ B from the source driver SD, and thus one of the pixel circuits 106 in the first row corresponding to the data line DL3 (e.g., the pixel circuits 106 in the third column and the first row) receives the data voltage VD1_ B.
At time t8, the gate signal G1 stops outputting, and the switch of the pixel circuit 106 in the first row is turned off. At this time, the control signal CTL is at a rising edge. At this time, the source driver SD stops outputting the data voltage VD1_ B according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplexing signal SL3 in response to the rising edge of the control signal CTL, i.e., the time t8 is substantially the stopping time of the multiplexing signal SL3, and the multiplexing signal SL3 is at the falling edge.
Through the above operations, the start time point of the multiplexing signal SL2 is substantially the same as the stop time point of the multiplexing signal SL1, and the start time point of the multiplexing signal SL3 is substantially the same as the stop time point of the multiplexing signal SL2, so that the noises caused by the multiplexing signals SL1 to SL3 are cancelled out.
In addition, since the source driver SD stops outputting the data voltage VD1_ R, VD1_ G, VD1_ B in response to the control signal CTL, even if the start time point of the multiplexing signal SL2 is substantially the same as the stop time point of the multiplexing signal SL1, the data voltage VD1_ R is not erroneously supplied to the data line DL 5. Similarly, even if the start time of the multiplexing signal SL3 is substantially the same as the stop time of the multiplexing signal SL2, the data voltage VD1_ G is not erroneously supplied to the data line DL 3.
It should be noted that although the operations related to the data voltage VD1 outputted by the source driver SD are described as examples, the operations related to the data voltage VD2 are substantially the same, and therefore, the description thereof is omitted.
It should be noted that the polarities of the signals G1, XSTB, CTL, SL1-SL3 may be changed according to actual needs, so that the rising and falling edges of the signals may be exchanged according to actual situations. For example, the trigger signal XSTB and the control signal CTL can be inverted pulses, so at time t3, the trigger signal XSTB is at the falling edge, and the control signal CTL is at the rising edge. Therefore, the present application is not limited to the above-described operation examples.
In an embodiment of the present invention, the source driver SD may make the output pins P1 and P2 in the high impedance state during the period from the time point t2 to the time point t4 and/or from the time point t5 to the time point t 7. In some embodiments, the high impedance state may cause the output pins P1, P2 to be connected to a large impedance or to be in a floating (floating) state.
In an embodiment of the present invention, the source driver SD may connect the output pins P1 and P2 to ground to reset the voltages on the data lines DL2, DL3, DL5 and DL6 during the part or all of the period from the time point t2 to the time point t4 and/or the part or all of the period from the time point t5 to the time point t 7.
For example, at the time point t2, the source driver SD may start to ground the output pins P1 and P2 according to the rising edge of the control signal CTL to stop outputting the data voltage VD1_ R, VD2_ R. Also, at the time point t3, the source driver SD may start to put the output pins P1 and P2 in a high impedance state according to the rising edge of the trigger signal XSTB.
In various embodiments, at the time point t2, the source driver SD may start to put the output pins P1 and P2 in a high impedance state according to the rising edge of the control signal CTL to stop outputting the data voltage VD1_ R, VD2_ R. Also, at the time point t3, the source driver SD may start to ground the output pins P1 and P2 according to the rising edge of the trigger signal XSTB.
Fig. 4 is a schematic diagram of a source driver SD according to an embodiment of the present application. In one embodiment, the source driver SD includes a data register DR, a latch LT, an output circuit OT, an output time controller OTC, and a switching circuit SW.
In one embodiment, the data register DR is configured to provide the data voltages VD1, VD2 to the latch LT. The output timing controller OTC is used for controlling the latch LT to provide the data voltages VD1, VD2 to the output circuit OT in response to the trigger signal XSTB. The output circuit OT supplies the data voltages VD1, VD2 to the output pins P1, P2 via the switching circuit SW.
In one embodiment, the switching circuit SW selectively electrically connects the output pins P1 and P2 to ground according to the control signal CTL. In one embodiment, the switching circuit SW can be switched according to the trigger signal XSTB to make the output pins P1 and P2 in a high impedance state.
For example, referring to fig. 5, at the aforementioned time point t2, the switching circuit SW can switch according to the rising edge of the control signal CTL to start grounding the output pins P1 and P2. At the aforementioned time point t3, the switching circuit SW can be switched according to the rising edge of the trigger signal XSTB, so that the output pins P1 and P2 are initially in a high impedance state (e.g., indicated as a high impedance state HiZ). Then, at the aforementioned time point t4, the switching circuit SW can switch according to the falling edge of the trigger signal XSTB to start to make the output pins P1 and P2 output the data voltages VD1 and VD 2.
It should be noted that in some embodiments, the switching circuit SW can also be integrated into the output circuit OT, and the present application is not limited to the above embodiments.
Referring to fig. 6, in other embodiments, the output of the connection switching circuit SW of the output circuit OT also has the capability of being in a high impedance state HiZ. In these embodiments, the output circuit OT can receive the trigger signal XSTB and accordingly determine the output or data voltages VD1, VD2 or make the output terminal thereof in the high impedance state HiZ. The switching circuit SW is configured to switch between the control signal CTL and the trigger signal XSTB to ground the output pins P1 and P2, or to output the data voltages VD1 and VD2 from the output circuit OT or to present a high impedance state HiZ from the output terminal of the output circuit OT at the output pins P1 and P2.
For example, referring to fig. 7, at the aforementioned time point t2, the switching circuit SW can switch according to the rising edge of the control signal CTL to start grounding the output pins P1 and P2. At the aforementioned time point t3, the output terminal of the output circuit OT may start to be in the high impedance state HiZ according to the rising edge of the trigger signal XSTB. Also, the switching circuit SW can be switched according to the rising edge of the trigger signal XSTB to start to make the output pins P1 and P2 assume the high impedance state HiZ from the output terminal of the output circuit OT. At the aforementioned time point t4, the output circuit OT can start outputting the data voltages VD1 and VD2 according to the falling edge of the trigger signal XSTB, so as to start the switching circuit SW outputting the data voltages VD1 and VD2 to the output pins P1 and P2.
Referring to fig. 8, in other embodiments, the switching circuit SW may also be provided independently of the source driver SD. In these embodiments, the source driver SD can receive the trigger signal XSTB and accordingly determine to make the output pins P1 and P2 assume the high impedance state HiZ or output the data voltages VD1 and VD 2. The switching circuit SW is used for switching according to the control signal CTL and the trigger signal XSTB to ground the corresponding one of the data lines DL1-DL6, or receive the data voltages VD1 and VD2 from the source driver SD or receive the high impedance state HiZ from the output pins P1 and P2 from the corresponding one of the data lines DL1-DL 6. For details, reference is made to the above paragraphs, which are not repeated herein. In addition, in different embodiments, the switching circuit SW can also be switched among three states to perform grounding, to assume a high impedance state HiZ, or to output the data voltages VD1, VD2 (e.g., similar to the embodiment of fig. 5, respectively).
Referring to FIG. 9, in some other embodiments, the switch circuit SW may also be disposed between the multiplexer MUX and the data lines DL1-DL 6. The switching circuit SW is used for switching according to the control signal CTL and the trigger signal XSTB to ground the corresponding one of the data lines DL1-DL6, or to receive the data voltages VD1 and VD2 from the source driver SD and the multiplexer MUX or receive the high impedance state HiZ from the output pins P1 and P2 from the corresponding one of the data lines DL1-DL 6. For details, reference is made to the above paragraphs, which are not repeated herein. Similarly, in different embodiments, the switching circuit SW can also switch between three states to ground, assume the high impedance state HiZ, or output the data voltages VD1, VD2 (e.g., similar to the corresponding embodiment of fig. 5).
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A display device, comprising:
a source driver for outputting a first data voltage and a second data voltage in sequence according to a trigger signal;
a multiplexer for receiving the first data voltage and the second data voltage and outputting the first data voltage and the second data voltage to different data lines in sequence according to a first multiplexing signal and a second multiplexing signal; and
a controller for generating a control signal to control a stop time point of the first multiplexing signal and a start time point of the second multiplexing signal to be substantially identical to each other, and for controlling the source driver to stop outputting the first data voltage corresponding to the control signal so as not to erroneously supply the first data voltage to the data lines.
2. The display device of claim 1, wherein a time point at which the source driver stops outputting the first data voltage is substantially the same as the suspension time point of the first multiplexing signal.
3. The display device according to claim 1, wherein an output pin for outputting the first data voltage and the second data voltage in the source driver is grounded during at least a part of a period in which the source driver stops outputting the first data voltage.
4. The display device of claim 1, wherein the source driver comprises:
and the switching circuit is used for selectively and electrically connecting an output pin which is used for outputting the first data voltage and the second data voltage in the source driver to the ground according to the control signal.
5. The display device according to claim 4, wherein the switching circuit is further configured to switch according to the trigger signal to make the output pin in a high impedance state.
6. The display apparatus according to claim 4, wherein the switching circuit switches according to a first edge of the control signal to electrically connect the output pin to the ground.
7. The display apparatus according to claim 4, wherein the switching circuit is further configured to switch according to a first edge of the trigger signal to make the output pin in a high impedance state, and wherein the switching circuit switches according to a second edge of the trigger signal to make the output pin output the second data voltage.
8. The display device of claim 1, wherein the suspension time point of the first multiplexing signal, the start time point of the second multiplexing signal, and the time point when the source driver stops outputting the first data voltage are substantially the same as a first edge time point of the control signal.
9. A display device, comprising:
a source driver for outputting a first data voltage and a second data voltage in sequence according to a trigger signal;
a multiplexer for receiving the first data voltage and the second data voltage and outputting the first data voltage and the second data voltage to a first data line and a second data line in sequence according to a first multiplexing signal and a second multiplexing signal;
a controller for generating a control signal to control a time point of a falling edge of the first multiplexing signal and a time point of a rising edge of the second multiplexing signal to be substantially identical to each other, or to control a time point of a rising edge of the first multiplexing signal and a time point of a falling edge of the second multiplexing signal to be substantially identical to each other, and to control the source driver to stop outputting the first data voltage corresponding to the control signal so as not to erroneously supply the first data voltage to the data lines; and
a switching circuit for switching according to the control signal to prevent the first data voltage from being provided to the second data line.
10. The display device of claim 9, wherein the switching circuit is configured to switch according to the control signal to selectively electrically connect the first data line and the second data line to a ground.
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| TW107102731A TWI659404B (en) | 2018-01-25 | 2018-01-25 | Display device |
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| TWI673633B (en) | 2018-03-13 | 2019-10-01 | 友達光電股份有限公司 | Touch display panel |
| TWI700685B (en) * | 2019-06-27 | 2020-08-01 | 敦泰電子有限公司 | Flat panel display and wearable device |
| TWI706392B (en) * | 2019-07-25 | 2020-10-01 | 友達光電股份有限公司 | Display device and operating method thereof |
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Also Published As
| Publication number | Publication date |
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| TW201933311A (en) | 2019-08-16 |
| CN108597433A (en) | 2018-09-28 |
| TWI659404B (en) | 2019-05-11 |
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