TWI659404B - Display device - Google Patents

Abstract

A display device includes: a source driver, a multiplexer, and a controller. The source driver is configured to sequentially output a first data voltage and a second data voltage according to a trigger signal. A multiplexer is used to receive the first data voltage and the second data voltage, and sequentially output the first data voltage and the second data voltage to different data according to a first multiplex signal and a second multiplex signal. line. The controller is used to generate a control signal to control a suspension time point of the first multiplex signal and a start time point of the second multiplex signal to be substantially the same as each other, and to control the source driver to stop corresponding to the control signal The first data voltage is output.

Description

Display device

This case relates to an electronic device. Specifically, the present application relates to a display device.

With the development of technology, display devices have been widely used in people's lives.

A typical display device may include a gate driver, a source driver, and a pixel circuit. The gate driver is used to provide a gate signal to the pixel circuit, so that the switch of the pixel circuit is turned on. The source driver is used to provide the data voltage to the pixel circuit with the switch turned on, so that the pixel circuit performs display corresponding to the data voltage.

An embodiment of the present invention relates to a display device. According to an embodiment of the present invention, the source driver of the display device includes a source driver, a multiplexer, and a controller. The source driver is configured to sequentially output a first data voltage and a second data voltage according to a trigger signal. Multiplexer It is used to receive the first data voltage and the second data voltage, and sequentially output the first data voltage and the second data voltage to different data lines according to a first multiplex signal and a second multiplex signal. The controller is used to generate a control signal to control a suspension time point of the first multiplex signal and a start time point of the second multiplex signal to be substantially the same as each other, and to control the source driver to stop corresponding to the control signal The first data voltage is output.

Another aspect of the present invention relates to a display device. According to an embodiment of the present invention, the source driver includes a source driver, a multiplexer, a controller, and a switching circuit. The source driver is configured to sequentially output a first data voltage and a second data voltage according to a trigger signal. A multiplexer is used for receiving the first data voltage and the second data voltage, and sequentially outputting the first data voltage and the second data voltage to a first data voltage according to a first multiplex signal and a second multiplex signal. A data line and a second data line. The controller is configured to generate a control signal to control a time point of a falling edge of the first multiplexing signal and a time point of a rising edge of the second multiplexing signal to be substantially the same as each other, or to control the first multiplexing signal. The time point of a rising edge and the time point of a falling edge of the second multiplex signal are substantially the same as each other. The switching circuit is used for switching according to the control signal to prevent the first data voltage from being provided to the second data line.

By applying the above-mentioned embodiment, noise caused by the first multiplex signal and the second multiplex signal can be reduced, and the provision of the first data voltage to the wrong data line can be avoided.

10‧‧‧ display device

40‧‧‧Gate driver

100‧‧‧ Controller

106‧‧‧pixel circuit

SD‧‧‧Source Driver

MUX‧‧‧Multiplexer

P1, P2‧‧‧ output pins

DL1-DL6‧‧‧Data line

GL1, GL2‧‧‧Gate line

G1, G2‧‧‧Gate signal

VD1, VD2‧‧‧ data voltage

VD1_R, VD1_G, VD1_B‧‧‧Data voltage

VD2_R, VD2_G, VD2_B‧‧‧Data voltage

CTL‧‧‧Control signal

XSTB‧‧‧Trigger signal

SL1-SL3 ‧‧‧ Multiplex Signal

t0-t8‧‧‧Time

DR‧‧‧Data Register

LT‧‧‧Latch

OT‧‧‧ output circuit

OTC‧‧‧Output time controller

SW‧‧‧Switching circuit

STB‧‧‧Trigger signal

HiZ‧‧‧High impedance state

FIG. 1 is a schematic diagram of a display device according to an embodiment of the present case; FIG. 2 is a schematic diagram of a multiplexer according to an embodiment of the present case; and FIG. 3 is a schematic diagram of a multiplexer according to an embodiment of the present case Signal schematic diagram of a display device; FIG. 4 is a schematic diagram of a source driver according to an embodiment of the present case; FIG. 5 is a schematic diagram of a switching circuit according to an embodiment of the present case; A schematic diagram of a source driver according to an embodiment; FIG. 7 is a schematic diagram of a switching circuit according to another embodiment of the present invention; and FIG. 8 is a schematic diagram of a display device according to another embodiment of the present invention. And FIG. 9 is a schematic diagram of a display device according to another embodiment of the present invention.

The following will clearly illustrate the spirit of the present disclosure with diagrams and detailed descriptions. Any person with ordinary knowledge in the technical field who understands the embodiments of the present disclosure can be changed and modified by the techniques taught in the present disclosure. It does not depart from the spirit and scope of this disclosure.

Regarding the "first", "second", ..., etc. used herein, they do not specifically mean the order or order, nor are they used to limit the present invention. They are only used to distinguish elements described in the same technical terms or operating.

As used in this article, "electrical coupling" can mean that two or more components make direct physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "electrical coupling" can also mean Two or more elements operate or act on each other.

The terms "including", "including", "having", "containing" and the like used in this article are all open-ended terms, which means including but not limited to.

As used herein, "and / or" includes any and all combinations of the things described.

Regarding the terms used in this article, unless otherwise specified, each term usually has the ordinary meaning of being used in this field, the content disclosed here, and the special content. Certain terms used to describe this disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of this disclosure.

FIG. 1 is a schematic diagram of a display device 10 according to an embodiment of the present invention. In this embodiment, the display device 10 includes a controller 100, a pixel circuit 106, a source driver SD, a gate driver 40, data lines DL1-DL6, gate lines GL1, GL2, and a multiplexer MUX. In this embodiment, the pixel circuits 106 are arranged in a matrix form. In one embodiment, the controller 100 is electrically connected to the source driver SD, the gate driver 40 and the multiplexer MUX. In one embodiment, the multiplexer MUX is electrically connected to the data line. Between DL1-DL6 and the output pins P1 and P2 of the source driver SD.

It should be noted that in this embodiment, although a 2 * 6 size display device 10 is used as an example for description, the number of each component and circuit in the display device 10 is not limited to this. The line is also within the scope of this case.

In one embodiment, the gate driver 40 is used to provide the gate signals G1 and G2 to the pixel circuit 106 row by row through the gate lines GL1 and GL2 to turn on the switches of the pixel circuit 106 in the pixel circuit 106 row by row.

In one embodiment, the source driver SD is used to provide data voltages VD1 (including the following data voltages VD1_R, VD1_G, VD1_B) and VD2 (including the following data voltages VD2_R) through the output pins P1 and P2 according to the trigger signal XSTB. , VD2_G, VD2_B) to the multiplexer MUX. In addition, the source driver SD is also used to stop outputting the data voltages VD1, VD2 to the multiplexer MUX according to the control signal CTL.

In one embodiment, the multiplexer MUX is used to selectively turn on a corresponding one of the output pins P1 to the data lines DL1-DL6 and to turn on the output pins P2 to the data lines DL1-DL6 according to the multiplex signals SL1-SL3. The other corresponding one is to provide the data voltages VD1 and VD2 to the corresponding one in the pixel circuit 106.

For example, referring to FIG. 2 at the same time, the source driver SD outputs the data voltage VD1_R (for example, the data voltage corresponding to the red sub-pixel) through the output pin P1, and outputs the data voltage VD2_R (for example, the corresponding corresponding voltage) through the output pin P2. Data voltage of the red sub-pixel), the multiplexer MUX can provide the data voltage VD1_R to the source according to the multiplex signal SL1. The material line DL1 and the connected pixel circuit 106 (for example, a red sub-pixel circuit), and the data voltage VD2_R are provided to the data line DL4 and the connected pixel circuit 106 (for example, a red sub-pixel circuit).

Then, when the source driver SD outputs the data voltage VD1_G (for example, the data voltage corresponding to the green sub-pixel) through the output pin P1, and outputs the data voltage VD2_G (for example, the data voltage corresponding to the green sub-pixel) through the output pin P2 The multiplexer MUX can provide the data voltage VD1_G to the data line DL5 and the connected pixel circuit 106 (such as a green sub-pixel circuit) according to the multiplex signal SL2, and the data voltage VD2_G to the data line DL2 and its The connected pixel circuit 106 (for example, a green sub-pixel circuit).

Then, the source driver SD outputs the data voltage VD1_B (for example, the data voltage corresponding to the blue sub-pixel) through the output pin P1, and outputs the data voltage VD2_B (for example, the data voltage corresponding to the blue sub-pixel) through the output pin P1. ), The multiplexer MUX can provide the data voltage VD1_B to the data line DL3 and its connected pixel circuit 106 (such as a blue sub-pixel circuit) and the data voltage VD2_B to the data line according to the multiplex signal SL3. DL6 and the connected pixel circuit 106 (for example, a blue sub-pixel circuit).

Thereby, the pixel circuit 106 which is turned on by the gate signals G1 and G2 can perform a display operation according to the data voltages VD1 and VD2.

It should be noted that the connection mode of the above-mentioned multiplexer MUX is merely an example, and this case is not limited thereto, and other connection modes are also within the scope of this case.

In one embodiment, the controller 100 is used to generate the aforementioned control signals CTL, trigger signals XSTB, and multiplex signals SL1-SL3. The controller 100 uses the control signal CTL to adjust the start time point of the multiplex signals SL1-SL3 (for example, one of the rising edge and the falling edge) and / or the stop time point (for example, the other of the rising edge and the falling edge). ) To reduce the noise caused by the multiplex signals SL1-SL3. In addition, the controller 100 also uses the control signal CTL to cause the source driver SD to stop outputting the data voltages VD1 and VD2 accordingly, so as to avoid the data voltage caused by adjusting the start time and / or the suspension time of the multiplex signals SL1-SL3. VD1, VD2 error output.

In one embodiment, the controller 100 may receive an image signal from the host, and generate the aforementioned control signal CTL, trigger signal XSTB, and multiplex signals SL1-SL3 according to the image signal. In an embodiment, the controller 100 generates a pulse of the control signal CTL at a preset time corresponding to the image signal, thereby adjusting the multiplex signals SL1-SL3. In one embodiment, the aforementioned predetermined time point may be determined according to the charging speed of the pixel circuit 106.

In one embodiment, the controller 100 may be implemented by a timing controller, but the present invention is not limited thereto. In an embodiment, the functions of the controller 100 may be implemented by a programmable logic device (PLD) and / or other hardware circuits therein, but the present invention is not limited thereto.

The details of an operation example of this case will be described below with reference to FIGS. 1-3, but this case is not limited to the following operation examples.

Referring to FIG. 3, at a time point t0, the gate signal G1 starts to output to turn on the switches of the pixel circuit 106 in the first column.

At time point t1, the trigger signal XSTB is at the falling edge. At this time, the source driver SD starts to output the data voltage VD1_R to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB. At this time, the controller 100 starts to output the multiplex signal SL1, that is, the time point t1 is approximately the start time of the multiplex signal SL1, and the multiplex signal SL1 is at the rising edge at this time.

From time point t1 to time point t2, the multiplexer MUX turns on the output pin P1 and the data line DL1 according to the multiplexing signal SL1, so that the data line DL1 receives the data voltage VD1_R from the source driver SD, so that the first One of the column pixel circuits 106 corresponding to the data line DL1 (such as the pixel circuit 106 located in the first row and the first column) receives the data voltage VD1_R.

At time t2, the control signal CTL is on the rising edge. At this time, the source driver SD stops outputting the data voltage VD1_R according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplexing signal SL1 corresponding to the rising edge of the control signal CTL, that is, the time point t2 is approximately the suspension time point of the multiplexing signal SL1, and the multiplexing signal SL1 is at the falling edge at this time. In addition, the controller 100 starts to output the multiplex signal SL2 corresponding to the rising edge of the control signal CTL, that is, the time point t2 is approximately the start time of the multiplex signal SL2, and the multiplex signal SL2 is at the rising edge at this time.

At time t3, the control signal CTL is on the falling edge, and the trigger signal XSTB is on the rising edge.

At time t4, the trigger signal XSTB is at the falling edge. At this time, the source driver SD starts to output the data voltage VD1_G to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB.

From time point t4 to time point t5, the multiplexer MUX turns on the output pin P1 and the data line DL5 according to the multiplexing signal SL2, so that the data line DL5 receives the data voltage VD1_G from the source driver SD, so that the first One of the column pixel circuits 106 corresponding to the data line DL1 (such as the pixel circuit 106 located in the fifth row and the first column) receives the data voltage VD1_G.

At time t5, the control signal CTL is on the rising edge. At this time, the source driver SD stops outputting the data voltage VD1_G according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplex signal SL2 in response to the rising edge of the control signal CTL, that is, the time point t5 is approximately the suspension time point of the multiplex signal SL2, and the multiplex signal SL2 is at the falling edge at this time. In addition, the controller 100 starts to output the multiplex signal SL3 corresponding to the rising edge of the control signal CTL, that is, the time point t5 is approximately the start time of the multiplex signal SL3, and the multiplex signal SL3 is at the rising edge at this time.

At time t6, the trigger signal XSTB is on the rising edge.

At time point t7, the trigger signal XSTB is at the falling edge. At this time, the source driver SD starts to output the data voltage VD1_B to the multiplexer MUX through the output pin P1 according to the falling edge of the trigger signal XSTB.

From time point t7 to time point t8, the multiplexer MUX turns on the output pin P1 and the data line DL3 according to the multiplexing signal SL3, so that the data line DL3 receives the data voltage VD1_B from the source driver SD, so that the first One of the column pixel circuits 106 corresponding to the data line DL3 (such as the pixel circuit 106 located in the third row and the first column) receives the data voltage VD1_B.

At time point t8, the gate signal G1 stops outputting, and the switches of the pixel circuit 106 in the first column are turned off. At this time, the control signal CTL is on the rise edge. At this time, the source driver SD stops outputting the data voltage VD1_B according to the rising edge of the control signal CTL. In addition, the controller 100 stops outputting the multiplex signal SL3 corresponding to the rising edge of the control signal CTL, that is, the time point t8 is approximately the suspension time point of the multiplex signal SL3, and the multiplex signal SL3 is at the falling edge at this time.

Through the above operations, the start time point of the multiplex signal SL2 can be made substantially the same as the stop time point of the multiplex signal SL1, and the start time point of the multiplex signal SL3 can be made substantially the same as the stop time point of the multiplex signal SL2. Thus, the noise caused by the multiplex signals SL1-SL3 cancels each other.

In addition, since the source driver SD stops outputting the data voltages VD1_R, VD1_G, and VD1_B corresponding to the control signal CTL, even if the start time point of the multiplex signal SL2 is substantially the same as the suspend time of the multiplex signal SL1, it will not cause the data voltage VD1_R is incorrectly provided to data line DL5. Similarly, even if the start time point of the multiplex signal SL3 is substantially the same as the stop time point of the multiplex signal SL2, the data voltage VD1_G is not erroneously provided to the data line DL3.

It should be noted that, although the above description is based on the related operation of the source driver SD outputting the data voltage VD1 as an example, the related operation of the data voltage VD2 is also substantially the same, so it will not be repeated here.

In addition, it should be noted that the polarity of the above signals G1, XSTB, CTL, SL1-SL3 can be changed as needed, so the rising and falling edges of the above signals will also be exchanged according to the actual situation. For example, the trigger signal XSTB and the control signal CTL may be reverse pulses, so at time point t3, the trigger signal XSTB is on the falling edge and the control signal CTL is on the rising edge. Yes Therefore, this case is not limited to the above operation examples.

In an embodiment of the present invention, during a part or all of the period from time point t2 to time point t4, and / or a part or all of period from time point t5 to time point t7, the source driver SD can make the output Pins P1 and P2 are in a high impedance state. In some embodiments, being in a high-impedance state may be such that the output pins P1 and P2 are connected to a large impedance, or may be in a floating state.

In an embodiment of the present invention, during a part or all of the period from time point t2 to time point t4, and / or a part or all of period from time point t5 to time point t7, the source driver SD can make the output The pins P1 and P2 are grounded to reset the voltages on the data lines DL2, DL3, DL5, and DL6.

For example, at time point t2, the source driver SD may start to ground the output pins P1 and P2 according to the rising edge of the control signal CTL to stop outputting the data voltages VD1_R and VD2_R. In addition, at time point t3, the source driver SD can start to make the output pins P1 and P2 in a high-impedance state according to the rising edge of the trigger signal XSTB.

In different embodiments, at time t2, the source driver SD may start to put the output pins P1 and P2 in a high-impedance state according to the rising edge of the control signal CTL to stop outputting the data voltages VD1_R and VD2_R. In addition, at time t3, the source driver SD can start to ground the output pins P1 and P2 according to the rising edge of the trigger signal XSTB.

FIG. 4 is a schematic diagram of a source driver SD according to an embodiment of the present invention. In one embodiment, the source driver SD includes a data register DR, a latch LT, an output circuit OT, an output time controller OTC, And switching circuit SW.

In one embodiment, the data register DR is used to provide the data voltages VD1 and VD2 to the latch LT. The output time controller OTC is used to control the latch signal LT to provide data voltages VD1 and VD2 to the output circuit OT in response to the trigger signal XSTB. The output circuit OT provides the data voltages VD1 and VD2 to the output pins P1 and P2 via the switching circuit SW.

In one embodiment, the switching circuit SW can selectively electrically connect the output pins P1 and P2 to the ground according to the control signal CTL. In one embodiment, the switching circuit SW can switch according to the trigger signal XSTB, so that the output pins P1 and P2 are in a high-impedance state.

For example, referring to FIG. 5 at the same time, at the aforementioned time point t2, the switching circuit SW may switch according to the rising edge of the control signal CTL to start grounding the output pins P1 and P2. In addition, at the aforementioned time point t3, the switching circuit SW may switch according to the rising edge of the trigger signal XSTB, so that the output pins P1 and P2 start to be in a high-impedance state (for example, expressed as a high-impedance state HiZ). Then, at the aforementioned time point t4, the switching circuit SW can switch according to the falling edge of the trigger signal XSTB to start the output pins P1 and P2 to output the data voltages VD1 and VD2.

It should be noted that, in some embodiments, the switching circuit SW can also be integrated into the output circuit OT, and this case is not limited to the above embodiments.

Referring to FIG. 6, in other embodiments, the output terminal of the connection switching circuit SW of the output circuit OT also has the capability of being in a high-impedance state HiZ. In these embodiments, the output circuit OT can receive the trigger signal XSTB and determine the output or data voltage VD1, VD2, or make it The output is HiZ. The switching circuit SW is used to switch the control signal CTL and the trigger signal XSTB to ground the output pins P1 and P2 or output the data voltages VD1 and VD2 from the output circuit OT to the output pins P1 and P2 or present them from the output circuit. High-Z state HiZ at the output of OT.

For example, referring to FIG. 7 at the same time, at the aforementioned time point t2, the switching circuit SW may switch according to the rising edge of the control signal CTL to start grounding the output pins P1 and P2. At the aforementioned time point t3, the output terminal of the output circuit OT may start to be in a high-impedance state HiZ according to the rising edge of the trigger signal XSTB. In addition, the switching circuit SW can switch according to the rising edge of the trigger signal XSTB to start making the output pins P1 and P2 present a high-impedance state HiZ from the output terminal of the output circuit OT. At the aforementioned time point t4, the output circuit OT can start to output the data voltages VD1 and VD2 according to the falling edge of the trigger signal XSTB, so as to start the switching circuit SW to output the data voltages VD1 and VD2 to the output pins P1 and P2.

Referring to FIG. 8, in other embodiments, the switching circuit SW may be provided independently of the source driver SD. In these embodiments, the source driver SD can receive the trigger signal XSTB, and then decide to cause the output pins P1 and P2 to assume the high-impedance state HiZ or output the data voltages VD1 and VD2. The switching circuit SW is used for switching according to the control signal CTL and the trigger signal XSTB to ground the counterparts in the data lines DL1-DL6, or to cause the counterparts in the data lines DL1-DL6 to receive the SD data voltage VD1 from the source driver VD2 or receives high-impedance state HiZ from output pins P1 and P2. Relevant details can refer to the above paragraphs, so they will not be repeated here. Also, in different In the embodiment, the switching circuit SW can also switch between three states to perform grounding, present a high-impedance state HiZ, or output data voltages VD1 and VD2 (for example, similar to the embodiment in FIG. 5).

Referring to FIG. 9, in other embodiments, the switching circuit SW may also be disposed between the multiplexer MUX and the data lines DL1 to DL6. The switching circuit SW is used to switch according to the control signal CTL and the trigger signal XSTB, so as to ground the counterparts in the data lines DL1-DL6, or cause the counterparts in the data lines DL1-DL6 to receive from the source driver SD and the multiplexer. The data voltage VD1, VD2 of the MUX or receives the high-impedance state HiZ from the output pins P1, P2. Relevant details can refer to the above paragraphs, so they will not be repeated here. Similarly, in different embodiments, the switching circuit SW can also switch between three states to ground, present a high-impedance state HiZ, or output data voltages VD1, VD2 (such as the embodiment similar to the corresponding FIG. 5) .

Although the present invention has been disclosed as above by way of example, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

Claims (10)

A display device includes: a source driver for sequentially outputting a first data voltage and a second data voltage according to a trigger signal; and a multiplexer for receiving the first data voltage and the second data voltage. Data voltage, and sequentially outputting the first data voltage and the second data voltage to different data lines according to a first multiplex signal and a second multiplex signal; and a controller for generating a control signal, A suspension time point for controlling the first multiplexing signal and a starting time point for the second multiplexing signal are substantially the same as each other, and are used to control the source driver to stop outputting the first data voltage corresponding to the control signal. The display device according to claim 1, wherein a time point at which the source driver stops outputting the first data voltage is substantially the same as the suspension time point of the first multiplex signal. The display device according to claim 1, wherein the source driver is used to output the first data voltage and the second data voltage during at least a part of the period when the source driver stops outputting the first data voltage. One of the output pins is grounded. The display device according to claim 1, wherein the source driver includes: a switching circuit for selectively electrically connecting the source driver to output the first data voltage and the second according to the control signal. An output pin of the data voltage is connected to a ground. The display device according to claim 4, wherein the switching circuit is further configured to switch according to the trigger signal so that the output pin is in a high impedance state. The display device according to claim 4, wherein the switching circuit switches according to a first edge of the control signal to electrically connect the output pin to the ground. The display device according to claim 4, wherein the switching circuit is further configured to switch according to a first edge of the trigger signal, so that the output pin is in a high-impedance state, and wherein the switching circuit is based on the trigger signal A second edge of is switched so that the output pin outputs the second data voltage. The display device according to claim 1, wherein the suspension time point of the first multiplex signal, the start time point of the second multiplex signal, and the time point when the source driver stops outputting the first data voltage It is substantially the same as the time point of a first edge of the control signal. A display device includes: a source driver for sequentially outputting a first data voltage and a second data voltage according to a trigger signal; and a multiplexer for receiving the first data voltage and the second data voltage. Data voltage, and sequentially output the first data voltage and the second data voltage to a first data line and a second data line according to a first multiplex signal and a second multiplex signal; a controller, The time point for generating a control signal to control a falling edge of the first multiplexing signal and the time point for a rising edge of the second multiplexing signal are substantially the same as each other, or controlling a time point of the first multiplexing signal. The time point of the rising edge and the time point of a falling edge of the second multiplex signal are substantially the same as each other; and a switching circuit for switching according to the control signal to prevent the first data voltage from being supplied to the second Data line. The display device according to claim 9, wherein the switching circuit is configured to switch according to the control signal to selectively electrically connect the first data line and the second data line to a ground.