TWI700685B - Flat panel display and wearable device - Google Patents

Abstract

A flat panel display and a wearable device are provided in the present invention. The wearable device includes a flat panel display. The flat panel display includes a data driver and a flat display panel. The data driver includes a plurality of output terminals. The flat panel includes a plurality of rows. Each row includes a plurality of pixels. The pixels are divided into first group pixels and second group pixels. The pixel driving period for each row includes a first group pixel driving period and a second group pixel driving period, wherein first group pixels are driven in first group pixel driving period and the second group pixels are driven in second group pixel driving period.

Description

Flat panel displays and wearable devices

The present invention relates to a flat-panel display technology. More specifically, the present invention relates to a flat-panel display and a wearable device using it.

As technology advances, wearable devices are becoming more and more popular. Due to the small size of the panel of the wearable device, it is not suitable for a driving circuit with a high number of pins. However, with the advancement of technology, people have higher and higher requirements for the resolution of the screen, and the improvement of the resolution also means that more pins of the drive circuit are needed. In order to reduce the number of pins of the driving circuit, in the design of the flat display panel, a multiplexer design is generally used to reduce the number of pins of the data driver. This design is especially important for small panels, such as those of wearable devices.

Figure 1 is a schematic diagram of a small panel of the prior art. Please refer to Figure 1. The small panel 101 has a 1-to-10 multiplexer 102 (MUX 1:10). Here, a 480RGB panel is used as an example. 480RGB requires 1440 data. If the above 1-to-10 multiplexer 102 is used, the data driver needs 144 pins plus 10 One control pin is used to control the multiplexer. However, the use of multiplexers will also increase manufacturing costs.

Therefore, there is a need for a newly designed display that can simultaneously reduce costs and achieve narrow bezels.

An object of the present invention is to provide a flat-panel display and a wearable device using the same, which can reduce the number of pins of the data driving circuit by grouping and separately driving pixels without excessive use of multiplexers, thereby realizing a display Narrow bezel design.

In view of this, the present invention provides a flat panel display. The flat display includes a data driver and a flat display panel. The data driver includes a plurality of data output terminals. The flat display panel includes a plurality of columns, each column includes a plurality of pixels, and each of the pixels is at least divided into a first group of pixels and a second group of pixels, wherein the driving time of each column of pixels includes the driving time of the first group of pixels and The second group of pixels driving time. During the first group of pixel driving time, the first group of pixels are driven, and during the second group of pixel driving time, the second group of pixels are driven.

The present invention also provides a wearable device. The wearable device includes a flat panel display, and the flat panel display includes a data driver and a flat display panel. The data driver includes a plurality of data output terminals. The flat display panel includes a plurality of columns, each column includes a plurality of pixels, and each of the pixels is at least divided into a first group of pixels and a second group of pixels, wherein the driving time of each column of pixels includes the driving time of the first group of pixels and The second group of pixels driving time. During the first group of pixel driving time, the first group of pixels are driven, and during the second group of pixel driving time, the second group of pixels are driven.

According to the flat display and the wearable device using the flat display according to the preferred embodiment of the present invention, the flat display panel includes a first group of multiplexing units and a second group of multiplexing units. The first group of multiplexing units are coupled between the plurality of data output terminals and the first group of pixels in each row. The second group of multiplexing units are coupled between the plurality of data output terminals and the second group of pixels in each row. The scanning time is divided into the driving time of the first group of pixels and the driving time of the second group of pixels. In the first group of pixel driving time, the second group of multiplexing units are turned off and the first group of multiplexing units are activated to drive the first group of pixels , In the second group of pixel driving time, turn off the first group of multiplexing units, and start the second group of multiplexing units to drive the second group of pixels.

According to the flat-panel display and the wearable device using the flat-panel display according to the preferred embodiment of the present invention, the first multiplexer unit includes a plurality of first multiplexer enabling circuits, which are coupled to the data driver to enable the first Group multiplexing unit. The second group of multiplexer units includes a plurality of second multiplexer enabling circuits coupled to the data driver to enable the second group of multiplexer units, wherein, during the driving time of the first group of pixels, the data driver controls the The first multiplexer enabling circuit enables the first group of multiplexed units, and controls the second multiplexer enabling circuits to disable the second group of multiplexed units to drive the first group of pixels, wherein, During the driving time of the second group of pixels, the data driver controls the second multiplexer enabling circuits to enable the second group of multiplexer units, and controls the first multiplexer enabling circuits to disable the first Group multiplexing units to drive the second group of pixels.

According to the flat panel display and the wearable device using the flat display according to the preferred embodiment of the present invention, the first group of multiplexing units includes a plurality of first multiplexers, and each first multiplexer includes an input terminal and a plurality of For the output end, the input end of each first multiplexer is correspondingly coupled to the corresponding data output end, and the output end of each first multiplexer is respectively coupled to the corresponding first group of pixels. The above-mentioned second group of multiplexers includes a plurality of second multiplexers, each second multiplexer includes an input end and a plurality of output ends, and the input end of each second multiplexer is correspondingly coupled to the corresponding data The output terminal, the output terminal of each second multiplexer is respectively coupled to the corresponding second group of pixels. In a preferred embodiment, the first multiplexer enabling circuit further includes a plurality of first switches, which are correspondingly coupled to a plurality of output terminals of the first multiplexer, and the first multiplexer enabling circuit enables In the first group of multiplexer units, the multiple first switches are turned on. The aforementioned second multiplexer enabling circuit further includes a plurality of second switches correspondingly coupled to a plurality of output terminals of the second multiplexer, and the second multiplexer enabling circuit enables the second group of multiplexers At this time, the plurality of second switches are turned on.

According to the flat display and the wearable device using the flat display according to the preferred embodiment of the present invention, each column of the flat display panel includes a first scan line and a second scan line. The first scan line is electrically connected to the first group of pixels. The second scan line is electrically connected to the second group of pixels. The flat display panel further includes a multiplexing unit and a gate driving circuit. The multiplexer unit includes a plurality of multiplexers, each multiplexer includes an input terminal and a plurality of output terminals, wherein the input terminal of each multiplexer is coupled to one of the corresponding data output terminals, each The multiple output terminals of a multiplexer are respectively coupled to the corresponding first group of pixels and the second group of pixels. For gate drive circuit To drive the first scan line and the second scan line respectively. When the first scan line is driven by the gate driving circuit, the data driver controls the multiplexing unit to drive the first group of pixels. When the second scan line is driven by the gate driving circuit, the data driver controls the multiplexing unit to drive the second group of pixels.

The present invention additionally provides a driving method of a flat panel display. The driving method of the flat panel display includes the following steps: divide the pixels on a plurality of columns of a flat display panel into a first group of pixels and a second group of pixels; divide the driving time of each column of pixels into a first group of pixel driving Time and a second group of pixel driving time; during the first group of pixel driving time, driving the first group of pixels; and during the second group of pixel driving time, driving the second group of pixels.

The spirit of the present invention is to group the pixels in each column and drive them in a time-sharing manner, thereby reducing the number of pins used in the data driving circuit without adding a multiplexer. Therefore, the volume of the wearable device can be further reduced.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments and accompanying drawings are described in detail as follows.

101: small panel

102:1 to 10 multiplexer

201: Flat panel display

202: Wearing Mechanism

301: Data Drive

302: Flat display panel

303: The first group of multiplexing units

304: The second group of multiplexing units

303-01~303-72: The first multiplexer

305-01~305-72: The first multiplexer enabling circuit

304-01~304-72: second multiplexer

306-01~306-72: The second multiplexer enabling circuit

M01~M10, M11~M20, M31~M40, M41~M50: Transistor

601: Panel layout

S800~S803: Process steps of the driving method of the flat panel display according to the preferred embodiment of the present invention

Figure 1 is a schematic diagram of a small panel of the prior art.

Figure 2 is a schematic diagram of a wearable device according to a preferred embodiment of the present invention.

FIG. 3 is a circuit diagram of a flat panel display 201 according to a preferred embodiment of the present invention.

Figure 4 is a circuit diagram of multiplexers 303-01 and 304-01 and multiplexer enabling circuits 305-01 and 306-01 according to a preferred embodiment of the present invention.

FIG. 5 shows the operation waveforms of the multiplexers 303-01 and 304-01 and the multiplexer enabling circuits 305-01 and 306-01 according to a preferred embodiment of the present invention.

FIG. 6 is a circuit diagram of a flat display panel 302 according to a preferred embodiment of the present invention.

FIG. 7 is an operation waveform diagram of the flat display panel 302 according to a preferred embodiment of the present invention.

FIG. 8 is a flowchart of a driving method of a flat panel display according to a preferred embodiment of the present invention.

Figure 2 is a schematic diagram of a wearable device according to a preferred embodiment of the present invention. Please refer to FIG. 2, this wearable device includes a flat display 201 and a wearable mechanism 202. FIG. 3 is a circuit diagram of a flat panel display 201 according to a preferred embodiment of the present invention. Please refer to FIG. 3, in this embodiment, the flat panel display 201 includes a data driver 301 and a flat display panel 302, where the flat display panel 302 can be a liquid crystal display panel, an organic light emitting diode display panel or other A flat display equivalent technology etc. can be realized recently, and the present invention is not limited to this. level The surface display panel 302 includes a plurality of columns, and each column includes a plurality of pixels. In this embodiment, 480RGB is used as an example. Therefore, each column has 1440 pixels.

In this embodiment, the aforementioned 1440 pixels are divided into a first group of pixels and a second group of pixels. Furthermore, in this embodiment, the panel includes a first group of multiplexing units 303 and a second group of multiplexing units 304. The first group of multiplexers 303 includes a plurality of first multiplexers 303-01 to 303-72 and corresponding first multiplexer enabling circuits 305-01 to 305-72. The second group of multiplexers 304 includes a plurality of second multiplexers 304-01 to 304-72 and corresponding second multiplexer enabling circuits 306-01 to 306-72. The output terminals of the multiplexers 303-01 to 303-72 of the first group of multiplexing unit 303 are coupled to the first group of pixels. The output terminals of the multiplexers 304-01 to 304-72 of the second group of multiplexing units 304 are coupled to the second group of pixels. Assuming that the multiplexers 303-01~303-72 and 304-01~304-72 each have 10 pins, the first group of pixels are 1~10, 21~30, 41~50...1421 ~1430 pixels; the second group of pixels are the 11th~20th, 31~40, 51~60...1431~1440 pixels.

Figure 4 is a circuit diagram of multiplexers 303-01 and 304-01 and multiplexer enabling circuits 305-01 and 306-01 according to a preferred embodiment of the present invention. Please refer to Figure 4, the first multiplexer 303-01 includes transistors M01~M10; the first multiplexer enabling circuit 305-01 includes transistors M11~M20; the second multiplexer 304-01 includes transistors M31~M40; The second multiplexer enabling circuit 306-01 includes transistors M41~M50.

FIG. 5 shows the operation waveforms of the multiplexers 303-01 and 304-01 and the multiplexer enabling circuits 305-01 and 306-01 according to a preferred embodiment of the present invention. Please refer to Figure 4 and Figure 5, in this embodiment is Take the P-type thin film transistor as an example. When the first scan line G1 starts to scan, the signal mux_sw1 changes from a logic high voltage to a logic low voltage, and the transistors M11~M20 are turned on at this time. When the signal mux1 changes from a logic high voltage to a logic low voltage, the transistor M01 is turned on. At this time, the data driver 301 provides the data D1 of the first pixel, which is transmitted to the first pixel through the transistors M01 and M11; when the signal mux2 is changed from the logic The high voltage turns into a logic low voltage and the transistor M02 is turned on. At this time, the data driver 301 provides the data D2 of the second pixel, which is transmitted to the second pixel through the transistors M02 and M12, and so on.

When the signal mux_sw1 changes from a logic low voltage to a logic high voltage, and the signal mux_sw2 changes from a logic high voltage to a logic low voltage, the transistors M41~M50 are turned on. When the signal mux1 changes from a logic high voltage to a logic low voltage, the transistor M31 is turned on. At this time, the data driver 301 provides data D11 of the eleventh pixel, which is transmitted to the eleventh pixel through the transistors M31 and M41; when the signal mux2 From the logic high voltage to the logic low voltage, the transistor M32 is turned on. At this time, the data driver 301 provides the data D12 of the twelfth pixel, and transmits it to the twelfth pixel through the transistors M32 and M42, and so on.

It can be seen from the above embodiment that the first multiplexer 303-01 and the second multiplexer 304-01 can be enabled/disabled by the signals mux_sw1 and mux_sw2. When the signal mux_sw1 is a logic high voltage, even if the transistors M01~M10 of the first multiplexer 303-01 are in the on state, the signal cannot reach the first pixel to the tenth pixel. Similarly, when the signal mux_sw2 is a logic high voltage, the second multiplexer 304-01 Even if the transistors M31~M40 are turned on, the signal will not reach the eleventh to twentieth pixels. Therefore, in this embodiment, only two additional control signals (signal mux_sw1 and signal mux_sw2) are used to achieve the goal of controlling 20 pixel channels. In other words, in this embodiment, only 12 pins are used to control 20 pixel channels. Without the switch design of the multiplexer enabling circuits 305-01 and 306-01, the data driver 301 would need 20 pins to control 20 pixel channels.

The above embodiments are implementations of multiplexers and multiplexer enabling circuits, thereby reducing the number of pins required by the data driver 301. To further reduce the number of pins, the pixels of a scan line can be divided into three groups. The data driver 301 only needs 48 data output pins, and the scan time needs to be divided into three. Similarly, the present invention can also divide the pixels into four groups, five groups, etc. The present invention is not limited to this.

The above-mentioned embodiment is implemented in the manner of a multiplexer cooperated with a multiplexer enabling circuit. In the following, another embodiment is provided.

FIG. 6 is a circuit diagram of a flat display panel 302 according to a preferred embodiment of the present invention. Please refer to Figure 6, the flat display panel 302 includes a multiplexer unit, the multiplexer unit includes a plurality of multiplexers, each multiplexer includes an input terminal and a plurality of output terminals, where each multiplexer The input terminal is coupled to one of the corresponding data output terminals, and the output terminals of each multiplexer are respectively coupled to the corresponding first group of pixels and the second group of pixels. As shown in the figure, the flat display panel 302 uses the panel wiring layout 601 to divide each column into two scan lines. The pixels on the first scan line G1 are the first group of pixels; the pixels on the second scan line G2 are the pixels For the second set of pixels. A preferred driving method is to use the left and right sides to configure the gate on array (GOA) on the substrate, and to drive the scan lines on the left and right sides respectively. Assuming that this panel is a 480RGB panel, each column has a total of 1440 pixels. Originally, 144 1-to-10 multiplexers are needed. Since each column is divided into two scan lines, and the first group of pixels of the first scan line G1 The corresponding data line is connected to the second group of pixels of the second scan line G2. In addition, in order to avoid the interleaving of the wiring layout, in this embodiment, the data line D1 corresponding to the first pixel is connected to the data line D1440 corresponding to the 1440th pixel, and the data line D2 corresponding to the second pixel is connected to the 1439th pixel. The data line D1439 corresponding to each pixel, and so on. With the above implementation, the number of pins that originally required 144 data drivers can be reduced to 72 pins without the need for an additional multiplexer. Therefore, the embodiment of the present invention greatly reduces the number of pins of the data driver, and can realize the design of a narrow-frame display.

FIG. 7 is an operation waveform diagram of the flat display panel 302 according to a preferred embodiment of the present invention. Please refer to Figure 7. When the scan line G1 is scanned, the data driver controls the multiplexer to output mux1~mux10 in sequence, turning on the corresponding switches to drive the first group of pixels (the pixels on the left half). When the scan line G2 is scanned, the data driver controls the multiplexer to output mux1~mux10 in sequence, turning on the corresponding switches to drive the second group of pixels (the pixels on the right half). In this embodiment, the panel design must connect D1 to D1440, D2 to D1439, ..., D10 to D1431, and so on. And in the second half of the time, the order of transmitting pixel data must be revised, and the order must be D1440→D1431.

In the above embodiment, the scan line is cut in half, the scan line on the left half is controlled by the left GOA, and the scan line on the right half is controlled by the right GOA. In this preferred embodiment, the design of adding a panel cable design and changing the timing of sending pixel data by the data driver achieves the purpose of reducing the number of pins of the data driver while maintaining the same design of multiplexers.

FIG. 8 is a flowchart of a driving method of a flat panel display according to a preferred embodiment of the present invention. Please refer to Figure 8. The driving method of this flat panel display includes the following steps:

Step S800: start.

Step S801: Divide the pixels on a plurality of columns of a flat display panel into a first group of pixels and a second group of pixels. For example, the two sets of multiplexing units as in the first embodiment described above are used to divide the pixels into the first group of pixels and the second group of pixels, or the gate driving method of the panel is modified to divide the pixels in one column into the left half of the pixel and the right half of the pixel. Half-edge pixels.

Step S802: divide the driving time of each column of pixels into a first group of pixel driving time and a second group of pixel driving time. As in the first embodiment, one scanning period is divided into two segments. During the first segment, the first group of pixels is driven by the first group of multiplexer units, and during the second segment, the second group of pixels is driven by the second group of multiplexer units. Group of pixels. In addition, as in the second embodiment, the column pixels can be directly divided into two parts and driven separately by the gate driving circuit.

Step S803: During the first group of pixel driving time, drive the first group of pixels, and during the second group of pixel driving time, drive the second group of pixels Pixels.

In summary, the spirit of the present invention is to group pixels in each column and drive them in a time-sharing manner, thereby reducing the number of pins used in the data driving circuit. Therefore, the volume of the wearable device can be further reduced, and a display with a narrow frame can be realized.

The specific embodiments proposed in the detailed description of the preferred embodiments are only used to facilitate the description of the technical content of the present invention, instead of restricting the present invention to the above-mentioned embodiments in a narrow sense, and do not exceed the spirit of the present invention and apply for patents below. The conditions of the scope, various changes and implementations made, all belong to the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

301: Data Drive

302: Flat display panel

303: The first group of multiplexing units

304: The second group of multiplexing units

303-01~303-72: The first multiplexer

305-01~305-72: The first multiplexer enabling circuit

304-01~304-72: second multiplexer

306-01~306-72: The second multiplexer enabling circuit

Claims (8)

A flat panel display includes: a data driver, including a plurality of data output terminals; and a flat display panel, including: a plurality of rows, each row includes a plurality of pixels, each of the pixels is divided into at least a first group of pixels and The second group of pixels; wherein the driving time of each column of pixels includes the first group of pixel driving time and the second group of pixel driving time, wherein, in the first group of pixel driving time, the first group of pixels are driven; wherein, in the second group Pixel driving time, driving a second group of pixels, where the flat display panel includes: a first group of multiplexing units coupled to the plurality of data output terminals and between the first group of pixels in each row; and a second A group of multiplexing units are coupled between the plurality of data output terminals and the second group of pixels in each row; wherein, a scanning time is divided into a first group of pixel driving time and a second group of pixel driving time, wherein During the driving time of the first group of pixels, turn off the second group of multiplexed units, and start the first group of multiplexed units to drive the first group of pixels; wherein, during the second group of pixel drive time, turn off the first group of multiplexed units and start The second group of multiplexers are used to drive the second group of pixels, wherein the first group of multiplexers includes: a plurality of first multiplexers, each of the first multiplexers includes an input terminal and a plurality of output terminals , The input terminals of each of the first multiplexers are correspondingly coupled Connected to the corresponding data output terminal, the output terminal of each of the first multiplexers is respectively coupled to the corresponding first group of pixels; and a plurality of first multiplexer enabling circuits; wherein, the second group of multiplexers It includes: a plurality of second multiplexers, each of the second multiplexers includes an input terminal and a plurality of output terminals, and the input terminal of each of the second multiplexers is correspondingly coupled to the corresponding data output terminal , The output terminals of each of the second multiplexers are respectively coupled to the corresponding second group of pixels; and a plurality of second multiplexer enabling circuits; wherein, during the driving time of the first group of pixels, the data driver controls the The first multiplexer enabling circuits are enabled to enable the first multiplexers, and the second multiplexer enabling circuits are controlled to disable the second multiplexers to drive the first group of pixels, wherein In the second set of pixel driving time, the data driver controls the second multiplexer enabling circuits to enable the second multiplexers, and controls the first multiplexer enabling circuits to disable the The first multiplexer to drive the second group of pixels. For the flat panel display described in item 1 of the scope of patent application, each of the first multiplexer enabling circuits includes: a plurality of first switches correspondingly coupled to a plurality of output terminals of the first multiplexer; When the first multiplexer enabling circuits enable the first group of multiplexer units, the plurality of first switches are turned on; wherein, each of the second multiplexer enabling circuits includes: A plurality of second switches are correspondingly coupled to a plurality of output terminals of the second multiplexer. When the second multiplexer enabling circuits enable the second group of multiplexer units, the plurality of second switches are Conduction. For the flat display described in item 1 of the scope of patent application, each column of the flat display panel includes: a first scan line electrically connected to the first group of pixels; and a second scan line electrically connected to the The second group of pixels; wherein, the flat display panel further includes: a multiplexer unit, including multiple multiplexers, each of the multiplexers includes an input terminal and a plurality of output terminals, wherein each of the multiple The input terminal of the multiplexer is coupled to one of the corresponding data output terminals, and the multiple output terminals of each of the multiplexers are respectively coupled to the corresponding first group of pixels and the second group of pixels; and a gate A pole drive circuit, wherein the gate drive circuit is used to drive the first scan line and the second scan line respectively; wherein, when the first scan line is driven by the gate drive circuit, the data driver controls the multiplexing unit, To drive the first group of pixels; wherein, when the second scan line is driven by the gate driving circuit, the data driver controls the multiplexing unit to drive the second group of pixels. As for the flat panel display described in any one of claims 1-3, wherein the flat panel display includes a liquid crystal panel or an organic light emitting diode panel. A wearable device includes: a flat display, including: a data driver, including a plurality of data output terminals; and a flat display panel, including: a plurality of rows, each row includes a plurality of pixels, each of the pixels is at least Divided into a first group of pixels and a second group of pixels; wherein, the driving time of each column of pixels includes the first group of pixel driving time and the second group of pixel driving time, wherein, during the first group of pixel driving time, the first group of pixels are driven Wherein, in the second set of pixel driving time, the second set of pixels are driven, wherein the flat display panel includes: a first set of multiplexing units coupled to the plurality of data output terminals and the first set of pixels in each row Between; and a second group of multiplexing units, coupled to the plurality of data output terminals and the second group of pixels in each row; wherein a scan time is divided into a first group of pixel driving time and a second group Pixel driving time, where, during the first group of pixel driving time, turn off the second group of multiplexing units, and start the first group of multiplexing units to drive the first group of pixels; wherein, during the second group of pixel driving time, turn off the A group of multiplexers are activated, and a second group of multiplexers are activated to drive the second group of pixels, wherein the first group of multiplexers includes: a plurality of first multiplexers, each of the first multiplexers Includes an input And a plurality of output terminals, the input terminal of each of the first multiplexers is correspondingly coupled to the corresponding data output terminal, and the output terminal of each of the first multiplexers is respectively coupled to the corresponding first group of pixels; And a plurality of first multiplexer enabling circuits; wherein the second group of multiplexers includes: a plurality of second multiplexers, each of the second multiplexers includes an input terminal and a plurality of output terminals, The input terminals of each of the second multiplexers are correspondingly coupled to the corresponding data output terminals, the output terminals of each of the second multiplexers are respectively coupled to the corresponding second group of pixels; and a plurality of second multiplexers A multiplexer enabling circuit; wherein, during the driving time of the first set of pixels, the data driver controls the first multiplexer enabling circuits to enable the first multiplexers and controls the second multiplexers to cause The enabling circuit disables the second multiplexers to drive the first group of pixels, wherein, during the second group of pixel driving time, the data driver controls the second multiplexer enabling circuits to enable the first group of pixels Two multiplexers, and control the first multiplexer enabling circuits to disable the first multiplexers to drive the second group of pixels. For the wearable device described in item 5 of the scope of patent application, wherein each of the first multiplexer enabling circuits includes: a plurality of first switches correspondingly coupled to a plurality of output terminals of the first multiplexer , When the first multiplexer enabling circuits enable the first group of multiplexed units, the plurality of first switches are turned on; Wherein, each of the second multiplexer enabling circuits includes: a plurality of second switches correspondingly coupled to a plurality of output terminals of the second multiplexer, and the second multiplexer enabling circuits are enabled In the second group of multiplexing units, the plurality of second switches are turned on. For the wearable device described in item 5 of the scope of patent application, each column of the flat display panel includes: a first scan line electrically connected to the first group of pixels; and a second scan line electrically connected The second group of pixels; wherein, the flat display panel further includes: a multiplexer unit, including multiple multiplexers, each of the multiplexers includes an input terminal and a plurality of output terminals, wherein each The input terminal of the multiplexer is coupled to one of the corresponding data output terminals, and the output terminals of each of the multiplexers are respectively coupled to the corresponding first group of pixels and the second group of pixels; and a A gate drive circuit, wherein the gate drive circuit is used to drive the first scan line and the second scan line respectively; wherein, when the first scan line is driven by the gate drive circuit, the data driver controls the multiplexing unit, To drive the first group of pixels; wherein, when the second scan line is driven by the gate driving circuit, the data driver controls the multiplexing unit to drive the second group of pixels. Such as the wearable device described in item 5 of the scope of patent application, wherein the flat display panel includes a liquid crystal panel or an organic light emitting diode surface board.

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