CN108597433A - Display device - Google Patents
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- CN108597433A CN108597433A CN201810394138.2A CN201810394138A CN108597433A CN 108597433 A CN108597433 A CN 108597433A CN 201810394138 A CN201810394138 A CN 201810394138A CN 108597433 A CN108597433 A CN 108597433A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
A display device includes: the source driver, the multiplexer and the controller are connected in series. The source driver is used for outputting a first data voltage and a second data voltage in sequence according to a trigger signal. The multiplexer is used for receiving the first data voltage and the second data voltage and sequentially outputting the first data voltage and the second data voltage to different data lines according to a first multiplexing signal and a second multiplexing signal. The controller generates a control signal to control a stop time point of the first multiplexing signal and a start time point of the second multiplexing signal to be substantially equal to each other, and controls the source driver to stop outputting the first data voltage in response to the control signal. The invention can reduce noise and avoid providing data voltage for wrong data line.
Description
Technical field
This application involves a kind of electronic devices.Specifically, this application involves a kind of display devices.
Background technology
With the development of science and technology, display device has been widely used in people’s lives.
Typical display device, it may include gate drivers, source electrode driver and pixel circuit.Gate drivers to
Grid signal is provided to pixel circuit, to enable the switch of pixel circuit open.Source electrode driver is providing data voltage to opening
The pixel circuit opened is closed, to enable pixel circuit be shown corresponding to data voltage.
Invention content
The embodiment of the application is related to a kind of display device.According to one embodiment of the application, the source electrode of display device
Driver includes：One source driver, a multiplexer and a controller.Source electrode driver is to according to a triggering letter
Number, sequentially export one first data voltage and one second data voltage.Multiplexer to receive first data voltage and
Second data voltage, and according to one first multiplex signal and one second multiplex signal, sequentially export first number
According to voltage and second data voltage to different data line.Controller is to generate a control signal, to control first multichannel
The time point at the beginning of the intermission point and second multiplex signal of multiplexed signals is substantially identical to each other, and to control
The source electrode driver is made to stop exporting first data voltage corresponding to the control signal.
Still another embodiment herein is related to a kind of display device.According to one embodiment of the application, source electrode driver packet
Include one source driver, a multiplexer, a controller and a switching circuit.Source electrode driver is to according to a triggering
Signal sequentially exports one first data voltage and one second data voltage.Multiplexer is receiving first data voltage
And second data voltage, and according to one first multiplex signal and one second multiplex signal, sequentially export this first
Data voltage and second data voltage are to one first data line and one second data line.Controller is believed to generate a control
Number, to control time point and the rising edge of second multiplex signal of a falling edge of first multiplex signal
Time point is substantially identical to each other, or controls time point and second multiplexing of a rising edge of first multiplex signal
The time point of one falling edge of signal is substantially identical to each other.Switching circuit according to the control signal to switch over, to prevent
First data voltage is provided to second data line.
Through an above-mentioned embodiment is applied, make an uproar caused by the first multiplex signal, the second multiplex signal can be lowered
Sound, and avoid providing the first data voltage to the data line of mistake.
Description of the drawings
Fig. 1 is the schematic diagram for implementing the display device exemplified according to the application one；
Fig. 2 is the schematic diagram for implementing the multiplexer exemplified according to the application one；
Fig. 3 is the signal schematic representation according to the display device shown in one operation example of the application；
Fig. 4 is the schematic diagram for implementing the source electrode driver exemplified according to the application one；
Fig. 5 is the schematic diagram for implementing the switching circuit exemplified according to the application one；
Fig. 6 is the schematic diagram according to another source electrode driver for implementing to exemplify of the application；
Fig. 7 is the schematic diagram according to another switching circuit for implementing to exemplify of the application；
Fig. 8 is the schematic diagram according to another display device for implementing to exemplify of the application；And
Fig. 9 is the schematic diagram according to another display device for implementing to exemplify of the application.
Reference sign：
10：Display device
40：Gate drivers
100：Controller
106：Pixel circuit
SD：Source electrode driver
MUX：Multiplexer
P1、P2：Output pin
DL1-DL6：Data line
GL1、GL2：Grid line
G1、G2：Grid signal
VD1、VD2：Data voltage
VD1_R、VD1_G、VD1_B：Data voltage
VD2_R、VD2_G、VD2_B：Data voltage
CTL：Control signal
XSTB：Trigger signal
SL1-SL3：Multiplex signal
t0-t8：Time point
DR：Data register
LT：Latch unit
OT：Output circuit
OTC：Output time controller
SW：Switching circuit
STB：Trigger signal
HiZ：High impedance status
Specific implementation mode
To understand the spirit for illustrate disclosed content with attached drawing and in detail narration below, any affiliated technology leads
Those of ordinary skill should can be taught after the embodiment for understanding disclosed content by disclosed content in domain
The technology shown is changed and modifies, without departing from the spirit and scope of disclosed content.
About " first " used herein, " second " ... etc., not especially censure the meaning of order or cis-position,
Nor to limit the present invention, only for distinguishing the element described with same technique term or operation.
About " electric property coupling " used herein, can refer to two or multiple element mutually directly make entity or be electrically connected with
It touches, or mutually puts into effect indirectly body or in electrical contact, and " electric property coupling " also can refer to two or multiple element mutual operation or action.
It is the term of opening, i.e., about "comprising" used herein, " comprising ", " having ", " containing " etc.
Mean including but not limited to.
Include then any of the things or all combinations about "and/or" used herein.
About word used herein (terms), in addition to having and especially indicating, usually have each word using herein
In field, in content disclosed herein with the usual meaning in special content.Certain words to describe the disclosure will be under
Or discussed in the other places of this specification, to provide those skilled in the art's guiding additional in the description in relation to the disclosure.
Fig. 1 is the schematic diagram for implementing the display device 10 exemplified according to the application one.In this example it is shown that device
10 include controller 100, pixel circuit 106, source electrode driver SD, gate drivers 40, data line DL1-DL6, grid line
GL1, GL2 and multiplexer MUX.In the present embodiment, pixel circuit 106 is arranged in matrix.In an embodiment
In, controller 100 is electrically connected source electrode driver SD, gate drivers 40 and multiplexer MUX.In one embodiment,
Multiplexer MUX is electrically connected between data line DL1-DL6 and output pin P1, P2 of source electrode driver SD.
It should be noted that in the present embodiment, though being illustrated by taking the display device 10 of 2 × 6 sizes as an example, however showing dress
The quantity for setting each element and circuit in 10 is not limited thereto, the said elements and circuit of other quantity, also in the application model
Among enclosing.
In one embodiment, gate drivers 40 provide grid signal G1, G2 extremely line by line to penetrate grid line GL1, GL2
Pixel circuit 106, to open the switch of the pixel circuit 106 in pixel circuit 106 line by line.
In one embodiment, source electrode driver SD through output pin P1, P2 according to trigger signal XSTB, carrying respectively
For data voltage VD1 (including following data voltage VD1_R, VD1_G, VD1_B), VD2 (including following data voltage VD2_R,
VD2_G, VD2_B) to multiplexer MUX.In addition, source electrode driver SD is also to according to control signal CTL, stopping output number
According to voltage VD1, VD2 to multiplexer MUX.
In one embodiment, multiplexer MUX is to according to multiplex signal SL1-SL3, selectivity conducting output
Another corresponding person in a corresponding person in pin P1 to data line DL1-DL6, and conducting output pin P2 to data line DL1-DL6,
Data voltage VD1, VD2 to be provided to the corresponding person in pixel circuit 106.
For example, referring concurrently to Fig. 2, output pin P1 output data voltage VD1_R (examples are penetrated in source electrode driver SD
The data voltage of corresponding red sub-pixel in this way) and it is (such as corresponding red through output pin P2 output data voltages VD2_R
The data voltage of sub-pixel) when, multiplexer MUX can provide data voltage VD1_R according to multiplex signal SL1
To data line DL1 and its pixel circuit of connection 106 (such as red sub-pixel circuit) and data voltage VD2_R is provided to
Data line DL4 and its pixel circuit of connection 106 (such as red sub-pixel circuit).
Then, in source electrode driver SD through output pin P1 output data voltages VD1_G (such as corresponding green sub-pixels
Data voltage) and through output pin P2 output data voltages VD2_G (such as data voltage of corresponding green sub-pixels)
When, data voltage VD1_G can be provided to data line DL5 and its company by multiplexer MUX according to multiplex signal SL2
Data voltage VD2_G is simultaneously provided to data line DL2 and its company by the pixel circuit 106 (be, for example, green sub-pixels circuit) that connects
The pixel circuit 106 (such as green sub-pixels circuit) connect.
Then, in source electrode driver SD through output pin P1 output data voltages VD1_B (such as corresponding blue subpixels
Data voltage) and through output pin P2 output data voltages VD2_B (such as data voltage of corresponding blue subpixels)
When, data voltage VD1_B can be provided to data line DL5 and its company by multiplexer MUX according to multiplex signal SL3
Data voltage VD2_B is simultaneously provided to data line DL2 and its connection by the pixel circuit 106 (such as blue subpixels circuit) that connects
Pixel circuit 106 (such as blue subpixels circuit).
Whereby, switch can be carried out by the pixel circuit 106 that grid signal G1, G2 is opened according to data voltage VD1, VD2
Display operation.
It should be noted that the connection type of above-mentioned multiplexer MUX is only to illustrate, the application is not limited thereto, other
The connection type of form is also among the application range.
In one embodiment, controller 100 to generate aforementioned control signals CTL, trigger signal XSTB and multiplexing
Signal SL1-SL3.Controller 100 using control signal CTL adjustment multiplex signal SL1-SL3 at the beginning of point (such as
One of rising edge and falling edge) and/or intermission point (such as the other of rising edge and falling edge), to lower
Noise caused by multiplex signal SL1-SL3.In addition, controller 100 also utilizes control signal CTL, to enable source electrode driver
SD correspondingly stops output data voltage VD1, VD2, to avoid because adjustment multiplex signal SL1-SL3 at the beginning of point
And/or intermission point causes the mistake output of data voltage VD1, VD2.
In one embodiment, controller 100 can receive the video signal from host, and aforementioned according to video signal generation
Control signal CTL, trigger signal XSTB and multiplex signal SL1-SL3.In one embodiment, controller 100 is corresponding to
Video signal generates the pulse of control signal CTL, so as to adjust multiplex signal SL1-SL3 in preset time point.It is real one
It applies in example, aforementioned preset time point can be determined according to the charging rate of pixel circuit 106.
In one embodiment, controller 100 can use sequence controller (timing controller) to realize, right the application
It is not limited.In one embodiment, the function of controller 100 can use programmable logic device (programmable therein
Logic device, PLD) and/or other hardware circuits realize that right the application is not limited.
To arrange in pairs or groups Fig. 1-Fig. 3 below, illustrate the detail of one operation example of the application, however the application is not with operations described below
Example is limited.
With reference to Fig. 3, in time point t0, grid signal G1 starts to export, to open opening for the first row pixel circuit 106
It closes.
In time point t1, trigger signal XSTB is in falling edge.At this point, source electrode driver SD is according to trigger signal XSTB
Falling edge, start penetrate output pin P1 output data voltage VD1_R to multiplexer MUX.At this point, controller 100 is opened
Beginning output multi-channel multiplexed signals SL1, that is, point at the beginning of time point t1 substantially multiplex signal SL1, and it is more at this time
Road multiplexed signals SL1 is in rising edge.
In time point t1 to time point t2, output pin is connected according to multiplex signal SL1 in multiplexer MUX
P1 and data line DL1, to enable data line DL1 receive the data voltage VD1_R from source electrode driver SD, to make the first row picture
One of respective data lines DL1 (pixel circuit 106 as being located at the first row, first row) receives data voltage in plain circuit 106
VD1_R。
In time point t2, control signal CTL is in rising edge.At this point, source electrode driver SD is according to control signal CTL's
Rising edge stops output data voltage VD1_R.In addition, controller 100 is more corresponding to the rising edge suspension output of control signal CTL
Road multiplexed signals SL1, that is, the intermission point of time point t2 substantially multiplex signal SL1, and multiplexing letter at this time
Number SL1 is in falling edge.In addition, rising edge of the controller 100 corresponding to control signal CTL, starts output multi-channel multiplexed signals
SL2, that is, point at the beginning of time point t2 substantially multiplex signal SL2, and multiplex signal SL2 is in upper at this time
Rise edge.
In time point t3, control signal CTL is in falling edge, and trigger signal XSTB is in rising edge.
In time point t4, trigger signal XSTB is in falling edge.At this point, source electrode driver SD is according to trigger signal XSTB
Falling edge, start output data voltage VD1_G to multiplexer MUX through output pin P1.
In time point t4 to time point t5, output pin is connected according to multiplex signal SL2 in multiplexer MUX
P1 and data line DL5, to enable data line DL5 receive the data voltage VD1_G from source electrode driver SD, to make the first row picture
One of respective data lines DL1 (pixel circuit 106 as being located at the 5th row, the first row) receives data voltage in plain circuit 106
VD1_G。
In time point t5, control signal CTL is in rising edge.At this point, source electrode driver SD is according to control signal CTL's
Rising edge stops output data voltage VD1_G.In addition, controller 100 is more corresponding to the rising edge suspension output of control signal CTL
Road multiplexed signals SL2, that is, the intermission point of time point t5 substantially multiplex signal SL2, and multiplexing letter at this time
Number SL2 is in falling edge.In addition, rising edge of the controller 100 corresponding to control signal CTL, starts output multi-channel multiplexed signals
SL3, that is, point at the beginning of time point t5 substantially multiplex signal SL3, and multiplex signal SL3 is in upper at this time
Rise edge.
In time point t6, trigger signal XSTB is in rising edge.
In time point t7, trigger signal XSTB is in falling edge.At this point, source electrode driver SD is according to trigger signal XSTB
Falling edge, start penetrate output pin P1 output data voltage VD1_B to multiplexer MUX.
In time point t7 to time point t8, output pin is connected according to multiplex signal SL3 in multiplexer MUX
P1 and data line DL3, to enable data line DL3 receive the data voltage VD1_B from source electrode driver SD, to make the first row picture
One of respective data lines DL3 (pixel circuit 106 as being located at third row, the first row) receives data voltage in plain circuit 106
VD1_B。
In time point t8, grid signal G1 stops output, and closes the switch of the first row pixel circuit 106.At this point, control
Signal CTL processed is in rising edge.At this point, source electrode driver SD stops output data voltage according to the rising edge of control signal CTL
VD1_B.In addition, controller 100 stops output multi-channel multiplexed signals SL3, that is, time corresponding to the rising edge of control signal CTL
The intermission point of point t8 substantially multiplex signal SL3, and multiplex signal SL3 is in falling edge at this time.
Via above-mentioned operation, point is approximately identical to multiplex signal at the beginning of can making multiplex signal SL2
The intermission point of SL1, and make to put at the beginning of multiplex signal SL3 and be approximately identical in multiplex signal SL2
Only time point, noise caused by make multiplex signal SL1-SL3 cancel each other out.
Further, since source electrode driver SD corresponding to control signal CTL stop output data voltage VD1_R, VD1_G,
VD1_B, even if so point is approximately identical to the intermission of multiplex signal SL1 at the beginning of multiplex signal SL2
Point is also not that data voltage VD1_R is made mistakenly to be provided to data line DL5.Similarly, even if multiplex signal SL3
Sart point in time is approximately identical to the intermission point of multiplex signal SL2, is also not to make data voltage VD1_G mistakenly
It is provided to data line DL3.
Though it should be noted that being illustrated by taking the relevant operation of source electrode driver SD output data voltages VD1 as an example above, so
And the relevant operation of data voltage VD2 is also roughly the same, therefore this will not be repeated here.
Additionally, it is to be noted that the polarity of above-mentioned signal G1, XSTB, CTL, SL1-SL3 can be become according to actual needs
Change, so the rising edge of above-mentioned signal, falling edge can also be exchanged according to actual conditions.For example, trigger signal XSTB, control letter
Number CTL can be reverse impulse, therefore in time point t3, trigger signal XSTB be in falling edge, and controls signal CTL and be in rising
Edge.So the application is not limited with above-mentioned operation example.
In one embodiment of the application, above-mentioned in the period partially or in whole of time point t2 to time point t4, and/or
In the period partially or in whole of time point t5 to time point t7, source electrode driver SD can make output pin P1, P2 be in high impedance
State.In some embodiments, output pin P1, P2 can be made to be connected to a big impedance in high impedance status, or
In suspension joint (floating) state.
In one embodiment of the application, above-mentioned in the period partially or in whole of time point t2 to time point t4, and/or
In the period partially or in whole of time point t5 to time point t7, source electrode driver SD can be such that output pin P1, P2 is grounded, with resetting
Voltage on data line DL2, DL3, DL5, DL6.
For example, in time point t2, source electrode driver SD can start to make output pin according to the rising edge of control signal CTL
P1, P2 are grounded, to stop output data voltage VD1_R, VD2_R.Also, in time point t3, source electrode driver SD can basis
The rising edge of trigger signal XSTB starts that output pin P1, P2 is made to be in high impedance status.
In different embodiments, in time point t2, source electrode driver SD can start according to the rising edge of control signal CTL
Output pin P1, P2 is set to be in high impedance status, to stop output data voltage VD1_R, VD2_R.Also, in time point t3
When, source electrode driver SD can start that output pin P1, P2 is made to be grounded according to the rising edge of trigger signal XSTB.
Fig. 4 is the schematic diagram for implementing the source electrode driver SD exemplified according to the application one.In one embodiment, source electrode drives
Dynamic device SD includes data register DR, latch unit LT, output circuit OT, output time controller OTC and switching circuit SW.
In one embodiment, data register DR is providing data voltage VD1, VD2 to latch unit LT.Output time control
For device OTC processed to correspond to trigger signal XSTB, control latch unit LT provides data voltage VD1, VD2 to output circuit OT.It is defeated
Go out circuit OT and provides data voltage VD1, VD2 to output pin P1, P2 via switching circuit SW.
In one embodiment, switching circuit SW can be selectively electrically connected with output pin P1, P2 according to control signal CTL
To ground.In one embodiment, switching circuit SW can be switched over according to trigger signal XSTB, to enable at output pin P1, P2
In high impedance status.
For example, referring concurrently to Fig. 5, in aforesaid time point t2, switching circuit SW can be according to the rising edge of control signal CTL
It switches over, to start to make output pin P1, P2 to be grounded.Also, in aforesaid time point t3, switching circuit SW can be according to triggering
The rising edge of signal XSTB switches over, so that output pin P1, P2 are initially located in high impedance status and (such as are expressed as high impedance
State HiZ).Then, in aforesaid time point t4, switching circuit SW can be switched over according to the falling edge of trigger signal XSTB,
To start to make output pin P1, P2 output data voltage VD1, VD2.
It should be noted that in some embodiments, switching circuit SW can be also integrated among output circuit OT, the application not with
Above-described embodiment is limited.
With reference to Fig. 6, in other embodiments, the output end of the connection switching circuit SW of output circuit OT also has place
In the ability of high impedance status HiZ.In these embodiments, output circuit OT can receive trigger signal XSTB, and determine according to this
Output or data voltage VD1, VD2 make its output in high impedance status HiZ.Switching circuit SW is to according to control letter
Number CTL and trigger signal XSTB is switched over, so that output pin P1, P2 ground connection, or make output pin P1, P2 output from defeated
Go out data voltage VD1, VD2 of circuit OT or the high impedance status HiZ of the output end from output circuit OT is presented.
For example, referring concurrently to Fig. 7, in aforesaid time point t2, switching circuit SW can be according to the rising edge of control signal CTL
It switches over, to start to make output pin P1, P2 to be grounded.In aforesaid time point t3, the output end of output circuit OT can basis
The rising edge of trigger signal XSTB is initially located in high impedance status HiZ.Also, switching circuit SW can be according to trigger signal XSTB's
Rising edge switches over, to start the high impedance status for making output pin P1, P2 that the output end from output circuit OT be presented
HiZ.In aforesaid time point t4, output circuit OT can start output data voltage according to the falling edge of trigger signal XSTB
VD1, VD2, to start to make switching circuit SW to export data voltage VD1, VD2 to output pin P1, P2.
With reference to Fig. 8, in other embodiments, switching circuit SW is independently of source electrode driver SD settings.At this
In a little embodiments, source electrode driver SD can receive trigger signal XSTB, and determine to make output pin P1, P2 that high impedance be presented according to this
State HiZ or output data voltage VD1, VD2.Switching circuit SW is to according to control signal CTL and trigger signal XSTB progress
Switching, so that the corresponding person ground connection in data line DL1-DL6, or so that the corresponding person in data line DL1-DL6 is received and come from source electrode
Driver SD data voltages VD1, VD2 receives the high impedance status HiZ from output pin P1, P2.Correlative detail can refer to
Above-mentioned paragraph, therefore this will not be repeated here.In addition, in different embodiments, switching circuit SW can also be switched between three kinds of states,
To be grounded, be presented high impedance status HiZ or output data voltage VD1, VD2 (such as implementation similar to corresponding Fig. 5
Example).
With reference to Fig. 9, in other embodiments, switching circuit SW may also set up in multiplexer MUX and data line
Between DL1-DL6.Switching circuit SW according to control signal CTL and trigger signal XSTB to switch over, so that data line
Corresponding person ground connection in DL1-DL6, or so that the corresponding person in data line DL1-DL6 is received and answered from source electrode driver SD and multichannel
With data voltage VD1, VD2 or high impedance status HiZ of the reception from output pin P1, P2 of device MUX.Correlative detail can refer to
Above-mentioned paragraph, therefore this will not be repeated here.Similarly, in different embodiments, switching circuit SW can also be cut between three kinds of states
It changes, to be grounded, be presented high impedance status HiZ or output data voltage VD1, VD2 (such as implementation similar to corresponding Fig. 5
Example).
Although the present invention is disclosed as above with embodiment, it is not limited to the present invention, any art technology
Personnel, without departing from the spirit and scope of the present invention, when various change and modification, therefore protection scope of the present invention can be made
It should be subject to appended claims range institute defender.
Claims (10)
1. a kind of display device, including：
One source driver, according to a trigger signal, sequentially to export one first data voltage and one second data voltage；
One multiplexer, to receive first data voltage and second data voltage, and according to one first multiplexing
Signal and one second multiplex signal sequentially export first data voltage and second data voltage to different data line；
And
One controller, to generate a control signal, with control an intermission point of first multiplex signal with this
The time point at the beginning of two multiplex signals is substantially identical to each other, and believes corresponding to the control to control the source electrode driver
Number stop export first data voltage.
2. display device as described in claim 1, the wherein source electrode driver stop exporting the time of first data voltage
Point is approximately identical to the intermission point of the first multiplex signal.
3. display device as described in claim 1, wherein stopping exporting first data voltage extremely in the source electrode driver
During few part, draw to export an output of first data voltage and second data voltage in the source electrode driver
Foot is grounded.
4. display device as described in claim 1, the wherein source electrode driver include：
One switching circuit, to according to the control signal, be selectively electrically connected in the source electrode driver to export this first
One output pin of data voltage and second data voltage is to a ground.
5. display device as claimed in claim 4, the wherein switching circuit be according to the trigger signal also to switch over, with
The output pin is enabled to be in a high impedance status.
6. display device as claimed in claim 4, the wherein switching circuit are carried out according to a first edge of the control signal
Switching, to be electrically connected the output pin to the ground.
7. display device as claimed in claim 4, the wherein switching circuit are also to according to one first side of the trigger signal
Edge switches over, and to enable the output pin be in a high impedance status, and the wherein switching circuit is according to the one of the trigger signal
Second edge switches over, to enable the output pin export second data voltage.
8. display device as described in claim 1, wherein the intermission point of first multiplex signal, this more than second
The time point that the sart point in time of road multiplexed signals and the source electrode driver stop exporting first data voltage is roughly the same
In the time point of a first edge of the control signal.
9. a kind of display device, including：
One source driver, according to a trigger signal, sequentially to export one first data voltage and one second data voltage；
One multiplexer, to receive first data voltage and second data voltage, and according to one first multiplexing
Signal and one second multiplex signal sequentially export first data voltage and second data voltage to one first data line
And one second data line；
One controller, to generate a control signal, with control first multiplex signal a falling edge time point with
The time point of one rising edge of second multiplex signal is substantially identical to each other, or controls the one of first multiplex signal
The time point of rising edge and the time point of a falling edge of second multiplex signal are substantially identical to each other；And
One switching circuit, to be switched over according to the control signal, with prevent first data voltage be provided to this second
Data line.
10. display device as claimed in claim 9, the wherein switching circuit be according to the control signal to switch over, with
First data line and second data line are selectively electrically connected with to a ground.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW107102731A TWI659404B (en) | 2018-01-25 | 2018-01-25 | Display device |
| TW107102731 | 2018-01-25 |
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| CN108597433A true CN108597433A (en) | 2018-09-28 |
| CN108597433B CN108597433B (en) | 2021-10-08 |
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| CN201810394138.2A Active CN108597433B (en) | 2018-01-25 | 2018-04-27 | Display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111243483A (en) * | 2019-07-25 | 2020-06-05 | 友达光电股份有限公司 | Display device and operation method thereof |
| US10782814B2 (en) | 2018-03-13 | 2020-09-22 | Au Optronics Corporation | Touch display panel |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| Publication number | Publication date |
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| TW201933311A (en) | 2019-08-16 |
| TWI659404B (en) | 2019-05-11 |
| CN108597433B (en) | 2021-10-08 |
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