CN101299322A - Control method for eliminating closedown ghost as well as display device and drive device - Google Patents
Control method for eliminating closedown ghost as well as display device and drive device Download PDFInfo
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- CN101299322A CN101299322A CN 200710102389 CN200710102389A CN101299322A CN 101299322 A CN101299322 A CN 101299322A CN 200710102389 CN200710102389 CN 200710102389 CN 200710102389 A CN200710102389 A CN 200710102389A CN 101299322 A CN101299322 A CN 101299322A
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Abstract
Provided is a control method for eliminating the shutdown ghost and a display device and a driving device using the same, wherein the display device includes a display panel, a source driver and a control device. The display panel includes a plurality of pixels, wherein the source driver is used for providing the pixel voltage to teh pixel, and the control device is used for receiving the control signal, and determining whether providing a first voltage to the pixel according to the control signal, and determining whether the source driver provides the pixel voltage to the pixel. When the system voltage of the display device is smaller than the scheduled voltage, the control device determines that the source driver stops providing the pixel voltage to the pixel and the control device provides the first voltage to the pixel.
Description
Technical field
The present invention relates to a kind of display device, particularly relate to a kind of display device and driving circuit that uses the control method that to eliminate power-off ghost shadow and use this method.
Background technology
Along with photoelectricity and development of semiconductor, driven the flourish of panel display.And in all multi-panel display devices, Thin Film Transistor-LCD (Thin Film Transistor LiquidCrystal Display with advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low electromagnetic interference (EMI), TFT-LCD), become the main flow in market recently.Because Thin Film Transistor-LCD is widely used in the electronic product closely bound up with life such as mobile computer, mobile phone and TV, thereby the improvement of image quality is always for continuing the target of pursuit.
Generally speaking, show that at unusual picture can rely on special driving method adds in case make.For instance, the ghost phenomena that is caused during before for fear of display panels in shutdown has been convenient to design in the gate drivers circuit of an overall height level function (all high function).This function is mainly when detecting the panel shutdown, produces controlling signal control gate driver output high level to all sweep traces.Therefore the just thin film transistor (TFT) of all pixels of openable panel or inferior pixel correspondence simultaneously to form the discharge that discharge path quickens electric charge in pixel or the inferior pixel capacitance, is eliminated the ghost that shutdown causes.
Fig. 1 shows the calcspar of the gate drivers of conventional liquid crystal.Please refer to Fig. 1, comprised shift register (shift register) 101, level shifter (level shifter) 102 and output buffer (output buffer) 103 in the gate drivers.Vertical direction frenquency signal V by the generation of frequency controller (not shown)
CLKControl the time of each grade shift register output state in the shift register 101, export the logic state of the corresponding sweep trace of On/Off sequentially one by one.And level shifter 102 is for transferring to the logic level of low-voltage required high open voltage of enough switch panel upper film transistors and the low voltage that closes in real time.Yet,, add that therefore output buffer 103 is to increase driving force if, may cause the driving force deficiency directly with the direct driven sweep line of the output of level shifter 102.
In addition, the OE signal is in order to the opening time of control TFT, and the XON signal is for detecting the controlling signal that the panel shutdown is produced, so that the lead-out terminal Y of gate drivers
1～Y
nAll the output high level is opened the online thin film transistor (TFT) of all panel scannings.Therefore, the XON signal is generally with voltage decline signal synchronous, that is can export the XON signal to gate drivers when when shutdown, system voltage was lower than certain particular value, quickens the charge discharge in all pixels in the panel or the inferior pixel capacitance.
Fig. 2 shows the calcspar of the source electrode driver of conventional liquid crystal.Please refer to Fig. 2, source electrode driver has comprised shift register 201, line latch (line latch) 202, level shifter 203, digital analog converter (digital to analog converter) 204, output buffer 205, data register 206 and signal receiver 207, wherein shift register 201, level shifter 203 and the function of output buffer 205 such as the explanation of Fig. 1 be not so given unnecessary details.
Signal receiver 207 receives digitized video signal data, and video signal data is stored in the data register 206.Horizontal direction frenquency signal H by the generation of time schedule controller (not shown)
CLKControl the time of each grade shift register output states in the shift register 201, will scan the video signal data that online all pixels will show one by one and store in the online latch (line latch) 202.And digital analog converter 204 is with the corresponding pixel voltage of digitized video signal data conversion, wherein the POL signal in every sweep trace time reversal once, make the output polarity of adjacent scanning lines opposite, and the CLK1 signal is the controlling signal that makes source electrode driver output.
In addition, the two ends of first switches set, 208 interior each switches connect the lead-out terminal X of source electrode driver respectively
1～X
nAnd the splicing ear Z that couples the panel data line
1～Z
n, wherein signal CON control first switches set 208 conducting whether, to the panel data line, so the CON signal can be CLK1 signal or the signal synchronous with the CLK1 signal with output pixel voltage.
As the explanation of above-mentioned gate drivers and source electrode driver, Fig. 3 shows the calcspar of traditional liquid crystal indicator.Wherein, the multiple source driver couples the data line of display panels 303, and a plurality of gate drivers couples the sweep trace of display panels 303.For example, source electrode driver 301a, 301b shown in Figure 3, the splicing ear 302 of 301c couple the data line of display panels 303, and the lead-out terminal 305 of gate drivers 304a, 304b couples the sweep trace of display panels 303.Time schedule controller 306 provides controlling signal CLK1 and POL to source electrode driver 301a, 301b, 301c.Utilize voltage-level detector 307 to detect side system voltage V
System, as system voltage V
SystemDuring less than certain particular value, provide the lead-out terminal 305 of XON signal control gate driver 304a, 304b all to export high level, make the online thin film transistor (TFT) of face display panels 303 scannings all open, quicken all pixels or the interior charge discharge of inferior pixel capacitance in the display panels 303.
Yet, in all thin film transistor (TFT) conductings (turn on), the output of source electrode driver still might be connected with data line, and the level of each output of source electrode driver also may be in state inequality (perhaps level), and causes display panels the non-uniform phenomenon of vertical bar line can occur when shutdown.Fig. 4 shows the sequential chart of source electrode driver and the relevant controlling signal of gate drivers.Please refer to Fig. 4, as system voltage V
SystemDuring less than certain particular value (being judged to be off-mode), the lead-out terminal Y of gate drivers
1～Y
n(as the explanation of Fig. 1) exports high level (shown in block 402) simultaneously.And because the controlling signal CLK1 and the controlling signal POL of the output of Controlling Source driver all are in unknown state 403 and 404 respectively, wherein controlling signal CLK1 (as the explanation of Fig. 2) also is the switching of control first switches set 208, therefore causes the splicing ear Z of source electrode driver
1～Z
nAlso be in unknown state 401.In other words, when online all thin film transistor (TFT)s of panel scanning were opened, the voltage difference of each bar data line on the panel just can make the charge discharge speed in pixel on the panel or the inferior pixel capacitance inconsistent, causes the uneven phenomenon of power-off ghost shadow.
Summary of the invention
The present invention proposes a kind ofly to be used in display device when shutdown and to eliminate the control method of ghost and the display device of using the method.This control method at first detects the system voltage of display device.When system voltage during less than predetermined voltage, just stop a plurality of pixels of output pixel voltage, and provide another voltage to these pixels to display device, avoiding the inconsistent ghost non-uniform phenomenon that is caused of the pixel capacitance velocity of discharge, and promote image quality.
The present invention proposes a kind of display device of eliminating power-off ghost shadow, comprises display panel, source electrode driver and control device.Display panel comprises a plurality of pixels.Source electrode driver is in order to provide pixel voltage to pixel.Whether control device is in order to receiving a controlling signal, and provide first voltage to pixel according to the controlling signal decision, and whether the determining source driver provides pixel voltage to pixel.When the system voltage of display device during less than predetermined voltage, control device Controlling Source driver stops to provide pixel voltage to pixel, and control device provides first voltage to pixel.
The display device of above-mentioned elimination power-off ghost shadow, control device comprises a plurality of handover modules, first connecting line and signal generating circuit in one embodiment.Each handover module comprises first lead-out terminal, second splicing ear, first splicing ear, first switch and second switch.The pixel voltage of first lead-out terminal reception sources driver output.First splicing ear couples pixel.Whether first switch determines conducting to the first lead-out terminal according to first controlling signal.Second switch couples first splicing ear, and whether determines conducting to the first switch or second splicing ear according to second controlling signal.First connecting line couples second splicing ear of handover module, and couples first voltage.Signal generating circuit receives this controlling signal, and produces first controlling signal and second controlling signal.When system voltage during less than predetermined voltage, first controlling signal is controlled the first not conducting of switch, and second controlling signal control second switch conducting to the second splicing ear.
The present invention proposes a kind of control method of eliminating power-off ghost shadow, is used to have the display device of source electrode driver and a plurality of pixels.At first detect the system voltage of this display device.When system voltage during less than predetermined voltage, the Controlling Source driver stops to provide pixel voltage to pixel, and provides first voltage to pixel.
The control method of above-mentioned elimination power-off ghost shadow, display device comprises a gate drivers in one embodiment, and the method comprises that also the control gate driver is opened the multi-strip scanning line when system voltage during less than predetermined voltage.
The present invention also is off-mode for when the system voltage that detects display device during less than first voltage, utilizes controlling signal control gate driver to open the multi-strip scanning line, makes the interior electric charge of pixel capacitance carry out discharging action.At the same time, utilize controlling signal Controlling Source driver to stop output pixel voltage to data line, and provide the pixel of a voltage level to online data, to avoid the online data voltage level difference of display device, cause pixel capacitance velocity of discharge difference and the uneven phenomenon of generation vertical bar line.The present invention proposes a kind of drive unit, is applicable to a display device.This driver comprises source electrode driver, in order to a plurality of pixels of a plurality of pixel voltages display panel to this display device to be provided, and control device, in order to receive a controlling signal, and whether provide one first voltage to these pixels according to controlling signal decision, and determine whether this source electrode driver provides these pixel voltages to above-mentioned pixel, wherein when a system voltage of display device during less than a predetermined voltage, control device determining source driver stops to provide pixel voltage to pixel, and control device provides one first voltage to pixel, to avoid the online data voltage level difference of display device, cause pixel capacitance velocity of discharge difference and the uneven phenomenon of generation vertical bar line.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment of the present invention cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the calcspar of the gate drivers of conventional liquid crystal.
Fig. 2 shows the calcspar of the source electrode driver of conventional liquid crystal.
Fig. 3 shows the calcspar of traditional liquid crystal indicator.
Fig. 4 shows the sequential chart of source electrode driver and the relevant controlling signal of gate drivers.
Fig. 5 A shows the calcspar of the display device of a preferred embodiment of the present invention.
Fig. 5 B shows a kind of calcspar of implementing circuit of the source electrode driver of embodiment of the invention Fig. 5 A.
Fig. 5 C shows a kind of calcspar of implementing circuit of the gate drivers of embodiment of the invention Fig. 5 A.
Fig. 5 D shows the source electrode driver of a preferred embodiment of the present invention and the sequential chart of the relevant controlling signal of gate drivers.
Fig. 6 A shows the calcspar of the display device of a preferred embodiment of the present invention.
Fig. 6 B shows a kind of calcspar of implementing circuit of the source electrode driver of embodiment Fig. 6 A.
Fig. 6 C shows a kind of enforcement circuit diagram of the control circuit of embodiment of the invention Fig. 6 B.
Fig. 7 A shows the calcspar of the display device of a preferred embodiment of the present invention.
Fig. 7 B shows a kind of calcspar of implementing circuit of the gate drivers of embodiment of the invention Fig. 7 A.
Fig. 8 A shows the calcspar of the display device of a preferred embodiment of the present invention.
Fig. 8 B shows a kind of calcspar of implementing circuit of the time schedule controller of embodiment of the invention Fig. 8 A.
Fig. 9 A shows the calcspar of the display device of a preferred embodiment of the present invention.
Fig. 9 B shows a kind of calcspar of implementing circuit of the source electrode driver inner control circuit of embodiment of the invention Fig. 9 A.
Figure 10 shows the method flow diagram of the elimination power-off ghost shadow of a preferred embodiment of the present invention.
The reference numeral explanation
OE, XON, V
CLK, H
CLK, CLK1, POL, CON, CON1, CON2: controlling signal
Y
1～Y
n, 305: the lead-out terminal of gate drivers
X
1～X
n: the lead-out terminal of source electrode driver
Z
1～Z
n, 302: the splicing ear of source electrode driver
V
System: system voltage
S1, S2: switch
C1, C2, C3, O1, W
1～W
n: terminal
P1, N1: transistor
I1, I2: phase inverter
101,201,507,516,607,716: shift register
102,203,509,517,609,717: level shifter
103,205,511,518,611,718: output buffer
202,508,608: the line latch
204,510,610: digital analog converter
206,513,613: data register
207,512,612: signal receiver
208: the first switches set
301a, 301b, 301c, 501a, 501b, 501c, 601a, 601b, 601c, 701a, 701b, 701c, 801a, 801b, 801c, 901a, 901b, 901c: source electrode driver
303,503,603,703,803: display panel
304a, 304b, 304c, 504a, 504b, 504c, 604a, 604b, 604c, 704a, 704b, 704c, 804a, 804b, 804c: gate drivers
306,506,606,706,806: time schedule controller
307,505,605: voltage-level detector
502,602,702,802,902: the first connecting lines
514,614,914a, 914b, 914c: signal generating circuit
515a, 515b, 515c, 615a, 615b, 615c: handover module
616: detecting unit
705,805: voltage detecting circuit
The 807:LVDS receiver
808: data latches
809: data processor
The 810:PSDS forwarder
811: grid controlling signal generator
812: source electrode controlling signal generator
917: the second connecting lines
V
1～V
n: data line
S1001～S1003: each step of the method for the power-off ghost shadow of a preferred embodiment of the present invention
Embodiment
The present invention proposes a kind of control method of eliminating ghost when display device is shut down that is used in, and this control method can be used in time schedule controller, driving method or the drive unit etc. of display device.This control method is for detecting the system voltage of display device, when system voltage during, stop output pixel voltage to pixel, and provide another voltage to pixel less than a predetermined voltage, avoiding the inconsistent ghost non-uniform phenomenon that is caused of the pixel capacitance velocity of discharge, and promote image quality.
Fig. 5 A shows the calcspar of the display device of one embodiment of the invention.Please refer to Fig. 5 A, display device has comprised source electrode driver 501a, 501b, 501c (3 source electrode drivers only being shown at this), gate drivers 504a, 504b, 504c (3 gate drivers only being shown at this), display panel 503, voltage-level detector 505, time schedule controller 506 and control device (not shown).Wherein display panel 503 comprises a plurality of pixels.
The frequency control signal that gate drivers 504a, 504b, 504c are provided according to time schedule controller 506 is opened the sweep trace of display panel 503 in regular turn.The frequency control signal that source electrode driver 501a, 501b, 501c are provided according to time schedule controller 506 provides pixel voltage to these pixels by data line.Voltage-level detector 505 is in order to detect the system voltage V of display device
SystemAs system voltage V
SystemDuring less than predetermined voltage, control device (not shown) just Controlling Source driver 501a, 501b, 501c stops to provide pixel voltage to data line, and provide one first voltage to data line, to avoid the inconsistent ghost non-uniform phenomenon that is caused of the pixel capacitance velocity of discharge.Below be described in detail the function of each square.At this hypothesis control device for being applied in the drive unit, its be coupled in source electrode driver and pixel between.Fig. 5 B shows source electrode driver 501a, the 501b of embodiment of the invention Fig. 5 A, a kind of calcspar (following just with source electrode driver 501a explanation) of implementing circuit of 501c.Please refer to Fig. 5 A and Fig. 5 B, the running of the shift register 507 that source electrode driver 501 is comprised, line latch 508, level shifter 509, digital simulation parallel operation 510, output buffer 511, signal receiver 512 and data register 513 can be with reference to the embodiment of figure 2 explanations, so do not given unnecessary details.
And control device has comprised handover module 515a, 515b, 515c (at this 3 groups of handover modules only are shown, and illustrate with handover module 515a), signal generating circuit 514 and first connecting line 502.The first lead-out terminal O1, the first splicing ear C1, the second splicing ear C2, first switch S 1 and second switch S2 have been comprised in the handover module 515a.The pixel voltage of first lead-out terminal O1 reception sources driver 501a output, and the first splicing ear C1 couples pixel.Whether first switch S 1 determines conducting to the first lead-out terminal O1 according to the first controlling signal CON1, and second switch couples the first splicing ear C1, and according to second controlling signal CON2 decision conducting to the first switch S 1 or the second splicing ear C2 wherein one.First connecting line 502 couples together for the second splicing ear C2 with handover module 515a, 515b, 515c.
Fig. 5 C shows gate drivers 504a, the 504b of embodiment of the invention Fig. 5 A, a kind of calcspar of implementing circuit of 504c, below just with gate drivers 504a explanation.Please refer to Fig. 5 A and Fig. 5 C, the running of the included shift register 516 of gate drivers 504a, level shifter 517, output buffer 518 can be with reference to the embodiment of figure 1 explanation, so do not given unnecessary details.And gate drivers 504a comprises the second lead-out terminal W
1～W
n, and these second lead-out terminals W
1～W
nCouple the sweep trace of display panel 503 respectively.
Fig. 5 D shows the source electrode driver of a preferred embodiment of the present invention and the sequential chart of the relevant controlling signal of gate drivers.Please refer to Fig. 5 C and Fig. 5 D, as voltage-level detector 505 detection system voltage V
SystemLess than predetermined voltage, that is when detecting display device and being off-mode, voltage-level detector 505 just produces controlling signal XON and comes control gate driver 504a, 504b, 504c to open the multi-strip scanning line on the display panel 503.In other words, i.e. the second lead-out terminal W
1～W
nOutput high level (as block 522) with the thin film transistor (TFT) on the conducting display panel 503, and provides discharge path to make display panel 503 pixels or the interior charge discharge of inferior pixel capacitance.
Please refer to Fig. 5 B and Fig. 5 D, at the same time, though controlling signal CLK1 and controlling signal POL all are in unknown state 520,521 respectively, but the signal generating circuit 514 in the source electrode driver 501a produces the first controlling signal CON1 and the second controlling signal CON2 when receiving controlling signal XON.The first controlling signal CON1 controls first switch S 1 and cuts off and being connected of the first lead-out terminal O1, and being connected of second controlling signal CON2 control second switch S2 cut-out and first switch S 1, and conducting to the second splicing ear C2.
In the present embodiment, first connecting line 502 couples the first voltage V
COMTherefore when shutdown, can provide the first voltage V
COMTo display panel 503 data line V
1～V
n, make the voltage of each bar online data identical, use the phenomenon of having avoided the inconsistent power-off ghost shadow inequality that causes of capacitor discharge speed.And the first voltage V
COMCan be the common electrode voltage that pixel couples jointly, therefore when shutdown, the electrode at pixel capacitance two ends is respectively first voltage and common electrode voltage.In other words, the electric charge that stores in the pixel capacitance is minimum, the raising that the velocity of discharge is also natural.
Fig. 6 A shows the calcspar of the display device of a preferred embodiment of the present invention, Fig. 6 B shows source electrode driver 601a, the 601b of embodiment Fig. 6 A, a kind of calcspar (at this 3 source electrode drivers only are shown, and illustrate with source electrode driver 601a) of implementing circuit of 601c.Please refer to Fig. 5 A, Fig. 5 B, Fig. 6 A and Fig. 6 B, embodiment Fig. 6 A, Fig. 6 B and embodiment Fig. 5 A, Fig. 5 B difference are source electrode driver 601a receiving system voltage V
System, and by the 614 detection system voltage V of the signal generating circuit in the source electrode driver 601a
System
Fig. 6 C shows a kind of enforcement circuit diagram of the signal generating circuit 614 of embodiment of the invention Fig. 6 B.Please refer to Fig. 6 C, signal generating circuit 614 has comprised detecting unit 616, N transistor npn npn N1, P transistor npn npn P1, the first phase inverter I1 and the second phase inverter I2.Detecting unit 616 detection system voltage V
System, when detecting unit 616 detects system voltage V
SystemExport an activation signal during less than predetermined voltage, make transistor N1 conducting, and export the first controlling signal CON1 and the second controlling signal CON2 by first and second phase inverter I1～I2.
Because first connecting line 602 couples the second splicing ear C2 of all handover modules in source electrode driver 601a, 601b, the 601c, and couples the first voltage V
COMTherefore when the display device shutdown, and when making all sweep traces be opening, the first controlling signal CON1 controls first switch S 1 and cuts off and being connected of the first lead-out terminal O1, and second controlling signal CON2 control second switch S2 conducting to the second splicing ear, so that the first voltage V to be provided
COMTo data line, the ghost phenomena of avoiding pixel or inferior pixel capacitance velocity of discharge difference to be caused.And other circuit operation mode is as implementing the explanation of illustration 5A, Fig. 5 B, so do not given unnecessary details.
Fig. 7 A shows the calcspar of the display device of a preferred embodiment of the present invention.Please refer to Fig. 7 A, this display device has comprised source electrode driver 701a, 701b, 701c (3 source electrode drivers only being shown at this), gate drivers 704a, 704b, 704c (3 gate drivers only being shown at this), time schedule controller 706 and display panel 703.
Source electrode driver 701a, the 701b of present embodiment, 701c utilize the source electrode driver of embodiment Fig. 6 B to implement.Fig. 7 B shows gate drivers 704a, the 704b of embodiment of the invention Fig. 7 A, a kind of calcspar of implementing circuit of 704c, below with gate drivers 704a explanation.Please refer to Fig. 7 A and Fig. 7 B, the running of the shift register 716 that gate drivers 704a is comprised, level shifter 717 and output buffer 718 can be with reference to the embodiment of figure 1 explanation.
In addition, gate drivers 704a comprises the second lead-out terminal W
1～W
nWith voltage detecting circuit 705.The second lead-out terminal W
1～W
nCouple the sweep trace of display panel 703 respectively, and voltage detecting circuit 705 is in order to detection system voltage V
System, and work as system voltage less than V
SystemDuring predetermined voltage, produce controlling signal XON, make the second lead-out terminal W
1～W
nAll export high level, to open all sweep traces on the display panel 703.
Fig. 8 A shows the calcspar of the display device of a preferred embodiment of the present invention.Please refer to Fig. 8 A, this display device comprises source electrode driver 801a, 801b, 801c (3 source electrode drivers only being shown at this), gate drivers 804a, 804b, 804c (3 gate drivers only being shown at this), display panel 803, time schedule controller 806.Source electrode driver 801a, the 801b of present embodiment, 801c utilize the source electrode driver of embodiment Fig. 5 B to implement, and gate drivers 804a, 804b, 804c utilize the gate drivers of embodiment Fig. 5 C to implement.In the present embodiment, time schedule controller 806 not only provides the display device running required frequency control signal, also can be in order to detection system voltage V
System
Fig. 8 B shows a kind of calcspar of implementing circuit of the time schedule controller 806 of embodiment of the invention Fig. 8 A.Please refer to Fig. 8 B, the LVDS that time schedule controller 806 is comprised (low voltagedifferential signal) receiver 807, data latches 808, data processor 809, RSDS (reduced swing differential signal) forwarder 810, grid controlling signal generator 811, source electrode controlling signal generator 812 are known well by those skilled in the art, so do not given unnecessary details.In addition, time schedule controller 806 has comprised voltage detecting circuit 805.Voltage detecting circuit 805 detection system voltage V
System, and as system voltage V
SystemDuring less than predetermined voltage, produce controlling signal XON to source electrode driver 801a, 801b, 801c and gate drivers 804a, 804b, 804c.
In addition, in embodiment of the invention Fig. 6 A and Fig. 7 A, each signal generating circuit detection system voltage V in the multiple source driver
System, and the time of first controlling signal and second controlling signal of sending may be inconsistent, thereby the uneven problem of picture may cause shutdown the time.Fig. 9 A shows the calcspar of the display device of a preferred embodiment of the present invention, and Fig. 9 B shows a kind of calcspar of implementing circuit of the interior signal generating circuit of source electrode driver of embodiment of the invention Fig. 9 A.Please refer to Fig. 9 A and Fig. 9 B, in the present embodiment, have signal generating circuit 914a, 914b, 914c (only illustrating) in source electrode driver 901a, 901b, the 901c respectively with 3 source electrode drivers at this.Utilize second connecting line 917 to connect the 3rd splicing ear C3 of signal generating circuit 914a, 914b, 914c, use that multiple source driver 901a, 901b, 901c are connected.Wherein first connecting line 902 is for coupling the second splicing ear C2 of all handover modules in source electrode driver 901a, 901b, the 901c.
And the purpose of present embodiment is to work as system voltage V
SystemDuring less than predetermined voltage, (for example: signal generating circuit 914a) interior detecting unit 916a output enable signal is drawn high A point current potential to the one signal generating circuit.When the pairing transistor N1 of single source electrode driver 914a conducting, the 3rd splicing ear C3 that is not sufficient to the multiple source driver is connected drags down, must in all source electrode drivers, draw high by the A point current potential of corresponding signal generating circuit, just be enough to the 3rd splicing ear C3 that the multiple source driver connects is dragged down.
Thus, the first controlling signal CON1 and the second controlling signal CON2 that just can reach in all multiple source drivers transmit simultaneously, detection system voltage V between solution multiple source driver
System, and send inconsistent problem of controlling signal time, use and improve the picture non-uniform phenomenon (block mura) that shutdown may occur.Remaining circuit operation as implement the explanation of illustration 7A, 7B, thus do not given unnecessary details, and embodiment of the invention Fig. 6 A, Fig. 6 B, Fig. 7 A, Fig. 7 B can also connect the multiple source driver according to the operation of present embodiment (Fig. 9 A, Fig. 9 B).
In sum, by the narration of top several embodiment, the method flow below this can reduce.Figure 10 shows the process flow diagram of control method of the elimination power-off ghost shadow of a preferred embodiment of the present invention.Please refer to Figure 10, at first, detect the system voltage (step S1001) of display device.When system voltage during less than predetermined voltage, the control gate driver is opened the multi-strip scanning line of display device simultaneously, to provide discharge path by the charge discharge (step S1002) in pixel on the display panel or the inferior pixel capacitance.At the same time, the Controlling Source driver stops output pixel voltage to pixel, and provides first voltage to pixel (step S1003), uses and avoids the inconsistent power-off ghost shadow phenomenon that causes of capacitor discharge speed.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (24)
1. display device of eliminating power-off ghost shadow comprises:
One display panel comprises a plurality of pixels;
The one source pole driver is in order to provide a plurality of pixel voltages to described pixel; And
Whether one control device in order to receiving a controlling signal, and provides one first voltage to described pixel according to this controlling signal decision, and determines whether this source electrode driver provides described pixel voltage to described pixel, wherein,
When a system voltage of this display device during less than a predetermined voltage, this control device determines this source electrode driver to stop to provide described pixel voltage to described pixel, and this control device provides one first voltage to described pixel.
2. the display device of elimination power-off ghost shadow as claimed in claim 1, wherein this control device comprises:
A plurality of handover modules, and each described handover module comprises:
One first lead-out terminal receives each described pixel voltage that this source electrode driver is exported;
One first splicing ear couples each described pixel;
One second splicing ear;
One first switch determines according to one first controlling signal whether conducting is to this first lead-out terminal; And
One second switch couples this first splicing ear, and determines according to one second controlling signal whether conducting is to this first switch or this second splicing ear;
One first connecting line couples this second splicing ear of described handover module, and couples this first voltage; And
One signal generating circuit receives this controlling signal, and produces this first controlling signal and this second controlling signal;
Wherein, when this system voltage during less than this predetermined voltage, this first controlling signal is controlled this not conducting of first switch, and this second controlling signal is controlled this second switch conducting to this second splicing ear.
3. display device as claimed in claim 2, wherein this signal generating circuit comprises:
One detecting unit in order to detecting this system voltage, and when this system voltage during less than this predetermined voltage, is exported an activation signal;
One P transistor npn npn, its grid couples an earthing potential, and its first source/drain electrode couples a power supply potential;
One N transistor npn npn, its grid receives this enable signal, and its first source/drain electrode couples second source/drain electrode of this P transistor npn npn, and its second source/drain electrode couples this earthing potential;
One first phase inverter, its input end couple first source/drain electrode of this N transistor npn npn, and its output terminal is exported this first controlling signal; And
One second phase inverter, its input end couple first source/drain electrode of this N transistor npn npn, and its output terminal is exported this second controlling signal.
4. display device as claimed in claim 3, wherein this signal generating circuit also comprises:
One the 3rd splicing ear couples first source/drain electrode of this N transistor npn npn.
5. display device as claimed in claim 4, wherein this control device also comprises:
One second connecting line couples the 3rd splicing ear.
6. the display device of elimination power-off ghost shadow as claimed in claim 1, wherein this controlling signal is that an external voltage detection device detects this system voltage less than this predetermined voltage produced.
7. the display device of elimination power-off ghost shadow as claimed in claim 1, wherein this controlling signal is this system voltage.
8. display device as claimed in claim 1 also comprises:
One voltage-level detector in order to detecting this system voltage, and produces this controlling signal.
9. display device as claimed in claim 1 also comprises:
One gate drivers receives this controlling signal, and whether opens the multi-strip scanning line according to this controlling signal decision;
Wherein, when this system voltage less than this predetermined voltage, this gate drivers is opened described sweep trace.
10. display device as claimed in claim 9, wherein this gate drivers also comprises:
One voltage detecting circuit in order to detecting this system voltage, and produces this controlling signal.
11. display device as claimed in claim 1 also comprises:
Time schedule controller, in order to produce the required a plurality of frequency control signals of this display device, this time schedule controller comprises:
One voltage detecting circuit in order to detecting this system voltage, and produces this controlling signal.
12. a control method of eliminating power-off ghost shadow is used to have a display device of one source pole driver and a plurality of pixels, the method comprises:
Detect a system voltage of this display device; And
When this system voltage during, control this source electrode driver and stop to provide a plurality of pixel voltages, and provide one first voltage to described pixel to described pixel less than a predetermined voltage.
13. the control method of elimination power-off ghost shadow as claimed in claim 12, wherein this display device comprises a gate drivers, and the method also comprises:
When this system voltage during, control this gate drivers and open the multi-strip scanning line less than this predetermined voltage.
14. a drive unit is applicable to a display device, this driver comprises:
The one source pole driver is in order to provide a plurality of pixels of a plurality of pixel voltages display panel to this display device; And
Whether one control device in order to receiving a controlling signal, and provides one first voltage to described pixel according to this controlling signal decision, and determines whether this source electrode driver provides described pixel voltage to described pixel, wherein,
When a system voltage of this display device during less than a predetermined voltage, this control device determines this source electrode driver to stop to provide described pixel voltage to described pixel, and this control device provides one first voltage to described pixel.
15. drive unit as claimed in claim 14, wherein this control device comprises:
A plurality of handover modules, and each described handover module comprises:
One first lead-out terminal receives each described pixel voltage that this source electrode driver is exported;
One first splicing ear couples each described pixel;
One second splicing ear;
One first switch determines according to one first controlling signal whether conducting is to this first lead-out terminal; And
One second switch couples this first splicing ear, and determines according to one second controlling signal whether conducting is to this first switch or this second splicing ear;
One first connecting line couples this second splicing ear of described handover module, and couples this first voltage; And
One signal generating circuit receives this controlling signal, and produces this first controlling signal and this second controlling signal;
Wherein, when this system voltage during less than this predetermined voltage, this first controlling signal is controlled this not conducting of first switch, and this second controlling signal is controlled this second switch conducting to this second splicing ear.
16. drive unit as claimed in claim 15, wherein this signal generating circuit comprises:
One detecting unit in order to detecting this system voltage, and when this system voltage during less than this predetermined voltage, is exported an activation signal;
One P transistor npn npn, its grid couples an earthing potential, and its first source/drain electrode couples a power supply potential;
One N transistor npn npn, its grid receives this enable signal, and its first source/drain electrode couples second source/drain electrode of this P transistor npn npn, and its second source/drain electrode couples this earthing potential;
One first phase inverter, its input end couple first source/drain electrode of this N transistor npn npn, and its output terminal is exported this first controlling signal; And
One second phase inverter, its input end couple first source/drain electrode of this N transistor npn npn, and its output terminal is exported this second controlling signal.
17. drive unit as claimed in claim 16, wherein this signal generating circuit also comprises:
One the 3rd splicing ear couples first source/drain electrode of this N transistor npn npn.
18. drive unit as claimed in claim 17, wherein this control device also comprises:
One second connecting line couples the 3rd splicing ear.
19. drive unit as claimed in claim 14, wherein this controlling signal detects this system voltage by an external voltage detection device and is produced less than this predetermined voltage.
20. drive unit as claimed in claim 14, wherein this controlling signal is this system voltage.
21. drive unit as claimed in claim 14 also comprises:
One voltage-level detector in order to detecting this system voltage, and produces this controlling signal.
22. drive unit as claimed in claim 14 also comprises:
One gate drivers receives this controlling signal, and whether opens the multi-strip scanning line according to this controlling signal decision;
Wherein, when this system voltage less than this predetermined voltage, this gate drivers is opened described sweep trace.
23. drive unit as claimed in claim 14, wherein this gate drivers also comprises:
One voltage detecting circuit in order to detecting this system voltage, and produces this controlling signal.
24. drive unit as claimed in claim 14 also comprises:
Time schedule controller, in order to produce the required a plurality of frequency control signals of this display device, this time schedule controller comprises:
One voltage detecting circuit in order to detecting this system voltage, and produces this controlling signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101023890A CN101299322B (en) | 2007-04-30 | 2007-04-30 | Display device for eliminating closedown ghost and drive device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101023890A CN101299322B (en) | 2007-04-30 | 2007-04-30 | Display device for eliminating closedown ghost and drive device |
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| CN101299322A true CN101299322A (en) | 2008-11-05 |
| CN101299322B CN101299322B (en) | 2011-12-07 |
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|---|---|---|---|
| CN2007101023890A Expired - Fee Related CN101299322B (en) | 2007-04-30 | 2007-04-30 | Display device for eliminating closedown ghost and drive device |
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