CN108550683A - A kind of method for integrating monolithic of high electron mobility transistor and light emitting diode with vertical structure - Google Patents
A kind of method for integrating monolithic of high electron mobility transistor and light emitting diode with vertical structure Download PDFInfo
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H—ELECTRICITY
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Abstract
The invention discloses the method for integrating monolithic of a kind of high electron mobility transistor and light emitting diode with vertical structure.After MOCVD epitaxy grows full structure LED, continue growth in situ HEMT heterojunction structures, obtains integrated epitaxial chip.Then the P electrode of the drain electrode of HEMT and LED are connected by way of metal interconnection after constituency etches, retransfers substrate, realize vertical LED structure.The source of HEMT, gate electrode structure are drawn finally by the method for trepanning etching, and prepares the N electrode structure of LED, the final single-chip integration for realizing HEMT and vertical structure LED.The integrated unit can not only realize the voltage control of high-power vertical structure LED, and GaN power devices high frequency, high-power advantage can be given full play to, it is advantageously implemented being miniaturized in integrated circuit, low cost, efficient intelligent lighting, intelligent display and visible light communication system.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of high electron mobility transistor and vertical structure light-emitting
The method for integrating monolithic of diode.
Background technology
Compared to conventional incandescent and fluorescent lighting, InGaN/GaN multiple quantum well light emitting diodes (LEDs) have more
High luminous efficiency, longer service life and energy-saving and environment-friendly advantage.A series of this excellent performance makes LED in intelligent photograph
There is great application prospect in bright, intelligent display system.In addition, silicon substrate vertical structure LED is compared to traditional process for sapphire-based cross
There is current distribution, more high power density and better thermal diffusivity evenly to structure LED, become high-power, high performance lED
Mainstay.But chip-scale LED prepared by different process is current control unit, single operating mode can not
Meet current intelligent lighting, intelligent display system.Especially in visible light communication field, have multi-functional, multimode voltage-controlled
LED array is the necessary condition for realizing efficient communication.In order to enable LED to be matched with conventional power integrated circuit (ICs), spirit is realized
Driving design living realizes that the control of LEDs voltages is a kind of effective and necessary processing route.
Integrated in component-level is the important way for realizing voltage-controlled device.There are two types of current general integration modes, and one
Kind is heterogeneous integrated in package level, and another kind is the single-chip integration in chip level.GaN photoelectrons and electronic device
Single-chip integration can effectively reduce the complexity of encapsulation, reduce parasitic element, be conducive to realize small size, the intelligence of low cost
Lighting system.The features such as GaN base device is due to its low on-resistance, low capacitance and high working frequency, makes it have excellent device
Part performance has potential application in terms of power amplifier, switched-mode power supply.
In order to give full play to LEDs illuminate advantage, also gather GaN base power device device advantage, realize voltage-controlled LEDs with
Integrated circuit is flexibly matched with, and promotes the micromation of GaN base power device and LEDs are integrated to have important industrial significance.Common
Epitaxial substrate also provides identical material platform for single-chip integration simultaneously.
Currently, the technique that GaN HEMT reported in the literature and LEDs is integrated generally comprises three kinds.One, selective area epitaxial layer moves
Except (SER), i.e., HEMT hetero-junctions is grown after the full structure epitaxial layers of LED, LED is exposed by the method that constituency etches, then
Carry out integrated technique.This method and process is simple, but etching technics control difficulty is big, and plasma damages chip strong, device
Performance is low.Two, selective area growth (SAG) is etched after having grown HEMT hetero-junctions by constituency, and the connection of LED and HEMT are obtained
Then area grows the full structures of LED by the method for secondary epitaxy, finally carries out integrated technique.This method and process is complicated, finished product
Rate is low, and diauxic growth makes cost obviously rise.The device that two detach is passed through metal bonding by three, back bonding (FCB)
Method integration get up.This method is high to technological requirement, needs to shift substrate and aligning equipment, production capacity are low.These methods
Although the single-chip integration of HEMT and LED may be implemented, they have the shortcomings that one it is common, i.e., can only realize HEMT device
It is integrated with transversary LED.And a big advantage of silicon substrate LED is high heat conduction, is suitble to prepare high-power thin-film LED.Mesh
Before, the industrialization of high-power vertical structure LED, but by vertical structure LED and GaN power device single-chip integrations, realize big
Power voltage control illuminates system, promotes intelligent lighting, the high efficiency of intelligent display and micromation, is still the one of academia and industrial quarters
Big challenge.
Invention content
The purpose of the present invention is to provide the monolithics of a kind of high electron mobility transistor and light emitting diode with vertical structure
Integrated approach realizes the high efficiency of intelligent illuminating system while pushing the miniaturization of intelligent lighting chip.
The purpose of the present invention is achieved through the following technical solutions.
A kind of method for integrating monolithic of high electron mobility transistor and light emitting diode with vertical structure, including following step
Suddenly：
(1) MOCVD technologies are utilized, on a si substrate the full structures of epitaxial growth LED, it is heterogeneous continues epitaxial growth HEMT in situ
Junction structure obtains integrated epitaxial chip structure；
(2) high temperature is carried out in specified area deposition HEMT device source, drain metal by photoetching, electron beam evaporation
Annealing obtains HEMT device source, drain electrode；
(3) chip in the source, drain electrode that prepare to step (2) carries out photoetching, ICP dry etchings, exposes LED region
P-GaN layer, and carry out magnesium-doped ion-activated annealing；
(4) HEMT marked off to step (3), LED region chip carry out again photoetching, ICP dry etchings by source, leakage
Electrode zone carries out device isolation with hetero-junctions；
(5) it utilizes source after step (4) isolation of photoetching, electron beam evaporation, prepare schottky gate electrode between drain electrode,
HEMT device is completed to make；
(6) chip surface obtained by step (5) grows SiO using the method for PECVD2Passivation layer reaches to hetero-junctions table
The purpose of face passivation protection；
(7) chip after being passivated to step (6) carries out photoetching, ICP dry etchings, exposes the source of HEMT, leakage, grid electricity
Pole, and electron beam evaporation extraction electrode is used, it then proceedes to deposit SiO using PECVD2Passivation layer, to reach to source, drain electrode
Etch the purpose of protection；
(8) photoetching, BOE wet etchings are carried out to the LED region of chip obtained by step (7), forms electricity corresponding with N electrode
Flow barrier (CBL) figure, while exposing LED region and part HEMT device source electrode region；
(9) P electrode of LED is prepared on the chip that step (8) p-GaN has CBL figures, and is made annealing treatment, by
It is connect in HEMT source electrodes, which is also the source electrode of HEMT simultaneously；
(10) step (9) is prepared to the Si bases chip of p-electrode and is bonded silicon substrate by way of metal bonding and is bonded,
Then extension silicon substrate is removed by the method for mechanical grinding and chemical attack, achievees the purpose that substrate shifts；
(11) roughening treatment is carried out to the n-GaN of step (10) substrate transfer rear surface exposure, increases LED light extractions to reach
Purpose, to gained chip carry out photoetching, ICP etching processings, grid, the drain electrode of HEMT device are exposed, using the side of PECVD
Method grows SiO2, protection is passivated to the GaN material side wall after ICP etchings, then repeats photoetching, ICP etch steps,
Exposure grid, drain electrode；
(12) HEMT structure grid, leakage extraction electrode and LED structure N electricity are deposited by the way of photoetching, electron beam evaporation
Pole, and make annealing treatment.
Preferably, the full structures of step (1) LED include 1~2 μm of AlN/GaN buffer layers successively, 1.5~2.5 μm
N-GaN layers, the multiple quantum well layer of 100~200nm and the p-GaN layer of 150~250nm；The HEMT heterojunction structures wrap successively
The i-GaN buffer layers of 100~200nm are included, the AlGaN of 40~80nm carries on the back barrier layer, the i-GaN channel layers of 60~120nm and 20
The AlGaN potential barrier of~25nm；Al groups are divided into 10%~20% in AlGaN back of the body barrier layer, Al in the AlGaN potential barrier
Group is divided into 20%~25%.
Preferably, the i- of 50~150nm is grown between step (1) the HEMT hetero-junctions channel layer and the full structures of LED
The AlGaN of GaN buffer layers and 40~80nm carry on the back barrier layer；Al groups are divided into 10%~20% in the AlGaN back ofs the body barrier layer.
Preferably, step (3) the magnesium-doped ion-activated annealing temperature be 600~700 DEG C, the time be 1~
2min。
Preferably, step (6), step (7) described SiO2The thickness of passivation layer is 50~200nm.
Preferably, in step (8), the SiO of the growths of PECVD twice is utilized2It is carved as passivation layer insulating and electrode
Protective layer is lost, while as CBL patterned etch mask layers, interdigital figure corresponding with N electrode is formed using the method for BOE corrosion
Shape.
Preferably, in step (8), after preparing CBL graph layers, SiO is removed using BOE solution2It is exposed while passivation layer
Go out the extraction source electrode of HEMT.
Preferably, in step (8), the CBL figure layer thickness of preparation is 100~400nm.
Preferably, the metal layer of the P electrode described in step (9) includes the Ni of 0.5~5nm successively, the Ag of 50~100nm or
The Cr of person's multilayer Ni/Ag, 20~50nm, the Pt of 100~200nm, Sn (200~1000nm)/Au (100~300nm)/Sn (200
~1000nm), overall thickness is more than 2 μm.
Preferably, in step (10), the bonding face for being bonded silicon substrate is sequentially depositing the Cr of 20~50nm, 100~200nm's
The Ni of Pt, 200~400nm, Sn (200~1000nm)/Au (100~300nm)/Sn (200~1000nm) multiple layer metal, bonding
Temperature is 250~300 DEG C, and bonding pressure is 3000~6000mbar, and bonding time is 20~60min.
Preferably, in step (11), the source of HEMT, gate electrode carry out among trepanning etching in the etchings of ICP twice
PECVD passivation layers growth, the SiO that passivation layer is 0.5~1 μm2。
The epitaxial structure of device main body of the present invention from the bottom to top successively include Si substrates, AlN/GaN buffer layers, n-GaN layers,
Multiple quantum well layer, p-GaN layer, i-GaN layers of+AlGaN back ofs the body barrier layer, AlN insert layers, AlGaN potential barrier.
On the basis of the epitaxial structure of LED+HEMT, the preparation process of device integrated system is as follows：
1, by photoetching, electron beam evaporation and etc. in specified area deposition HEMT device source, drain metal, and carry out
High annealing obtains HEMT device source, leakage Ohm contact electrode；
2, photoetching, ICP dry etchings are carried out to the chip for preparing source and drain Ohm contact electrode, exposes LED region
The p-GaN in domain, and carry out 600~700 DEG C of magnesium-doped ion-activated annealings；
3, to it is described mark off HEMT, the chip of LED region carries out photoetching again, ICP dry etchings by the sources HEMT, electric leakage
Pole carries out device isolation with hetero-junctions；
4, using photoetching, electron beam evaporation and etc. Schottky gate electricity is prepared between source after the isolation, drain electrode
Pole；
5, SiO is grown using the method for PECVD in the chip surface2Dielectric layer film reaches blunt to hetero-junctions surface
Change the purpose of protection；
6, photoetching, ICP dry etchings, source of exposure, leakage, gate electrode are carried out to the chip after above-mentioned passivation, and uses electronics
Beam evaporation extraction electrode finally continues to deposit SiO using PECVD2, to achieve the purpose that source, drain electrode etching protection；
7, photoetching, BOE wet etchings are carried out to the LED region of said chip, forms current blocking corresponding with n- electrodes
Layer (CBL) figure, while exposing LED region p-GaN and part HEMT device source electrode region.
8, the P electrode of LED is prepared on the chip that the surfaces p-GaN have CBL figures, and is carried out 450~550 DEG C and moved back
Fire processing, due to being connect with HEMT source electrodes, which is also the source electrode of HEMT simultaneously；
9, by the Si bases chip for preparing p-electrode be bonded silicon substrate by way of metal bonding and be bonded, then
Remove extension silicon substrate by the method for mechanical grinding and chemical attack, achievees the purpose that substrate shifts；
10, roughening treatment is carried out to the n-GaN of substrate transfer rear surface exposure, to reach the mesh for increasing LED light extractions
's；Then photoetching, ICP etching processings are carried out to the chip, exposes grid, the drain electrode of HEMT device；
11, SiO is grown using the method for PECVD2, protection is passivated to the GaN material side wall after ICP etchings,
Then repeat photoetching, ICP etch steps, exposure HEMT gate, drain electrode；
12, HEMT structure grid, leakage extraction electrode and LED structure N electricity are deposited by the way of photoetching, electron beam evaporation
Pole, and 200~300 DEG C of annealings.
The principle of the present invention is as follows：
The single chip integrated preparation method of the HMET power devices and vertical structure LED of the present invention, first from the full structures of LED
Adding HEMT hetero-junctions, orthogonal epitaxial growth starts successively, shares by the source electrode of HEMT and the P electrode of LED and realizes interconnection, so
The final single-chip integration for realizing device is shifted by substrate bonding afterwards.
Compared with the existing technology, the beneficial effects of the present invention are：
The present invention realizes the single-chip integration of GaN power devices and vertical structure LED, reduces LED voltage driving circuit
Volume, simplify vertical structure LED Voltag driving circuit design, improve HEMT and LED integrated systems power density and
Luminous efficiency.
Description of the drawings
Fig. 1 is the epitaxial structure schematic diagram of the embodiment of the present invention；
Fig. 2 is the epitaxial layer structure schematic diagram after the constituency etching of the embodiment of the present invention, and the etching is by HEMT in LED region
Domain demarcates；
Fig. 3 is the chip cross-section schematic diagram prepared after P electrode of the embodiment of the present invention；
Fig. 4 is the chip schematical top view after having prepared P electrode of the embodiment of the present invention；
Fig. 5 is the schematic cross-section of the final integration system chip of the embodiment of the present invention；
Fig. 6 is the final integration system chip schematical top view of the embodiment of the present invention.
Specific implementation mode
With reference to embodiment and attached drawing, the present invention is described in further detail, but embodiments of the present invention are unlimited
In this.
Embodiment 1
(1) MOCVD 1.8 μm of AlN/GaN buffer layers 2 of epitaxial growth, n-GaN layers of 2.1um successively on silicon substrate 1 are used
3,180nm InGaN/GaN multiple quantum well layers 4,200nm p-GaN layers 5,200nm i-GaN buffer layers and AlGaN carry on the back barrier layer 6
(Al groups are divided into 15%), 100nm i-GaN channel layers 7,20nm AlGaN potential barriers 8 (Al groups are divided into 25%), epitaxial structure is such as
Shown in Fig. 1；
(2) on the epitaxial structure of step (1), the regions HEMT and LED region are designed, using photoetching technique, electron beam
Evaporation technique, in HEMT area deposition multiple layer metal Ti (20nm)/Al (120nm)/Ni (40nm)/Au (50nm), in 850 DEG C of nitrogen
The source of annealing 30s formation, leakage Ohm contact electrode, distribution of electrodes are as shown in Figure 3 under gas atmosphere；
(3) wafer in the source, drain electrode that prepare to step (2) carries out Twi-lithography and etch step, first by LED region
Hetero-junctions etch completely, p-GaN layer is exposed, as shown in Fig. 2, and in 600 DEG C of N2Anneal 90s under atmosphere, realizes magnesium-doped
It is ion-activated.Again by source, drain electrode and heterogeneous junction isolation, etching depth 350nm；
(4) the crystal column surface source in step (3) through over etching, that Ni (100nm)/Au (200nm) is deposited between drain electrode is double
Layer metal, forms Schottky contacts gate electrode.Then the method for using PECVD grows the SiO of one layer of 100nm in crystal column surface2It is blunt
Change layer film；
(5) wafer that grown passivation layer film to step (4) carries out photoetching, using BOE solution corrosions removal electrode pad
The SiO on surface2, etching time 80s only exposes the source of HEMT, leakage, gate electrode, then uses electron-beam evaporation Ti
(30nm)/Au (250nm) double-level-metal draws this three electrode, and ensures that extraction electrode pad is fallen in SiO2On passivation layer, finally again
The SiO of 200nm is grown using PECVD technique2Insulating layer；
(6) step (5) grown to the method that the wafer of insulating layer first uses photoetching technique to add BOE solution wet etchings,
Current barrier layer (CBL) corresponding with N electrode figure, etching time 240s are formed in LED region, and exposes part source electricity
Pole, forms structure as shown in Figure 3,4, HF in the BOE solution：NH4F=1:7 (volume ratios)；
(7) crystal column surface of CBL graph layers is sequentially depositing W metal using electron beam evaporation, thermal evaporation in step (6)
(3nm)/Ag(100nm)/Ti(100nm)Cr(30nm)/Pt(150nm)/Ni(30nm)/Sn(1000nm)/Au(300nm)/Sn
(300nm), these metals constitute the Ohmic contact P electrode of LED and the source electrode of HEMT, but Ag has the work in reflecting layer
With Ti, Pt are used for doing protective layer, and Cr is used as adhesion layer, and Sn/Au metal layers are used as bonding metal layer；
(8) wafer that step (7) is deposited to p-electrode metal, and equally deposited Cr (30nm)/Au (300nm)/Sn
The silicon substrate of (1000nm)/Au (200nm) multiple layer metal is 260 DEG C in temperature, and pressure is bonded under conditions of being 3000mbar
30min；
(9) wafer that step (8) bonding is completed is removed into initial epitaxial substrate, residue 40 using the method for mechanical grinding
~50 μm of remaining silicon uses HNO3：HF：Glacial acetic acid (2：1：1, volume ratio) solution corrosion 4min, then use Cl base gases ICP
Etching removal buffer epitaxial layers, electrode power 500W, etch period 10min expose n-GaN layers；
(10) wafer that step (9) is exposed to n-GaN, impregnates 1min, solution temperature 70 in 30wt%KOH solution
DEG C, make n-GaN roughing in surface, on corresponding leakage, the progress photoetching of gate electrode extraction electrode region, etching, removal leakage, gate electrode
N-GaN, using PECVD grow 500nm SiO2Insulating layer is passivated protection to GaN etched sidewalls, then uses BOE rotten
The method of erosion exposes leakage, gate electrode pad, etching time 480s, but retains sidewall passivation layer；
(11) wafer that step (10) is prepared for side wall passivation protection prepares leakage using electron beam evaporation, grid draw electricity
Pole, electrode structure are Ti (50nm)/Au (1000nm).And interdigital N electricity is prepared using photoetching, BOE burn into electron beam evaporation techniques
Pole etching time is 400s, and N electrode metal structure is Ti (20nm)/Al (60nm)/Ti (30nm)/Au (40nm)/Pt
(100nm)/Au (1000nm), and carry out 200 DEG C of N2Ambient anneal 1min, final integrated system are as shown in Figure 5,6.
The monolithically integrated system of HEMT and vertical structure LED manufactured in the present embodiment realize the operating current of LED by
The grid voltage of HEMT device controls, and system bulk is 1 × 1mm, compared to conventional package, heterogeneous integrated Voltag driving circuit,
1000 times of volume-diminished.Integrated compared to traditional HEMT and transversary LED, which increases 10~12%,
Luminous power increases 15~17%.
Embodiment 2
(1) MOCVD 1.8 μm of AlN/GaN buffer layers 2 of epitaxial growth, n-GaN layers of 2.1um successively on silicon substrate 1 are used
3,180nm InGaN/GaN multiple quantum well layers 4,200nm p-GaN layers 5,200nm i-GaN buffer layers and AlGaN carry on the back barrier layer 6
(Al groups are divided into 15%), 100nm i-GaN channel layers 7,20nm AlGaN potential barriers 8 (Al groups are divided into 20%), epitaxial structure is such as
Shown in Fig. 1；
(2) on the epitaxial structure of step (1), the regions HEMT and LED region are designed, using photoetching technique, electron beam
Evaporation technique, in HEMT area deposition multiple layer metal Ti (20nm)/Al (120nm)/Ni (40nm)/Au (50nm), in 850 DEG C of nitrogen
The source of annealing 30s formation, leakage Ohm contact electrode, distribution of electrodes are as shown in Figure 3 under gas atmosphere；
(3) wafer in the source, drain electrode that prepare to step (2) carries out Twi-lithography and etch step, first by LED region
Hetero-junctions etch completely, p-GaN layer is exposed, as shown in Fig. 2, and in 600 DEG C of N2Anneal 60s under atmosphere, realizes magnesium-doped
It is ion-activated.Again by source, drain electrode and heterogeneous junction isolation, etching depth 370nm；
(4) the crystal column surface source in step (3) through over etching, that Ni (100nm)/Au (200nm) is deposited between drain electrode is double
Layer metal, forms Schottky contacts gate electrode.Then the method for using PECVD grows the SiO of one layer of 200nm in crystal column surface2It is blunt
Change layer film；
(5) wafer that grown passivation layer film to step (4) carries out photoetching, using BOE solution corrosions removal electrode pad
The SiO on surface2, etching time 160s only exposes the source of HEMT, leakage, gate electrode, then uses electron-beam evaporation Ti
(30nm)/Au (250nm) double-level-metal draws this three electrode, and ensures that extraction electrode pad is fallen in SiO2On passivation layer, finally again
The SiO of 200nm is grown using PECVD technique2Insulating layer；
(6) step (5) grown to the method that the wafer of insulating layer first uses photoetching technique to add BOE solution wet etchings,
Current barrier layer (CBL) corresponding with N electrode figure, etching time 320s are formed in LED region, and exposes part source electricity
Pole, forms structure as shown in Figure 3,4, HF in the BOE solution：NH4F=1:7 (volume ratios)；
(7) crystal column surface of CBL graph layers is sequentially depositing W metal using electron beam evaporation, thermal evaporation in step (6)
(1nm)/Ag(100nm)/Ti(100nm)Cr(30nm)/Pt(150nm)/Ni(30nm)/Sn(500nm)/Au(300nm)/Sn
(300nm), these metals constitute the Ohmic contact P electrode of LED and the source electrode of HEMT, but Ag has the work in reflecting layer
With Ti, Pt are used for doing protective layer, and Cr is used as adhesion layer, and Sn/Au metal layers are used as bonding metal layer；
(8) wafer that step (7) is deposited to p-electrode metal, and equally deposited Cr (30nm)/Au (300nm)/Sn
The silicon substrate of (500nm)/Au (200nm) multiple layer metal is 300 DEG C in temperature, and pressure is bonded under conditions of being 5000mbar
30min；
(9) wafer that step (8) bonding is completed is removed into initial epitaxial substrate, residue 40 using the method for mechanical grinding
~50 μm of remaining silicon uses HNO3：HF：Glacial acetic acid (2：1：1, volume ratio) solution corrosion 4min, then use Cl base gases ICP
Etching removal buffer epitaxial layers, electrode power 500W, etch period 10min expose n-GaN layers；
(10) wafer that step (9) is exposed to n-GaN, impregnates 1min, solution temperature 70 in 30wt%KOH solution
DEG C, make n-GaN roughing in surface, on corresponding leakage, the progress photoetching of gate electrode extraction electrode region, etching, removal leakage, gate electrode
N-GaN, using PECVD grow 1000nm SiO2Insulating layer is passivated protection to GaN etched sidewalls, then uses BOE
The method of corrosion exposes leakage, gate electrode pad, etching time 960s, but retains sidewall passivation layer；
(11) wafer that step (10) is prepared for side wall passivation protection prepares leakage using electron beam evaporation, grid draw electricity
Pole, electrode structure are Ti (50nm)/Au (1000nm).And interdigital N electricity is prepared using photoetching, BOE burn into electron beam evaporation techniques
Pole etching time is 800s, and N electrode metal structure is Ti (20nm)/Al (60nm)/Ti (30nm)/Au (40nm)/Pt
(100nm)/Au (1000nm), and carry out 200 DEG C of N2Ambient anneal 1min, final integrated system are as shown in Figure 5,6.
The monolithically integrated system of HEMT and vertical structure LED that the present embodiment is prepared are similar to Example 1, herein not
It repeats again.
Embodiment 3
(1) MOCVD 1.8 μm of AlN/GaN buffer layers 2 of epitaxial growth, n-GaN layers of 2.1um successively on silicon substrate 1 are used
3,180nm InGaN/GaN multiple quantum well layers 4,200nm p-GaN layers 5,200nm i-GaN buffer layers and AlGaN carry on the back barrier layer 6
(Al groups are divided into 15%), 100nm i-GaN channel layers 7,20nm AlGaN potential barriers 8 (Al groups are divided into 20%), epitaxial structure is such as
Shown in Fig. 1；
(2) on the epitaxial structure of step (1), the regions HEMT and LED region are designed, using photoetching technique, electron beam
Evaporation technique, in HEMT area deposition multiple layer metal Ti (20nm)/Al (120nm)/Ni (40nm)/Au (50nm), in 850 DEG C of nitrogen
The source of annealing 30s formation, leakage Ohm contact electrode, distribution of electrodes are as shown in Figure 3 under gas atmosphere；
(3) wafer in the source, drain electrode that prepare to step (2) carries out Twi-lithography and etch step, first by LED region
Hetero-junctions etch completely, p-GaN layer is exposed, as shown in Fig. 2, and in 600 DEG C of N2Anneal 120s under atmosphere, realizes magnesium-doped
It is ion-activated.Again by source, drain electrode and heterogeneous junction isolation, etching depth 300nm；
(4) the crystal column surface source in step (3) through over etching, that Ni (100nm)/Au (200nm) is deposited between drain electrode is double
Layer metal, forms Schottky contacts gate electrode.Then the method for using PECVD grows the SiO of one layer of 50nm in crystal column surface2Passivation
Layer film；
(5) wafer that grown passivation layer film to step (4) carries out photoetching, using BOE solution corrosions removal electrode pad
The SiO on surface2, etching time 40s only exposes the source of HEMT, leakage, gate electrode, then uses electron-beam evaporation Ti
(30nm)/Au (250nm) double-level-metal draws this three electrode, and ensures that extraction electrode pad is fallen in SiO2On passivation layer, finally again
The SiO of 200nm is grown using PECVD technique2Insulating layer；
(6) step (5) grown to the method that the wafer of insulating layer first uses photoetching technique to add BOE solution wet etchings,
Current barrier layer (CBL) corresponding with N electrode figure, etching time 200s are formed in LED region, and exposes part source electricity
Pole, forms structure as shown in Figure 3,4, HF in the BOE solution：NH4F=1:7 (volume ratios)；
(7) crystal column surface of CBL graph layers is sequentially depositing W metal using electron beam evaporation, thermal evaporation in step (6)
(1nm)/Ag(100nm)/Ti(100nm)Cr(30nm)/Pt(150nm)/Ni(30nm)/Sn(800nm)/Au(300nm)/Sn
(300nm), these metals constitute the Ohmic contact P electrode of LED and the source electrode of HEMT, but Ag has the work in reflecting layer
With Ti, Pt are used for doing protective layer, and Cr is used as adhesion layer, and Sn/Au metal layers are used as bonding metal layer；
(8) wafer that step (7) is deposited to p-electrode metal, and equally deposited Cr (30nm)/Au (300nm)/Sn
The silicon substrate of (800nm)/Au (200nm) multiple layer metal is 280 DEG C in temperature, and pressure is bonded under conditions of being 4000mbar
30min；
(9) wafer that step (8) bonding is completed is removed into initial epitaxial substrate, residue 40 using the method for mechanical grinding
~50 μm of remaining silicon uses HNO3：HF：Glacial acetic acid (2：1：1, volume ratio) solution corrosion 4min, then use Cl base gases ICP
Etching removal buffer epitaxial layers, electrode power 500W, etch period 10min expose n-GaN layers；
(10) wafer that step (9) is exposed to n-GaN, impregnates 1min, solution temperature 70 in 30wt%KOH solution
DEG C, make n-GaN roughing in surface, on corresponding leakage, the progress photoetching of gate electrode extraction electrode region, etching, removal leakage, gate electrode
N-GaN, using PECVD grow 700nm SiO2Insulating layer is passivated protection to GaN etched sidewalls, then uses BOE rotten
The method of erosion exposes leakage, gate electrode pad, etching time 600s, but retains sidewall passivation layer；
(11) wafer that step (10) is prepared for side wall passivation protection prepares leakage using electron beam evaporation, grid draw electricity
Pole, electrode structure are Ti (50nm)/Au (1000nm).And interdigital N electricity is prepared using photoetching, BOE burn into electron beam evaporation techniques
Pole etching time is 560s, and N electrode metal structure is Ti (20nm)/Al (60nm)/Ti (30nm)/Au (40nm)/Pt
(100nm)/Au (1000nm), and carry out 200 DEG C of N2Ambient anneal 1min, final integrated system are as shown in Figure 5,6.
The monolithically integrated system of HEMT and vertical structure LED that the present embodiment is prepared are similar to Example 1, herein not
It repeats again.
The present invention is using the above embodiment is a preferred embodiment of the present invention, but embodiments of the present invention are not by institute
State the limitation of embodiment, it is other it is any without departing from the spirit and principles of the present invention made by change, modification, substitute,
Combination simplifies, and should be equivalent substitute mode, is included within the scope of the present invention.
Claims (10)
1. the method for integrating monolithic of a kind of high electron mobility transistor and light emitting diode with vertical structure, which is characterized in that packet
Include following steps：
(1) MOCVD technologies are utilized, on a si substrate the full structures of epitaxial growth LED, continues the original position heterogeneous junctions of epitaxial growth HEMT
Structure obtains integrated epitaxial chip structure；
(2) high annealing is carried out in specified area deposition HEMT device source, drain metal by photoetching, electron beam evaporation,
Obtain HEMT device source, drain electrode；
(3) chip in the source, drain electrode that prepare to step (2) carries out photoetching, ICP dry etchings, exposes the p- of LED region
GaN layer, and carry out magnesium-doped ion-activated annealing；
(4) HEMT marked off to step (3), LED region chip carry out photoetching, ICP dry etchings again by source, drain electrode
Region carries out device isolation with hetero-junctions；
(5) it utilizes source after step (4) isolation of photoetching, electron beam evaporation, prepare schottky gate electrode between drain electrode, complete
HEMT device makes；
(6) chip surface obtained by step (5) grows SiO using the method for PECVD2Passivation layer reaches to hetero-junctions surface passivation
The purpose of protection；
(7) chip after being passivated to step (6) carries out photoetching, ICP dry etchings, exposes the source of part HEMT, leakage, grid electricity
Pole, and electron beam evaporation extraction electrode is used, it then proceedes to deposit SiO using PECVD2It is passivated protection, extraction electrode portion
The SiO for dividing the regions pad to be grown in step (5)2On, the damage to avoid subsequent etching to source, drain electrode；
(8) photoetching, BOE wet etchings are carried out to the LED region of chip obtained by step (7), forms CBL figures corresponding with N electrode
Shape, while exposing LED region and part HEMT device source electrode region；
(9) prepare the P electrode of LED on the chip that step (8) p-GaN has CBL figures, and made annealing treatment, due to
HEMT source electrodes connect, which is also the source electrode of HEMT simultaneously；
(10) step (9) is prepared to the Si bases chip of p-electrode and is bonded silicon substrate by way of metal bonding and is bonded, then
Remove extension silicon substrate by the method for mechanical grinding and chemical attack, achievees the purpose that substrate shifts；
(11) roughening treatment is carried out to the n-GaN of step (10) substrate transfer rear surface exposure, to reach the mesh for increasing LED light extractions
, photoetching, ICP etching processings are carried out to gained chip, expose grid, the drain electrode of HEMT device, is given birth to using the method for PECVD
Long SiO2, protection is passivated to the GaN material side wall after ICP etchings, then repeats photoetching, ICP etch steps, exposure
Grid, drain electrode；
(12) HEMT structure grid, leakage extraction electrode and LED structure N electrode are deposited by the way of photoetching, electron beam evaporation,
And it makes annealing treatment.
2. according to the method described in claim 1, it is characterized in that, the full structures of step (1) LED include 1~2 μm successively
AlN/GaN buffer layers, 1.5~2.5 μm of n-GaN layers, the multiple quantum well layer of 100~200nm and the p-GaN of 150~250nm
Layer；The HEMT heterojunction structures include the i-GaN buffer layers of 100~200nm successively, and the AlGaN of 40~80nm carries on the back barrier layer,
The i-GaN channel layers of 60~120nm and the AlGaN potential barrier of 20~25nm；Al groups are divided into 10% in the AlGaN back ofs the body barrier layer
~20%, Al groups are divided into 20%~25% in the AlGaN potential barrier.
3. according to the method described in claim 1, it is characterized in that, step (3) the magnesium-doped ion-activated annealing temperature
Degree is 600~700 DEG C, and annealing time is 1~2min.
4. according to the method described in claim 1, it is characterized in that, step (6), step (7) described SiO2The thickness of passivation layer is
50~200nm.
5. according to the method described in claim 1, it is characterized in that, in step (8), the SiO of the growths of PECVD twice is utilized2As
It is passivated layer insulating and electrode etch-protecting layer, while as CBL patterned etch mask layers, the method corroded using BOE
Form interdigital figure corresponding with N electrode.
6. according to the method described in claim 1, it is characterized in that, in step (8), using BOE solution corrosions during shape
At CBL graph layers, while exposing the source electrode of HEMT extractions.
7. according to the method described in claim 1, it is characterized in that, in step (8), the thickness for preparing CBL graph layers is 100~
400nm。
8. according to the method described in claim 1, it is characterized in that, the metal layer of the P electrode described in step (9) includes successively
The Ag of the Ni of 0.5~5nm, 50~100nm or the Cr of multilayer Ni/Ag, 20~50nm, the Pt of 100~200nm, Sn (200~
1000nm)/Au (100~300nm)/Sn (200~1000nm), overall thickness are more than 2 μm.
9. according to the method described in claim 1, it is characterized in that, in step (10), the bonding face for being bonded silicon substrate sinks successively
The Cr of 20~50nm of product, the Ni of the Pt of 100~200nm, 200~400nm, Sn (200~1000nm)/Au (100~300nm)/
Sn (200~1000nm) multiple layer metal, bonding temperature are 250~300 DEG C, and bonding pressure is 3000~6000mbar, when bonding
Between be 20~60min.
10. according to the method described in claim 1, it is characterized in that, in step (11), the etchings of ICP twice to the source of HEMT,
Gate electrode carries out having carried out a PECVD passivation layers growth, the SiO that passivation layer is 0.5~1 μm among trepanning etching2。
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