CN108540123A

CN108540123A - Level shifting circuit

Info

Publication number: CN108540123A
Application number: CN201710119920.9A
Authority: CN
Inventors: 方刘禄; 刘跃智; 徐灵炎; 张伟国
Original assignee: Shanghai Fudan Microelectronics Group Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2017-03-02
Filing date: 2017-03-02
Publication date: 2018-09-14
Anticipated expiration: 2037-03-02
Also published as: CN108540123B

Abstract

A kind of level shifting circuit, the circuit include：Low-voltage level conversion circuit is suitable for, when the supply voltage of the high power domain of access is less than or equal to corresponding device pressure voltage, the signal of the low voltage domain of input being respectively converted into the supply voltage and no-voltage of corresponding high power domain；High-voltage level conversion circuit, when supply voltage suitable for the high power domain in access is located between twice of the corresponding device pressure voltage and the corresponding device pressure voltage, the signal of the low power domain of input is respectively converted into the supply voltage and low-voltage of the high power domain.Above-mentioned scheme can be compatible with the level shifting circuit of high-low voltage, can expand the scope of application of level shifting circuit.

Description

Level shifting circuit

Technical field

The present invention relates to field of circuit technology, more particularly to a kind of level shifting circuit.

Background technology

Level shifting circuit is widely used in various interface circuits and input is defeated for realizing the logical transition of level Go out in unit.

But level shifting circuit in the prior art is only capable of that the level conversion less than or equal to device pressure resistance is implemented separately Or the level conversion higher than device pressure resistance is implemented separately, and conversion speed is not high, cannot realize and be less than or equal to simultaneously The level conversion of device pressure resistance is higher than the level conversion of device pressure resistance again, and realizes high-speed transitions.Limit level conversion electricity The scope of application on road.

Invention content

The embodiment of the present invention solves the problems, such as be how to realize the high-speed level conversion circuit of compatible high low supply voltage, expand The scope of application of big level shifting circuit.

To solve the above problems, an embodiment of the present invention provides a kind of level shifting circuit, the circuit includes：Low-voltage Level shifting circuit is suitable for when the supply voltage of the high power domain of access is less than or equal to corresponding device pressure voltage, will be defeated The signal of the low voltage domain entered is respectively converted into the supply voltage and no-voltage of corresponding high power domain；High-voltage level conversion electricity Road is suitable for being located at the corresponding device pressure voltage and the corresponding device pressure resistance in the supply voltage of the high power domain of access When between twice of value, the signal of the low power domain of input is respectively converted into the supply voltage and low-voltage of the high power domain.

Optionally, the low-voltage level conversion circuit includes the first input unit, low-pressure passage and the first output unit； First input unit is suitable for when the supply voltage of the high power domain of input is less than or equal to corresponding device pressure voltage, The signal of the low power domain received is converted into corresponding differential signal；The low-pressure passage, suitable for being inputted described first The differential signal that cell translation obtains is exported to first output unit；First output unit is suitable for the low pressure The differential signal of access output is converted to the supply voltage and no-voltage of complementary high power domain.

Optionally, first input unit includes the first PMOS tube, the first NMOS tube, the second NMOS tube and the 3rd NMOS Pipe；The grid end of first PMOS tube and the grid end of first NMOS tube couple, and as the signal of preset low power domain Input terminal, the signal of the source of first PMOS tube and the low power domain couples, the drain terminal of first PMOS tube with The drain terminal of first NMOS tube couples, and source and the ground wire of first NMOS tube couple；The grid end of second NMOS tube It is coupled with the grid end of first PMOS tube and first NMOS tube, drain terminal and the first voltage node of second NMOS tube Coupling, source and the ground wire of second NMOS tube couple；The grid end of the third NMOS tube and first PMOS tube and institute The drain terminal coupling of the first NMOS tube is stated, drain terminal and the second voltage node of the third NMOS tube couple, the third NMOS tube Source and ground wire couple.

Optionally, the low-pressure passage includes switch subelement and the first pressure-resistant subelement；The switch subelement includes 4th NMOS tube and the 6th NMOS tube；Described first pressure-resistant subelement includes the 5th NMOS tube and the 7th NMOS tube；Described 4th The grid end of NMOS tube is coupled with tertiary voltage node, the source coupling of the drain terminal and the 5th NMOS tube of the 4th NMOS tube It connects, source and the first voltage node of the 4th NMOS tube couple；The grid end of 5th NMOS tube and the 7th NMOS The grid end of pipe is coupled with the 4th voltage node, and the drain terminal of the 5th NMOS tube and the 5th voltage node couple, and the described 5th The source of NMOS tube and the drain terminal of the 4th NMOS tube couple；The grid end of 6th NMOS tube and tertiary voltage node coupling It connects, the drain terminal of the 6th NMOS tube is coupled with the source of the 7th NMOS tube, the source and second of the 6th NMOS tube Voltage node couples；The drain terminal of 7th NMOS tube and the 6th voltage node couple, the source of the 7th NMOS tube and institute State the drain terminal coupling of the 6th NMOS tube.

Optionally, first output unit includes：4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS Pipe, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube and the 11st PMOS tube；The grid end and the 7th of 4th PMOS tube Voltage node couples, and the source of the 4th PMOS tube is coupled with the drain terminal of the 6th PMOS tube；5th PMOS tube Grid end and the 7th voltage node couple, and drain terminal and the 5th voltage node of the 5th PMOS tube couple, and described the The source of five PMOS tube is coupled with preset positive output voltage node；The grid end of 6th PMOS tube and the positive output voltage Node couples, and the source of the 6th PMOS tube is coupled with the supply voltage of the high power domain；The grid of 7th PMOS tube The supply voltage of end and source and the high power domain couples, drain terminal and the positive output voltage node of the 7th PMOS tube Coupling；The grid end of 8th PMOS tube and the 7th voltage node VBP are coupled, the source of the 8th PMOS tube with it is described The drain terminal of tenth PMOS tube couples, and drain terminal and the 6th voltage node of the 8th PMOS tube couple；9th PMOS The grid end of pipe is coupled with the 7th voltage node, and drain terminal and the 6th voltage node of the 9th PMOS tube couple, institute State the source of the 9th PMOS tube and the coupling of the drain terminal of the grid end of the 6th PMOS tube and the 7th PMOS tube；Described tenth The grid end of PMOS tube is coupled with negative output voltage node, the supply voltage of the source and the high power domain of the tenth PMOS tube Coupling；The grid end and source of 11st PMOS tube are coupled with the power voltage terminal of the high power domain, and the described 11st The drain terminal of PMOS tube is coupled with the negative output voltage node.

Optionally, the tertiary voltage node and the signal of the low power domain couple；4th voltage node and institute State the supply voltage coupling of high power domain；7th voltage node is coupled with preset no-voltage.

Optionally, the high-voltage level conversion circuit includes the second input unit, high-pressure passage and the second output unit； Second input unit is suitable for, when the supply voltage of the high power domain of input is more than corresponding device pressure voltage, to be connect The signal for the low power domain received is converted to corresponding differential signal；The low-pressure passage is suitable for turning second input unit The differential signal got in return is exported to second output unit；Second output unit is suitable for the low-pressure passage is defeated The differential signal gone out is converted to complementary high power supply voltage domain voltage and low-voltage.

Optionally, second input unit includes first PMOS tube, first NMOS tube, the 2nd NMOS Pipe and the third NMOS tube；The grid end of first PMOS tube is coupled with the input terminal of the input signal, and described first The source of PMOS tube and the signal of the low power domain couple, the leakage of the drain terminal of first PMOS tube and first NMOS tube End coupling；The source of first NMOS tube is coupled with ground wire, the grid end of second NMOS tube and first PMOS tube and The grid end of first NMOS tube couples, and drain terminal and the first voltage node of second NMOS tube couple, the 2nd NMOS The source of pipe is coupled with ground wire, the drain terminal of the grid end of the third NMOS tube and first PMOS tube and first NMOS tube Coupling, drain terminal and the second voltage node of the third NMOS tube couple, and source and the ground wire of the third NMOS tube couple.

Optionally, the high-pressure passage includes the second pressure-resistant subelement being mutually coupled and diode clamp subelement；Institute It includes the 8th NMOS tube and the tenth NMOS tube to state the second pressure-resistant subelement；The diode clamp subelement includes the 9th NMOS Pipe, the 11st NMOS tube, the second PMOS tube and third PMOS tube；The grid end of 8th NMOS tube and the 4th voltage node Coupling, the drain terminal of the 8th NMOS tube and the grid end of second PMOS tube couple, the source of the 8th NMOS tube and the One voltage node couples；The grid end of 9th NMOS tube is coupled with the 5th voltage node, the leakage of the 9th NMOS tube End and the drain terminal of second PMOS tube couple, and the source of the 9th NMOS tube is coupled with the drain terminal of the 8th NMOS tube； The source of second PMOS tube is coupled with the 5th voltage node；The grid end and the 4th voltage node of tenth NMOS tube Coupling, the drain terminal of the tenth NMOS tube are coupled with the grid end of the third PMOS tube, the source of the tenth NMOS tube and institute State the coupling of second voltage node；The grid end of 11st NMOS tube is coupled with the 6th voltage node, and the described 11st The drain terminal of NMOS tube and the drain terminal of the third PMOS tube couple, the grid of the source and third PMOS tube of the 11st NMOS tube End coupling；The grid end and the coupling of the 6th voltage node of the source of the third PMOS tube and the 11st NMOS tube.

Optionally, second output unit includes that subelement and complementary signal output son list are eliminated in the mutual coupling being mutually coupled Member；It includes the 5th PMOS tube and the 9th PMOS tube that subelement is eliminated in the mutual coupling；Complementary signal output is single Member includes the 4th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the tenth PMOS tube With the 11st PMOS tube；The grid end of 4th PMOS tube is coupled with the 7th voltage node, the source of the 4th PMOS tube with The drain terminal of 6th PMOS tube couples；The grid end of 5th PMOS tube is coupled with the 7th voltage node, and the described 5th The drain terminal of PMOS tube is coupled with the 5th voltage node, source and the preset positive output voltage node of the 5th PMOS tube Coupling；The grid end of 6th PMOS tube is coupled with the positive output voltage node, the source of the 6th PMOS tube with it is described The supply voltage of high power domain couples；The supply voltage coupling of the grid end and source and the high power domain of 7th PMOS tube It connects, drain terminal and the positive output voltage node of the 7th PMOS tube couple；The grid end of 8th PMOS tube and described the Seven voltage node VBP couplings, the source of the 8th PMOS tube are coupled with the drain terminal of the tenth PMOS tube, the 8th PMOS The drain terminal of pipe is coupled with the 6th voltage node；The grid end of 9th PMOS tube is coupled with the 7th voltage node, institute The drain terminal and the 6th voltage node for stating the 9th PMOS tube couple, the source and the 6th PMOS tube of the 9th PMOS tube Grid end and the 7th PMOS tube drain terminal coupling；The grid end of tenth PMOS tube and the negative output voltage node coupling It connects, the source of the tenth PMOS tube is coupled with the supply voltage of the high power domain；The grid end of 11st PMOS tube and The power voltage terminal of source and the high power domain couples, drain terminal and the negative output voltage node of the 11st PMOS tube Coupling.

Optionally, the tertiary voltage node is coupled with ground wire；4th voltage node and 2/3 the high power domain Supply voltage coupling；5th voltage node and coupling；7th voltage node and 1/3 the high power domain electricity Source voltage coupling.

Compared with prior art, technical scheme of the present invention has the following advantages that：

Above-mentioned scheme can connect by the setting of low-voltage level conversion circuit and high-voltage level conversion circuit When the supply voltage of the high power domain entered is less than or equal to device pressure voltage, the signal of the low power domain of input is converted to described The supply voltage or no-voltage of high power domain, and corresponding device can be located in the supply voltage of the high power domain of access When between twice of part pressure voltage and the corresponding device pressure voltage, the signal of the low power domain of the input is respectively converted into The supply voltage and low-voltage of the high power domain, can be compatible with the level conversion of high low supply voltage, turn to expand level Change the scope of application of circuit.

Description of the drawings

Fig. 1 is a kind of block schematic illustration of level shifting circuit in the embodiment of the present invention；

Fig. 2 is a kind of circuit diagram of level shifting circuit in the embodiment of the present invention；

Fig. 3 is that a kind of level shifting circuit in the embodiment of the present invention is equivalent when supply voltage is less than device pressure voltage Circuit diagram；

Fig. 4 is that a kind of level shifting circuit in the embodiment of the present invention is equivalent when supply voltage is more than device pressure voltage Circuit diagram.

Specific implementation mode

To solve the above-mentioned problems in the prior art, technical solution used in the embodiment of the present invention passes through low-voltage The setting of level shifting circuit and high-voltage level conversion circuit can be less than or wait in the supply voltage of the high power domain of access When device pressure voltage, the signal of the low power domain of input is converted to the supply voltage or no-voltage of the high power domain, And corresponding device pressure voltage and the corresponding device pressure resistance can be located in the supply voltage of the high power domain of access When between twice of value, the signal of the low power domain of the input is respectively converted into the supply voltage of the high power domain and low electricity Pressure, can be compatible with the level conversion of high low supply voltage, to expand the scope of application of level shifting circuit.

To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 1 shows a kind of block schematic illustration of level shifting circuit in the embodiment of the present invention.Referring to Fig. 1, the present invention Level shifting circuit in embodiment may include low-voltage level conversion circuit 11 and high-voltage level conversion circuit 12, In：

Low-voltage level conversion circuit 11 is suitable for being less than or equal to corresponding device in the supply voltage of the high power domain of access When part pressure voltage, the signal of the low power domain of input is respectively converted into the supply voltage and no-voltage of corresponding high power domain.

High-voltage level conversion circuit 12 is suitable for being located at the corresponding device in the supply voltage of the high power domain of access When between twice of pressure voltage and the corresponding device pressure voltage, the signal of the low power domain of input is respectively converted into the height The supply voltage and low-voltage of power domain.

In an embodiment of the present invention, the low-voltage level conversion circuit 11 (does not show including the first input unit in figure Go out), low-pressure passage (not shown) and the first output unit (not shown), wherein：

First input unit is suitable for being less than or equal to corresponding device in the supply voltage of the high power domain of input resistance to When pressure value, the voltage signal of the low power domain received is converted into corresponding differential signal.

The low-pressure passage, the differential signal suitable for first input unit to be converted to are exported to described first defeated Go out unit.

First output unit, the differential signal suitable for exporting the low-pressure passage are converted to complementary high power domain Supply voltage and no-voltage.

In an embodiment of the present invention, the high-voltage level conversion circuit 12 (does not show including the second input unit in figure Go out), high-pressure passage (not shown) and the second output unit (not shown), wherein：

Second input unit is suitable for being more than corresponding device pressure voltage in the supply voltage of the high power domain of input When, the voltage signal of the low power domain received is converted into corresponding differential signal；

The low-pressure passage, the differential signal suitable for second input unit to be converted to are exported to described second defeated Go out unit；

Second output unit, the differential signal suitable for exporting the low-pressure passage are converted to complementary high power domain Supply voltage and low-voltage.

It is further described in detail below in conjunction with the level shifting circuit in Fig. 2 to the 4 pairs of embodiment of the present invention.

In order to make it easy to understand, will turn respectively to the low voltage level in the level shifting circuit in the embodiment of the present invention below It changes circuit and high-voltage level conversion circuit is described in detail respectively.

Referring to Fig. 2, the low-voltage level conversion circuit in the embodiment of the present invention may include by the first PMOS tube MP1, The first input unit that one NMOS tube MN1, the second NMOS tube MN2 and third NMOS tube MN3 are constituted, by the 4th NMOS tube MN4, the The low-pressure passage that five NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 are constituted, and by the 4th PMOS tube MP4, the Five PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS The first output unit that pipe MP10 and the 11st PMOS tube MP11 are constituted.

In specific implementation, by the first PMOS tube MP1, the first NMOS tube MN1, the second NMOS tube MN2 and third NMOS tube In the first input unit that MN3 is constituted：

The grid end of first PMOS tube MP1 is coupled with input signal VIN, the source and low supply voltage of the first PMOS tube MP1 The drain terminal of the signal VDDL couplings of domain voltage, the drain terminal of the first PMOS tube MP1 and the first NMOS tube MN1 couple；First NMOS tube The source of MN1 is coupled with ground wire GND, the grid of the grid end of the second NMOS tube MN2 and the first PMOS tube MP1 and the first NMOS tube MN1 End coupling；The drain terminal of second NMOS tube MN2 is coupled with first voltage node VOLB, source and the ground wire GND of the second NMOS tube MN2 Coupling；The grid end of third NMOS tube MN3 and the drain terminal of the first PMOS tube MP1 and the first NMOS tube MN1 couple, third NMOS tube The drain terminal of MN3 is coupled with second voltage node VOL, and source and the ground wire GND of third NMOS tube MN3 are coupled.

In specific implementation, by the 4th NMOS tube MN4, the 6th NMOS tube MN6, the 5th NMOS tube MN5 and the 7th NMOS tube In the low-pressure passage that MN7 is constituted：

The grid end of 4th NMOS tube MN4 is coupled with tertiary voltage node VSW, the drain terminal and the 5th of the 4th NMOS tube MN4 The source of NMOS tube MN5 couples, and the source of the 4th NMOS tube MN4 is coupled with the first voltage node VOLB；5th NMOS tube The grid end of MN5 is coupled with the 4th voltage node VBN, and the drain terminal of the 5th NMOS tube MN5 and the 5th voltage node X are coupled, and the 5th The source of NMOS tube and the drain terminal of the 4th NMOS tube MN4 couple；The grid end of 6th NMOS tube MN6 and tertiary voltage node VSW couplings It connects, the drain terminal of the 6th NMOS tube MN6 and the source of the 7th NMOS tube MN7 couple, the source and second voltage of the 6th NMOS tube MN6 Node VOL couplings；The grid end of 7th NMOS tube MN7 is coupled with the 4th voltage node VBN, the drain terminal of the 7th NMOS tube MN7 and the Six voltage node Y couplings, the source of the 7th NMOS tube MN7 are coupled with the drain terminal of the 6th NMOS tube MN6.

In specific implementation, by the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10 and the 11st PMOS tube MP11 are constituted first defeated Go out in unit：

The grid end of the 4th PMOS tube MP4 is coupled with the 7th voltage node VBP, the source of the 4th PMOS tube MP4 It is coupled with the drain terminal of the 6th PMOS tube MP6；The grid end of the 5th PMOS tube MP5 and the 7th voltage node VBP couplings Connect, the drain terminal of the 5th PMOS tube MP5 and the 5th voltage node X are coupled, the source of the 5th PMOS tube MP5 with it is pre- If negative output voltage node VOHB coupling；The grid end of the 6th PMOS tube MP6 and the positive output voltage node VOH couplings It connects, the source of the 6th PMOS tube MP6 is coupled with the supply voltage VDDH of the high power domain；The 7th PMOS tube MP7 Grid end and the supply voltage VDDH of source and the high power domain couple, the drain terminal of the 7th PMOS tube MP7 with it is described just Output voltage node VOH couplings；The grid end of the 8th PMOS tube MP8 is coupled with the 7th voltage node VBP, and the described 8th The drain terminal of the source of PMOS tube MP8 and the tenth PMOS tube MP10 couple, the drain terminal of the 8th PMOS tube MP8 and described the Six voltage node Y couplings；The grid end of the 9th PMOS tube MP9 is coupled with the 7th voltage node VBP, the 9th PMOS The drain terminal of pipe MP9 is coupled with the 6th voltage node Y, the source of the 9th PMOS tube MP9 and the 6th PMOS tube MP6 Grid end and the 7th PMOS tube MP7 drain terminal coupling；The grid end of the tenth PMOS tube MP10 and the negative output voltage Node VOHB couplings, the source of the tenth PMOS tube MP10 are coupled with the supply voltage VDDH of the high power domain；Described The grid end and source of 11 PMOS tube MP11 and the supply voltage VDDH of the high power domain are coupled, the 11st PMOS The drain terminal of MP11 pipes is coupled with the negative output voltage node VOHB.

In specific implementation, when the supply voltage of the high power domain of access is less than or equal to corresponding device pressure voltage, The tertiary voltage node VSW and the signal VDDL of the low power domain are coupled；The 4th voltage node VBN and the high electricity The supply voltage VDDH couplings of source domain；The 7th voltage node VBP is coupled with preset no-voltage.

In specific implementation, when the supply voltage VDDH of high power domain is less than or equal to the first PMOS tube PM1 to the 11st When the device pressure voltage of PMOS tube PM11 and the first NMOS tube MN1 to the 11st NMOS tube MN11, tertiary voltage node VSW and 4th voltage node VBN is coupled with high power supply voltage VDDH, and the 7th voltage node VBP is coupled with no-voltage.

At this point, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 8th PMOS tube MP8, the 9th PMOS tube MP9 and the 4th The NMOS tube MN7 of NMOS tube MN4~the 7th will always be in the state of conducting so that level shifting circuit shown in Fig. 2 and Fig. 3 institutes The circuit shown, as existing low voltage level conversion circuit.

The operation principle of low transition circuit is described in detail first below in conjunction with Fig. 3.

Referring to Fig. 3, when the supply voltage VDDH of high power domain is less than or equal to device pressure voltage, the 4th NMOS tube MN4 With the grid end of the 6th NMOS tube MN6, i.e. tertiary voltage node VSW and the signal VDDL of low power domain are coupled, in low-pressure passage The switch subelement that 4th NMOS tube MN4 and the 6th NMOS tube MN6 are constituted is opened so that low-pressure passage is opened；When high power domain Supply voltage VDDH be more than device pressure resistance when, the grid end of the 4th NMOS tube MN4 and the 6th NMOS tube MN6, i.e. tertiary voltage section Point VSW ground connection, at this time low-pressure passage shutdown.

The first PMOS tube MP1 and the first NMOS tube MN1 in first input unit form phase inverter, as input signal VIN When by signal VDDL that Zero voltage transition is low power domain, the second NMOS tube MN2 switchs to be connected by ending, input signal VIN warp Zero level signal is converted to after phase inverter so that third NMOS tube MN3 switchs to end by being connected.

Wherein, the grid end of the tenth PMOS tube MP10 is pulled down to no-voltage, i.e., the first electricity by the conducting of the second NMOS tube MN2 It is no-voltage to press node VOLB.When first voltage node VOLB is no-voltage so that the tenth PMOS tube MP10 conductings, and third The grid end voltage of 6th PMOS tube MP6 is pulled up the supply voltage of supreme power domain by NMOS tube MN3 cut-offs, the tenth PMOS tube MP10 VDDH, the i.e. voltage of second voltage node VOL are the supply voltage VDDH of high power domain.When the voltage of second voltage node VOL For high power supply voltage VDDH when, the 6th PMOS tube MP6 cut-off.

So far, complete once by input signal VIN by no-voltage to low power domain signal VDDL conversion, at this point, defeated Go out the supply voltage VDDH that first voltage node VOL is equal to high power domain, second voltage node VOLB is equal to no-voltage.

With continued reference to Fig. 3, when input signal VIN becomes no-voltage from the signal VDDL of low power domain so that second NMOS tube MN2 ends, and the signal VDDL of low power domain is converted to after the inverted device of no-voltage so that the MN3 conductings of third NMOS tube. At this point, the grid end of the 6th PMOS tube MP6 is pulled down to no-voltage by third NMOS tube MN3, i.e. first voltage node VOL is zero electricity Pressure.Meanwhile when first voltage node VOL is no-voltage, the 6th PMOS tube MP6 conductings, and the second NMOS tube NM2 cut-offs, the The grid end voltage of tenth PMOS tube is pulled upward to the supply voltage VDDH of high power domain, i.e. second voltage node by six PMOS tube MP6 VOLB is equal to the supply voltage VDDH of high power domain.When second voltage node VOLB is equal to the supply voltage VDDH of high power domain When, the tenth PMOS tube MP10 cut-offs.An input signal VIN is thus completed by the signal VDDL of low power domain to no-voltage Conversion, at this point, output first voltage node VOL=0, second voltage node VOLB=VDDH.

Pass through above-mentioned operation, you can be less than or equal to device pressure voltage in the voltage of the supply voltage VDDH of high power domain When, complete the level conversion of supply voltage VDDHs of the input signal VIN from the signal VDDL of low power domain to high power domain.

In above-mentioned operating process, the first pressure resistance being made of the 5th NMOS tube MN5 and the 7th NMOS tube MN7 is single Member, for doing pressure-resistant treatments.Specifically, when the supply voltage VDDH of high power domain is less than or equal to device pressure resistance, the 5th The grid end namely the 4th voltage node VBN of NMOS tube and the 7th NMOS tube and the supply voltage VDDH of high power domain are coupled so that 5th NMOS tube MN5 and the 7th NMOS tube MN7 are in the conduction state.

When the supply voltage VDDH of high power supply is more than device pressure resistance, the grid of the 5th NMOS tube MN5 and the 7th NMOS tube MN7 End, i.e., the 4th voltage node VBN meets preset 2/3VDDH, their source voltage terminal is up to 2/3VDDH-VTH at this time so that The source-drain voltage VDS of 4th NMOS tube MN4 and the 6th NMOS tube MN6 and the second NMOS tube MN2 in input unit and third The source-drain voltage VDS of NMOS tube MN3 is no more than corresponding device pressure voltage, to the 4th NMOS tube MN4, the 6th NMOS tube MN6 and the second NMOS tube MN2 in input unit and the pressure-resistant protection of third NMOS tube MN3 progress.

The high power level conversion circuit in the embodiment of the present invention will be described in detail below.

With continued reference to Fig. 2, the second input unit in high-voltage level conversion circuit may include the first PMOS tube MP1, The first NMOS tube MN1, the second NMOS tube MN2 and the third NMOS tube MN3；High-pressure passage may include the 8th NMOS tube MN8 and the tenth NMOS tube MN10, the 9th NMOS tube MN9, the 11st NMOS tube MN11, the second PMOS tube MP2 and third PMOS tube MP3；Second output unit may include the 4th PMOS tube MP4, the 5th PMOS tube MP5, the described 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10 and the 11st PMOS tube MP11；Wherein：

In specific implementation, by the first PMOS tube MP1, the first NMOS tube MN1, the second NMOS tube MN2 and In the second input unit that the third NMOS tube MN3 is constituted：

The grid end of first PMOS tube MP1 and the grid end of the first NMOS tube MN1 couple, and the input terminal of input signal VIN, the The source of one PMOS tube MP1 and the signal VDDL of low power domain are coupled, the drain terminal of the first PMOS tube MP1 and the first NMOS tube MN1 Drain terminal coupling；The source of first NMOS tube MN1 is coupled with ground wire GND, grid end and the first PMOS tube of the second NMOS tube MN2 The grid end of MP1 and the first NMOS tube MN1 couple；The drain terminal of second NMOS tube MN2 is coupled with first voltage node VOLB, and second The source of NMOS tube is coupled with ground wire GND；The leakage of the grid end of third NMOS tube and the first PMOS tube MP1 and the first NMOS tube MN1 End coupling, drain terminal and the second voltage node VOL of third NMOS tube MN3 are coupled, source and the ground wire GND of third NMOS tube MN3 Coupling.

In specific implementation, by the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st What the first output unit that NMOS tube MN11, the second PMOS tube MP2, third PMOS tube MP3 and the 4th PMOS tube MP4 are constituted was constituted In high-pressure passage：

The grid end of 8th NMOS tube MN8 is coupled with the 4th voltage node VBN, the drain terminal and the 9th of the 8th NMOS tube MN8 The source of NMOS tube MN9 and the coupling of the grid end of the second PMOS tube MP2, the source and first voltage node of the 8th NMOS tube MN8 VOLB is coupled；The grid end of 9th NMOS tube MN9 and the second PMOS tube MP2 sources and the 5th voltage node X couplings, the 9th NMOS tube The drain terminal of the drain terminal of MN9 and the second PMOS tube MP2 couple, the source of the 9th NMOS tube MN9 and the drain terminal of the 8th NMOS tube MN8 and The grid end of second PMOS tube MP2 couples；The grid end of second PMOS tube MP2 and the drain terminal and the 9th NMOS tube of the 8th NMOS tube MN8 The source of MN9 couples, the drain terminal coupling of the drain terminal and the 9th NMOS tube MN9 of the second PMOS tube MP2, the source of the second PMOS tube MP2 The grid end and the 5th voltage node X couplings of end and the 9th NMOS tube MN9；The grid end MN10 and the 4th voltage node of tenth NMOS tube VBN is coupled, the grid end coupling of the drain terminal of the tenth NMOS tube MN10 and the source of the 11st NMOS tube MN11 and third PMOS tube MP3 It connects, the source of the tenth NMOS tube MN10 and the VOL couplings of second voltage node；The grid end and the 3rd PMOS of 11st NMOS tube MN11 Pipe MP3 sources and the 6th voltage node Y couplings, the drain terminal coupling of the drain terminal and third PMOS tube MP3 of the 11st NMOS tube MN11, The source of 11st NMOS tube MN11 and the coupling of the grid end of the drain terminal of the tenth NMOS tube MN10 and third PMOS tube MP3；Third The source of the drain terminal and the 11st NMOS tube MN11 of the grid end of PMOS tube MP3 and the tenth NMOS tube MN10 couples, third PMOS tube The drain terminal of the drain terminal of MP3 and the 11st NMOS tube MN11 couple, the source of third PMOS tube MP3 and the 11st NMOS tube MN11's Grid end and the 6th voltage node Y couplings.

In specific implementation, by the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the tenth PMOS tube MP10 and In the second output unit that 11 PMOS tube MP11 are constituted：

In specific implementation, when the voltage of the supply voltage VDDH of high power domain is more than the first PMOS tube PM1 to the 11st The pressure voltage of the device pressure voltage of PMOS tube MP11 and the first NMOS tube MN1 to the 11st NMOS tube MN11, and it is less than first The device of the device pressure voltage and the first NMOS tube MN1 to the 11st NMOS tube MN11 of PMOS tube PM1 to the 11st PMOS tube M1 At twice of pressure voltage, tertiary voltage node VSW and no-voltage are coupled, by the electricity that the 4th voltage node VBN is high power domain 2/3 coupling of source voltage VDDH, and the 1/3 of the 7th voltage node VBP and supply voltage VDDH of high power domain is coupled.This When, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 8th PMOS tube MP8 and the 9th PMOS tube MP9 will be in the shape of conducting State, the 4th NMOS tube MN4 will be completely in the state of cut-off to the 7th NMOS tube MN7.So, level conversion electricity shown in Fig. 2 Road will be equivalent to circuit shown in Fig. 4.

Referring to Fig. 4, when the supply voltage VDDH of high power domain is more than device pressure voltage, the 4th PMOS tube MP4, the 8th The grid end of PMOS tube MP8, the 5th PMOS tube MP5 and the 9th PMOS tube MP9, i.e. the 7th voltage node VBP connect preset 1/3 height The supply voltage VDDH of power domain so that four PMOS tube MP4, the 8th PMOS tube MP8, the 5th PMOS tube MP5 and the 9th PMOS tube The source voltage terminal of MP9 minimum 1/3VDDH+VTH at this time, and then can make the 6th PMOS tube MP6 and the tenth PMOS tube MP10 Source-drain voltage VDS be no more than corresponding device pressure voltage.

6th PMOS tube MP6, the 4th PMOS tube MP4, the 5th PMOS tube MP5 and the tenth PMOS tube MP10, the 8th PMOS tube This cross-connection system of MP8, the 9th PMOS tube MP9 constitutes positive feedback so that the 5th voltage node X and the 6th when stable state exports Voltage node Y is complementary voltage signal, to ensure the voltage and negative output voltage node VOHB of positive output voltage node VOH Voltage is the voltage signal of complementation.Meanwhile the 5th PMOS tube MP5 and the 9th PMOS tube MP9 when level translation is initial in weak Conducting state weakens the 6th PMOS tube MP6, the 4th PMOS tube MP4, the 5th PMOS tube MP5 and the tenth PMOS tube MP10, the 8th Mutual coupling between PMOS tube MP8, the 5th PMOS tube MP5, to improve the speed of level conversion.

When input signal VIN becomes the signal VDDL of low power domain from no-voltage so that the second NMOS tube MN2 conductings, The signal VDDL of low power domain exports zero voltage signal after phase inverter carries out reverse phase, in the output end of phase inverter, to make Obtain the MN3 cut-offs of third NMOS tube.

When the second NMOS tube MN2 conductings and the MN3 cut-offs of third NMOS tube, first voltage node VOLB and the 5th voltage section The level of point X will be pulled down to low level by the second NMOS tube MN2, so that the tenth PMOS tube MP10 conductings, at this point, first Voltage node VOLB is no-voltage；The level of 5th voltage node X is the VTH of the 9th NMOS tube MN9 or the second PMOS tube MP2； Negative output voltage node VOHB is that the voltage of the 7th voltage node VBP adds the threshold V T H of the 5th PMOS tube, is equal to 1/ 3VDDH+VTH.Meanwhile the voltage of second node voltage VOL and the 6th voltage node Y pull up supreme electricity by the tenth PMOS tube MP10 It is flat, make the 6th PMOS tube MP6 cut-offs.At this point, the voltage of second voltage node VOL is the threshold value that VBN subtracts the 9th NMOS tube MN9 Voltage VTH is equal to 2/3VDDH-VTH；The grid end voltage of 6th PMOS tube MP6, the i.e. voltage of positive output node VOH are equal to high electricity The supply voltage VDDH of source domain.

The above process, complete an input signal VIN by no-voltage to low power domain signal VDDL conversion, at this point, Export the voltage VOH=VDDH of positive output voltage node, the voltage VOHB=1/3VDDH+VTH of negative output voltage node, second The voltage VOL=2/3VDDH-VTH of voltage node, the voltage VOLB=0 of first voltage node.

When input signal VIN becomes no-voltage from the signal VDDL of low power domain, the second NMOS tube MN2 cut-offs, zero electricity Pressure exports the signal VDDL of low power domain, so that third NMOS tube MN3 is led after phase inverter carries out reverse phase in output end It is logical.

When the second NMOS tube MN2 cut-offs and the MN3 conductings of third NMOS tube, second voltage node VOL and the 6th voltage section The level of point Y will be pulled down to low level by third NMOS tube MN3, so that the 6th PMOS tube MP6 conductings, at this point, second Voltage node VOL is no-voltage；The level of 6th voltage node Y is the threshold voltage of the 11st NMOS tube or third PMOS tube VTH；The grid end voltage of 6th PMOS tube, i.e. the voltage VOH of positive voltage output end are that the 7th node voltage VBP adds the 9th PMOS The threshold V T H of pipe MP9 is equal to 1/3VDDH+VTH.

Meanwhile first voltage node VOLB and the 5th voltage node X are pulled to high level by the 6th PMOS tube MP6, make Ten PMOS tube MP10 cut-offs.At this point, the voltage VBN that first voltage node VOLB is the 4th voltage node subtracts the 8th NMOS tube The threshold V T H of MN8 is equal to 2/3VDDH-VTH；The grid end voltage of tenth PMOS tube MP10, i.e. negative output voltage node Voltage VOHB is equal to VDDH.So far, complete an input signal VIN by low power domain signal VDDL to no-voltage conversion, At this point, voltage VOH=1/3VDDH+VTH, the voltage VOHB=VDDH of negative output voltage node of output positive output voltage node, The voltage VOL=0 of second voltage node, the voltage VOLB=2/3VDDH-VTH of first voltage node.

By operating twice above, that is, complete when the voltage of high power supply voltage VDDH is more than device pressure resistance and is less than two When times device pressure resistance, signal is from low supply voltage VDDL to the level conversion of high power supply voltage VDDH.

In the above-mentioned course of work of high-voltage level conversion circuit, when high power supply voltage VDDH is more than device pressure voltage When, the 8th NMOS tube and the tenth NMOS tube constitute the second pressure-resistant subelement, when the 8th NMOS tube MN8's and the tenth NMOS tube MN10 Grid end, i.e. the 4th voltage node VBN connect the supply voltage VDDH coupling of preset 2/3 high power domain, the 8th NMOS tube MN8 and Tenth NMOS tube MN10 source voltage terminals are up at this time 2/3VDDH-VTH, so that the 2nd NMOS in the second input unit The source voltage terminal VDS voltages of pipe MN2 and third NMOS tube MN3 are no more than corresponding device pressure voltage, so as to defeated to second The the second NMOS tube MN2 and third NMOS tube MN3 entered in unit carries out pressure-resistant protection.9th NMOS tube MN9 and the second PMOS tube MP2 and the 11st NMOS tube MN11 and third PMOS tube MP3 separately constitute two diode clamp subelements, for preventing defeated Enter signal VIN in the handoff procedure of no-voltage and the signal VDDL of low power domain, the 5th voltage node X and the 6th voltage node The damage for momentary spike voltage pair the 8th the NMOS tube MN8 and the tenth NMOS tube MN10 that Y occurs.

In specific implementation, the 5th PMOS tube MP5 and the 9th PMOS tube MP9 is in weak conducting shape when level translation is initial State weakens the 6th PMOS tube MP6, the 4th PMOS tube MP4, the 5th PMOS tube MP5 and the tenth PMOS tube MP10, the 8th PMOS tube This cross-connection system of MP8, the 5th PMOS tube MP5 constitutes positive feedback, improves the speed of level conversion.

Using the said program in the embodiment of the present invention, electricity is converted by low-voltage level conversion circuit and high-voltage level The setting on road, can be when the supply voltage of the high power domain of access be less than or equal to device pressure voltage, by the low power supply of input The signal in domain is converted to the supply voltage or no-voltage of the high power domain, and can be in the electricity of the high power domain of access When source voltage is located between twice of corresponding device pressure voltage and the corresponding device pressure voltage, by the low power supply of the input The signal in domain is respectively converted into the supply voltage and low-voltage of the high power domain, and the level that can be compatible with high low supply voltage turns It changes, to expand the scope of application of level shifting circuit.

The method and system of the embodiment of the present invention are had been described in detail above, the present invention is not limited thereto.Any Field technology personnel can make various changes or modifications without departing from the spirit and scope of the present invention, therefore, of the invention Protection domain should be subject to claim limited range.

Claims

1. a kind of level shifting circuit, which is characterized in that including：

Low-voltage level conversion circuit is suitable for being less than or equal to the pressure resistance of corresponding device in the supply voltage of the high power domain of access When value, the signal of the low voltage domain of input is respectively converted into the supply voltage and no-voltage of corresponding high power domain；

High-voltage level conversion circuit is suitable for being located at the corresponding device pressure voltage in the supply voltage of the high power domain of access When between twice of the corresponding device pressure voltage, the signal of the low power domain of input is respectively converted into the high power domain Supply voltage and low-voltage.

2. level shifting circuit according to claim 1, which is characterized in that the low-voltage level conversion circuit includes the One input unit, low-pressure passage and the first output unit；

First input unit is suitable for being less than or equal to corresponding device pressure voltage in the supply voltage of the high power domain of input When, the signal of the low power domain received is converted into corresponding differential signal；

The low-pressure passage, the differential signal suitable for first input unit to be converted to export single to first output Member；

First output unit, the differential signal suitable for exporting the low-pressure passage are converted to the electricity of complementary high power domain Source voltage and no-voltage.

3. level shifting circuit according to claim 2, which is characterized in that first input unit includes the first PMOS Pipe, the first NMOS tube, the second NMOS tube and third NMOS tube；

The grid end of first PMOS tube and the grid end of first NMOS tube couple, and as the signal of preset low power domain Input terminal, the signal of the source of first PMOS tube and the low power domain couples, the drain terminal of first PMOS tube with The drain terminal of first NMOS tube couples, and source and the ground wire of first NMOS tube couple；

The grid end of second NMOS tube is coupled with the grid end of first PMOS tube and first NMOS tube, and described second The drain terminal of NMOS tube is coupled with first voltage node, and source and the ground wire of second NMOS tube couple；

The grid end of the third NMOS tube is coupled with the drain terminal of first PMOS tube and first NMOS tube, the third The drain terminal of NMOS tube is coupled with second voltage node, and source and the ground wire of the third NMOS tube couple.

4. level shifting circuit according to claim 3, which is characterized in that the low-pressure passage include switch subelement and First pressure-resistant subelement；

The switch subelement includes the 4th NMOS tube and the 6th NMOS tube；Described first pressure-resistant subelement includes the 5th NMOS tube With the 7th NMOS tube；

The grid end of 4th NMOS tube is coupled with tertiary voltage node, drain terminal and the 5th NMOS of the 4th NMOS tube The source of pipe couples, and source and the first voltage node of the 4th NMOS tube couple；

The grid end of 5th NMOS tube and the grid end of the 7th NMOS tube are coupled with the 4th voltage node, the 5th NMOS The drain terminal of pipe and the 5th voltage node couple, and the source of the 5th NMOS tube is coupled with the drain terminal of the 4th NMOS tube；

The grid end of 6th NMOS tube is coupled with tertiary voltage node, drain terminal and the 7th NMOS of the 6th NMOS tube The source of pipe couples, and source and the second voltage node of the 6th NMOS tube couple；

The drain terminal of 7th NMOS tube and the 6th voltage node couple, source and the 6th NMOS of the 7th NMOS tube The drain terminal of pipe couples.

5. level shifting circuit according to claim 4, which is characterized in that first output unit includes：4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, the tenth PMOS tube and 11 PMOS tube；

The grid end of 4th PMOS tube is coupled with the 7th voltage node, source and the 6th PMOS of the 4th PMOS tube The drain terminal of pipe couples；

The grid end of 5th PMOS tube is coupled with the 7th voltage node, the drain terminal and the described 5th of the 5th PMOS tube Voltage node couples, and source and the preset positive output voltage node of the 5th PMOS tube couple；

The grid end of 6th PMOS tube is coupled with the positive output voltage node, source and the height of the 6th PMOS tube The supply voltage of power domain couples；

The grid end and source of 7th PMOS tube are coupled with the supply voltage of the high power domain, the leakage of the 7th PMOS tube End is coupled with the positive output voltage node；

The grid end of 8th PMOS tube and the 7th voltage node VBP are coupled, the source of the 8th PMOS tube with it is described The drain terminal of tenth PMOS tube couples, and drain terminal and the 6th voltage node of the 8th PMOS tube couple；

The grid end of 9th PMOS tube is coupled with the 7th voltage node, the drain terminal and the described 6th of the 9th PMOS tube Voltage node couples, the source and the grid end of the 6th PMOS tube and the drain terminal of the 7th PMOS tube of the 9th PMOS tube Coupling；

The grid end of tenth PMOS tube is coupled with negative output voltage node, source and the high power supply of the tenth PMOS tube The supply voltage in domain couples；

The grid end and source of 11st PMOS tube are coupled with the power voltage terminal of the high power domain, the 11st PMOS The drain terminal of pipe is coupled with the negative output voltage node.

6. level shifting circuit according to claim 5, which is characterized in that the tertiary voltage node and the low power supply The signal in domain couples；4th voltage node and the supply voltage of the high power domain couple；7th voltage node with Preset no-voltage coupling.

7. level shifting circuit according to claim 6, which is characterized in that the high-voltage level conversion circuit includes the Two input units, high-pressure passage and the second output unit；

Second input unit is suitable for when the supply voltage of the high power domain of input is more than corresponding device pressure voltage, will The signal of the low power domain received is converted to corresponding differential signal；

The low-pressure passage, the differential signal suitable for second input unit to be converted to export single to second output Member；

Second output unit, the differential signal suitable for exporting the low-pressure passage are converted to complementary high power supply voltage domain electricity Pressure and low-voltage.

8. level shifting circuit according to claim 7, which is characterized in that second input unit includes described first PMOS tube, first NMOS tube, second NMOS tube and the third NMOS tube；

The grid end of first PMOS tube and the input terminal of the input signal couple, the source of first PMOS tube with it is described The signal of low power domain couples, and the drain terminal of first PMOS tube and the drain terminal of first NMOS tube couple；

The source of first NMOS tube is coupled with ground wire, the grid end of second NMOS tube and first PMOS tube and described The grid end of first NMOS tube couples, and drain terminal and the first voltage node of second NMOS tube couple, second NMOS tube Source is coupled with ground wire, the drain terminal coupling of the grid end of the third NMOS tube and first PMOS tube and first NMOS tube It connects, drain terminal and the second voltage node of the third NMOS tube couple, and source and the ground wire of the third NMOS tube couple.

9. level shifting circuit according to claim 8, which is characterized in that the high-pressure passage includes be mutually coupled Two pressure-resistant subelements and diode clamp subelement；

Described second pressure-resistant subelement includes the 8th NMOS tube and the tenth NMOS tube；The diode clamp subelement includes the 9th NMOS tube, the 11st NMOS tube, the second PMOS tube and third PMOS tube；

The grid end of 8th NMOS tube is coupled with the 4th voltage node, the drain terminal and described second of the 8th NMOS tube The grid end of PMOS tube couples, source and first voltage the node coupling of the 8th NMOS tube；

The grid end of 9th NMOS tube is coupled with the 5th voltage node, the drain terminal and described second of the 9th NMOS tube The drain terminal of PMOS tube couples, and the source of the 9th NMOS tube is coupled with the drain terminal of the 8th NMOS tube；2nd PMOS The source of pipe is coupled with the 5th voltage node；

The grid end of tenth NMOS tube and the coupling of the 4th voltage node, drain terminal and the 3rd PMOS of the tenth NMOS tube The grid end of pipe couples, and source and the second voltage node of the tenth NMOS tube couple；

The grid end of 11st NMOS tube is coupled with the 6th voltage node, the drain terminal of the 11st NMOS tube with it is described The drain terminal of third PMOS tube couples, and the source of the 11st NMOS tube is coupled with the grid end of third PMOS tube；The third The grid end and the coupling of the 6th voltage node of the source of PMOS tube and the 11st NMOS tube.

10. level shifting circuit according to claim 9, which is characterized in that second output unit includes phase mutual coupling Subelement and complementary signal output subelement are eliminated in the mutual coupling connect；

It includes the 5th PMOS tube and the 9th PMOS tube that subelement is eliminated in the mutual coupling；Complementary signal output is single Member includes the 4th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the tenth PMOS tube With the 11st PMOS tube；

The grid end of tenth PMOS tube is coupled with the negative output voltage node, source and the height of the tenth PMOS tube The supply voltage of power domain couples；

11. level shifting circuit according to claim 10, which is characterized in that the tertiary voltage node and ground wire coupling It connects；4th voltage node and 2/3 the high power domain supply voltage couple；5th voltage node and coupling； 7th voltage node and 1/3 the high power domain supply voltage couple.