CN108508959B - LDO (low dropout regulator) based on cascode voltage flip follower structure - Google Patents
LDO (low dropout regulator) based on cascode voltage flip follower structure Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to an LDO (low dropout regulator) based on a cascode voltage flip follower structure. By adding a transconductance current enhancement circuit, a static current branch circuit and a quick response loop on the basis of a conventional cascode voltage flip follower structure, the transient response speed of the LDO is effectively improved under the condition of equal power consumption, the input voltage is changed between 1.8V and 3.3V, the output voltage is stabilized at 1.6V, the load capacitance is changed in a sampling period, the load transient response time of the system is only about 177ns, the static current of the system is 104.1uA, and the load capacity of 0mA-1mA is possessed. The LDO provided by the invention effectively improves the transient response speed of the LDO, meets the performance requirement of the Sigma-delta modulator, and has the advantages that the performance reliability is proved through performance simulation, and the LDO has a huge application space in the audio Sigma-delta modulator.
Description
Technical Field
The invention is used in an audio Sigma-delta modulator, and particularly relates to an LDO (low dropout regulator) based on a cascode voltage flip follower structure.
Background
In recent years, with the rapid development of electronic technology and integrated circuit systems, particularly the continuous popularization of portable and consumer electronics in the internet era, power management chips have been playing an increasing role in various fields such as automobiles, medical treatment, mobile communication, computer networks, and infrastructure. The power management chip is used as a bridge between the battery and the electronic equipment, plays roles of distributing, managing and stabilizing power, and the performance of the power management chip determines the overall performance of the electronic equipment to a great extent. With the continued innovation and development of integrated circuit processes. As one of the power management chips, a low dropout linear regulator (Low Dropout Regulator, LDO for short) is used, and its demand is gradually expanding. Under the large environment background of intelligent life and energy conservation and environmental protection, the LDO chip gradually develops to high performance such as low power consumption, high precision, quick response, low cost and the like besides the basic requirements of stability and reliability.
The conventional LDO uses a voltage-inverting follower structure as a control loop, and the main disadvantage of the structure is that the requirement of load current is not suitable for no-load conditions. When the load current is smaller than a certain value, the voltage at the gate end of the power tube is increased, so that the control tube enters a linear region, the LDO loses the capability of regulating the output voltage, and the output voltage is changed. On the basis of the voltage overturn follower structure, the common-source common-gate voltage overturn follower structure is an improved version of the voltage overturn follower structure. Compared with the voltage flip follower structure, the cascode voltage flip follower structure is added with a transistor with a common grid structure, and the addition of the transistor improves the gain of a feedback loop and improves the load adjustment rate of the LDO. However, the gate end of the power tube with the structure is still a high-resistance node, the gate end is still a lower frequency pole, the loop bandwidth is limited, and the transient response speed of the system is limited.
The invention provides a novel quick response LDO based on a cascode voltage flip follower structure, which has a clear and simple circuit structure, and can start a quick loop under high-frequency change to accelerate the transient response speed of the LDO.
Disclosure of Invention
The invention aims to provide an LDO based on a cascode voltage flip follower structure, which effectively improves the transient response speed of the LDO, meets the performance requirement of a Sigma-delta modulator, proves the reliability of the performance of the Sigma-delta modulator through performance simulation, and has huge application space in an audio Sigma-delta modulator.
In order to achieve the above purpose, the technical scheme of the invention is as follows: an LDO based on a cascode voltage flip follower structure comprises MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10 and M P 、M N First to fourth current sources, first end of M1 and first end of M5, M P A first end of M8, a first end of M9, a first end of M10 are connected to VDD, a second end of M1 is connected to a control end of M6, a first end of M2, a control end of M1 is connected to a control end of M5, a control end of M9, a control end of M10, a second end of M7, a second end of M2 is connected to a control end of M2, a control end of M3, and connected to GND via a first current source, a first end of M3 is connected to M P Second end of M N Is connected as the output end of the LDO circuit, and the second end of M3 is connected with M N Is connected to the control end of M4 and is connected to GND via a second current source and a third current source, the second end of M4 is connected to the second end of M5, M P The control end of M4 is used as the bias voltage input end of the LDO circuit, the first end of M6 is connected with the first end of M7, and is connected with M via a fourth current source N Is connected to GND, the second end of M6 is connected to the second end of M8, the control end of M8, the second end of M9The control end of M7 is connected to a reference voltage source.
In an embodiment of the present invention, M6, M7, M8, M9, M10 and the fourth current source form a transconductance amplifier, wherein M8, M9, M10 form a transconductance current enhancing circuit.
In one embodiment of the present invention, the aspect ratio of M8, M9, M10 is: 1: n: n+1, assuming that the magnitudes of the currents flowing through M6 and M7 are I, the current ratios flowing through M8, M9, and M10 are: i [1/n+1]: i [ n/n+1]: i, a step of I; when the load changes, the output voltage will generate downward overshoot when the load suddenly changes from light load to heavy load, so the output voltage of the output end of the LDO circuit suddenly decreases, the voltage at the control end of M6 suddenly decreases, and the transconductance of the transconductance amplifier is enhanced by n+1 times compared with that of the transconductance amplifier without increasing the transconductance current enhancement circuit, assuming that the current of M6 decreases to be half of the original current, namely 0.5I, the current of M7 becomes 1.5I, and the current flowing through M8 increases to be 0.5I (1/n+1); similarly, when the load is suddenly changed from heavy load to light load, the transconductance is enhanced by n+1 times.
In one embodiment of the invention, M P The LDO circuit is a power tube.
In one embodiment of the invention, M3, M4, M P The cascode voltage flip-flop structure is formed.
In an embodiment of the present invention, the fast response loop further includes a first to seventh MOS transistors, a fifth current source, and a capacitor C1, wherein the first end of the first MOS transistor is connected to VDD with the first end of the second MOS transistor and the first end of the third MOS transistor, the second end of the first MOS transistor is connected to the second end of the fourth MOS transistor, the control end of the fourth MOS transistor, and the control end of the fifth MOS transistor, the control end of the first MOS transistor is connected to the control end of the second MOS transistor and the control end of the third MOS transistor, and the second end of the second MOS transistor is connected to M with the second end of the fifth MOS transistor P The second end of the third MOS tube is connected to GND through a fifth current source, the first end of the fourth MOS tube is connected with the second end of the sixth MOS tube, the control end of the sixth MOS tube and the control end of the seventh MOS tube, and the first end of the fifth MOS tube is connected with the second end of the seventh MOS tube and connected to M through C1 P Is the second one of (2)And the first end of the sixth MOS tube and the first end of the seventh MOS tube are connected to GND.
In an embodiment of the invention, a bias circuit for providing bias voltage and bias current for the LDO circuit is further included.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, a transconductance current enhanced circuit, a static current branch circuit and a quick response loop are added on the basis of a conventional cascode voltage flip follower structure, so that the transient response speed of the LDO is effectively improved under the condition of equal power consumption, the input voltage is changed between 1.8V and 3.3V, the output voltage is stabilized at 1.6V, the load capacitance is changed in a sampling period, the load transient response time of the system is only about 177ns, the static current of the system is 104.1uA, and the load capacity of 0mA-1mA is possessed; the LDO designed by the invention effectively improves the transient response speed of the LDO, meets the performance requirement of the Sigma-delta modulator, proves the reliability of the performance of the LDO through performance simulation, and has huge application space in the audio Sigma-delta modulator.
Drawings
Fig. 1 is a main circuit block diagram of a fast response LDO based on a cascode voltage flip-flop structure.
Fig. 2 is a diagram of a fast response loop configuration.
Fig. 3 is an overall circuit diagram of a fast response LDO based on a cascode voltage flip-flop structure.
Fig. 4 is a waveform diagram of a linear adjustment rate simulation of a fast response LDO based on a cascode voltage flip-flop structure.
Fig. 5 is a waveform diagram of a load adjustment rate simulation of a fast response LDO based on a cascode voltage flip-flop structure.
Fig. 6 is a load transient simulation graph of a fast response LDO based on a cascode voltage flip-flop structure.
Detailed Description
The technical scheme of the invention is specifically described below with reference to the accompanying drawings.
The invention provides a voltage inversion follower based on a common source and a common gateLDO of the device structure comprises MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10 and M P 、M N First to fourth current sources, first end of M1 and first end of M5, M P A first end of M8, a first end of M9, a first end of M10 are connected to VDD, a second end of M1 is connected to a control end of M6, a first end of M2, a control end of M1 is connected to a control end of M5, a control end of M9, a control end of M10, a second end of M7, a second end of M2 is connected to a control end of M2, a control end of M3, and connected to GND via a first current source, a first end of M3 is connected to M P Second end of M N Is connected as the output end of the LDO circuit, and the second end of M3 is connected with M N Is connected to the control end of M4 and is connected to GND via a second current source and a third current source, the second end of M4 is connected to the second end of M5, M P The control end of M4 is used as the bias voltage input end of the LDO circuit, the first end of M6 is connected with the first end of M7, and is connected with M via a fourth current source N The second terminal of M6 is connected to the second terminal of M8, the control terminal of M8, the second terminal of M9, and the control terminal of M7 is connected to the reference voltage source.
M6, M7, M8, M9, M10 and a fourth current source form a transconductance amplifier, wherein M8, M9 and M10 form a transconductance current enhancement circuit. The ratio of the width to the length of M8, M9 and M10 is as follows: 1: n: n+1, assuming that the magnitudes of the currents flowing through M6 and M7 are I, the current ratios flowing through M8, M9, and M10 are: i [1/n+1]: i [ n/n+1]: i, a step of I; when the load changes, the output voltage will generate downward overshoot when the load suddenly changes from light load to heavy load, so the output voltage of the output end of the LDO circuit suddenly decreases, the voltage at the control end of M6 suddenly decreases, and the transconductance of the transconductance amplifier is enhanced by n+1 times compared with that of the transconductance amplifier without increasing the transconductance current enhancement circuit, assuming that the current of M6 decreases to be half of the original current, namely 0.5I, the current of M7 becomes 1.5I, and the current flowing through M8 increases to be 0.5I (1/n+1); similarly, when the load is suddenly changed from heavy load to light load, the transconductance is enhanced by n+1 times.
M P The LDO circuit is a power tube. M3, M4, M P Forming a cascode voltageFlip follower structure.
The fast response loop comprises a first MOS tube, a seventh MOS tube, a fifth current source and a capacitor C1, wherein the first end of the first MOS tube is connected with the first end of the second MOS tube, the first end of the third MOS tube is connected to VDD, the second end of the first MOS tube is connected with the second end of the fourth MOS tube, the control end of the fourth MOS tube and the control end of the fifth MOS tube, the control end of the first MOS tube is connected with the control end of the second MOS tube and the control end of the third MOS tube, and the second end of the second MOS tube and the second end of the fifth MOS tube are connected to M P The second end of the third MOS tube is connected to GND through a fifth current source, the first end of the fourth MOS tube is connected with the second end of the sixth MOS tube, the control end of the sixth MOS tube and the control end of the seventh MOS tube, and the first end of the fifth MOS tube is connected with the second end of the seventh MOS tube and connected to M through C1 P The first end of the sixth MOS transistor and the first end of the seventh MOS transistor are connected to GND.
The LDO circuit also comprises a bias circuit for providing bias voltage and bias current for the LDO circuit.
The following is a specific implementation procedure of the present invention.
The invention provides a novel quick response LDO based on a cascode voltage flip follower structure. The invention adopts SMIC0.18 mu mCMOS technology to carry out simulation verification, and the input voltage range is as follows: 1.8V-3.3V, 1.6V output voltage, 10pF load capacitance, 0mA-1mA load current, and in the design process, the LDO is applied to the background of an audio Sigma-delta modulator, and finally, the quick transient response and low power consumption are realized.
The main circuit of the fast response LDO based on the cascode voltage flip follower structure is shown in fig. 1. In FIG. 1, M P The transistors are power transistors, as can be seen from the above description, transistors M3, M4, M P The structure of the cascode voltage flip follower is formed and is a main loop of the LDO. M6, M7, M8, M9 and M10 tail currents Is jointly form a transconductance amplifier, MOS tubes M2 and M3 have the same size and flow the same static current, and MOS tube M N Has a certain static current and is connected with the output end.
When the output voltage Vout changes, the power tube M is regulated by the MOS tubes M3 and M4 P The gate terminal voltage of (a) changes the output current so that the output voltage returns to a stable value. M6, M7, M8, M9 and M10 tail currents IS jointly form a transconductance amplifier, M8, M9 and M10 jointly form a transconductance enhancement circuit, and an NMOS tube M Is connected to an output end N When the load is suddenly changed, M N The tube provides additional static current, so that the transient response speed of the load of the system is faster, and meanwhile, the MOS tube M N The gate terminal of (2) is connected with the main loop to promote the feedback of the loop.
The tail currents Is of M6, M7, M8, M9 and M10 jointly form a transconductance amplifier, and a transconductance current enhancement circuit Is added into the transconductance amplifier. In the drawing, in the dashed line boxes, M8, M9 and M10 form a transconductance current enhancing circuit, and for convenience of explanation, the aspect ratio of the MOS transistors M8, M9 and M10 is set as follows: 1: n: n+1, it is known that the currents flowing through the MOS transistors M6 and M7 are equal in the static state, and the ratio of the currents flowing through the three transistors M8, M9, and M10 is: i [1/n+1]: i [ n/n+1]: i, a step of I; when the load changes, the output voltage will overshoot downwards when the load suddenly changes from light load to heavy load, so VOUT suddenly decreases to suddenly decrease VREF, and supposing that the current M6 is reduced to half of the original current, namely 0.5I, M7 current becomes 1.5I, and the current flowing through M8 is increased to 0.5I (1/n+1), compared with a transconductance amplifier without increasing the transconductance current enhancement circuit, the transconductance is enhanced by n+1 times. When the load is suddenly changed from heavy load to light load, the same analysis shows that the transconductance is enhanced by n+1 times.
In order to further improve the load transient response speed of the LDO, a fast loop is further added in the design of the invention. As shown in the circuit of fig. 2, for a simple cascode structure, the bias current is set to a ratio of 1:10 for reducing power consumption. The fast loop is connected to the power tube M in FIG. 1 through a capacitor P The output terminal Vout, point x in the figure is the connection point with the gate terminal of the power tube. The capacitor C1 exists, and is in an open circuit state in a direct current working environment, so that the capacitor has no influence on the static working point of the main loop of the LDO, and when alternating current changes, the capacitor is conducted, and the loop is fastAnd normally works. Fig. 3 is an overall circuit diagram of a fast response LDO based on a cascode voltage flip-flop.
Next, taking an example of abrupt change of load from light load to heavy load, the main working principle of the fast response LDO based on the cascode voltage flip follower structure provided by the invention is analyzed:
when the load suddenly changes from light load to heavy load, a large amount of current is pumped out from the output end, and the output voltage suddenly becomes smaller:
1. when the load current increases, the output voltage is pulled low, the main loop: the voltage of the grid end of the power tube is reduced through MOS tubes M3 and M4 of the common grid structure, the output current of the power tube is increased, the output voltage is restored to a steady-state value, meanwhile, the common grid tube is added to enable the loop gain to be increased, and the load adjustment rate of the LDO is improved.
2. When the load current becomes large, from M N The tube provides additional quiescent current such that the overshoot voltage of the output voltage becomes small while M N The gate terminal voltage of the power tube is further reduced through the common-gate MOS tube M4 by reducing the tube current, so that the power tube current is increased, and the output voltage is increased and restored to a steady-state value. M is M N The addition of the tube effectively improves the load transient response speed of the LDO and reduces the overshoot of the output voltage.
3. Under the high-frequency change, the output voltage changes to enable the voltage of the grid end of the power tube to be rapidly reduced through a rapid loop, the output current is increased, and the output voltage is restored to a steady-state value.
The transient simulation result of the LDO circuit is shown in fig. 4, and as shown in fig. 4, a linear adjustment rate simulation waveform diagram of the load current changing from 0mA to 1mA is shown, when the load current is 1mA, the output voltage change is 1.5669mV, and according to the calculation formula of the linear adjustment rate, the linear adjustment rates are respectively: when the load is 0mA and the input voltage is changed from 1.8V to 3.3V, the output voltage is changed to 1.779mV, and the linear adjustment rate is 0.659mV/V through calculation.
The invention focuses on the improvement of the transient response speed of the load. Therefore, in the DC characteristic simulation of the present invention, the load current changes only from 0mA to 1mA. FIG. 5 is a simulation graph of the load regulation rate for an input voltage of 1.8V-3.3V, with the maximum change in output voltage being only 0.109mV when the load current is from 0mA-1mA. Under the different power supply voltage changes of 1.8V, 2.3V, 2.8V and 3.3V, the output voltage changes are respectively as follows: 0.109mV, 0.093mV, 0.091mV, 0.093mV. According to the calculation formula of the load adjustment rate, the load adjustment rate is respectively as follows: 0.0605V/V.times.A, 0.0404V/V.times.A, 0.0325V/V.times.A, 0.0281V/V.times.A. The maximum quiescent current of the LDO of this section is only: 104.1uA, and realizes low power consumption design. Fig. 6 shows a load transient response diagram of the LDO. When the output load capacitance changes within the sampling period, the output voltage transient response time is only around 177 ns.
The invention designs an improved LDO circuit applied to an audio Sigma-delta modulator. The invention adopts SMIC0.18 mu mCMOS technology to carry out simulation verification, and the input voltage range is as follows: 1.8V-3.3V, 1.6V output voltage, 10pF load capacitance, 0mA-1mA load current, and in the design process, the LDO is applied to the background of an audio Sigma-delta modulator, and finally, the quick transient response and low power consumption are realized. Finally, the total design circuitry was incorporated into a Sigma-delta modulator and photographed on a real chip.
The above is a preferred embodiment of the present invention, and all changes made according to the technical solution of the present invention belong to the protection scope of the present invention when the generated functional effects do not exceed the scope of the technical solution of the present invention.
Claims (3)
1. LDO based on common-source common-gate voltage flip follower structure is characterized by comprising MOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10 and M P 、M N First to fourth current sources, first end of M1 and first end of M5, M P A first end of M8, a first end of M9, a first end of M10 are connected to VDD, a second end of M1 is connected to a control end of M6, a first end of M2, a control end of M1 is connected to a control end of M5, a control end of M9, a control end of M10, a second end of M7, a second end of M2 is connected to a control end of M2, a control end of M3, and connected to GND via a first current source, a first end of M3 is connected to M P Second end of M N Is connected as the output end of the LDO circuit, and the second end of M3 is connected with M N Is connected to the control end of M4 and is connected to GND via a second current source and a third current source, the second end of M4 is connected to the second end of M5, M P The control end of M4 is used as the bias voltage input end of the LDO circuit, the first end of M6 is connected with the first end of M7, and is connected with M via a fourth current source N A second end of M6 is connected with a second end of M8, a control end of M8 and a second end of M9, and a control end of M7 is connected with a reference voltage source; m6, M7, M8, M9, M10 and a fourth current source form a transconductance amplifier, wherein M8, M9 and M10 form a transconductance current enhancement circuit; the ratio of the width to the length of M8, M9 and M10 is as follows: 1: n: n+1, assuming that the magnitudes of the currents flowing through M6 and M7 are I, the current ratios flowing through M8, M9, and M10 are: i1/n+1]：I[n/n+1]: i, a step of I; when the load changes, the output voltage will generate downward overshoot when the load suddenly changes from light load to heavy load, so the output voltage of the output end of the LDO circuit suddenly decreases, the voltage at the control end of M6 suddenly decreases, and the transconductance of the transconductance amplifier is enhanced by n+1 times compared with that of the transconductance amplifier without increasing the transconductance current enhancement circuit, assuming that the current of M6 decreases to be half of the original current, namely 0.5I, the current of M7 becomes 1.5I, and the current flowing through M8 increases to be 0.5I (1/n+1); similarly, when the load is suddenly changed from heavy load to light load, the transconductance is enhanced by n+1 times; m3, M4, M P Forming a cascode voltage flip follower structure; the fast response loop comprises a first MOS tube, a seventh MOS tube, a fifth current source and a capacitor C1, wherein the first end of the first MOS tube is connected with the first end of the second MOS tube, the first end of the third MOS tube is connected to VDD, the second end of the first MOS tube is connected with the second end of the fourth MOS tube, the control end of the fourth MOS tube and the control end of the fifth MOS tube, the control end of the first MOS tube is connected with the control end of the second MOS tube and the control end of the third MOS tube, and the second end of the second MOS tube and the second end of the fifth MOS tube are connected to M P The second end of the third MOS tube is connected to GND through a fifth current source, the first end of the fourth MOS tube and the second end of the sixth MOS tube, the control end of the sixth MOS tube and the fourth MOS tube are connected to the GND through a fifth current sourceThe control end of the seventh MOS tube is connected, the first end of the fifth MOS tube is connected with the second end of the seventh MOS tube, and is connected to M through C1 P The first end of the sixth MOS transistor and the first end of the seventh MOS transistor are connected to GND.
2. The LDO of claim 1, wherein M is a cascode voltage flip-flop based structure P The LDO circuit is a power tube.
3. The LDO based on the cascode voltage flip-follower structure of claim 1, further comprising a bias circuit for providing a bias voltage, a bias current to the LDO circuit.
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| US5889393A (en) * | 1997-09-29 | 1999-03-30 | Impala Linear Corporation | Voltage regulator having error and transconductance amplifiers to define multiple poles |
| US7446515B2 (en) * | 2006-08-31 | 2008-11-04 | Texas Instruments Incorporated | Compensating NMOS LDO regulator using auxiliary amplifier |
| CN101419479B (en) * | 2008-12-10 | 2012-05-23 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| CN102298407A (en) * | 2010-06-28 | 2011-12-28 | 中国人民解放军国防科学技术大学 | Low-output voltage and fast response low-dropout regulator (LDO) circuit based on current control loop |
| CN202110462U (en) * | 2011-05-11 | 2012-01-11 | 电子科技大学 | LDO based on dynamic zero-pole tracking techniques |
| US8624568B2 (en) * | 2011-09-30 | 2014-01-07 | Texas Instruments Incorporated | Low noise voltage regulator and method with fast settling and low-power consumption |
| EP2605102B1 (en) * | 2011-12-12 | 2014-05-14 | Dialog Semiconductor GmbH | A high-speed LDO Driver Circuit using Adaptive Impedance Control |
| US9405309B2 (en) * | 2014-11-29 | 2016-08-02 | Infineon Technologies Ag | Dual mode low-dropout linear regulator |
| CN104898752B (en) * | 2015-06-26 | 2017-03-15 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of fast transient response without capacitor type LDO |
| CN105005351B (en) * | 2015-07-23 | 2017-02-01 | 中山大学 | Cascode fully integrated low-dropout linear voltage regulator circuit |
| CN107102665A (en) * | 2016-02-22 | 2017-08-29 | 联发科技（新加坡）私人有限公司 | Low pressure difference linear voltage regulator |
| CN208188718U (en) * | 2018-05-31 | 2018-12-04 | 福州大学 | Quick response LDO circuit based on cascade voltage overturning follower configuration |
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