CN113568462A - High power supply of noise restraines than circuit - Google Patents

High power supply of noise restraines than circuit Download PDF

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Publication number
CN113568462A
CN113568462A CN202110513722.7A CN202110513722A CN113568462A CN 113568462 A CN113568462 A CN 113568462A CN 202110513722 A CN202110513722 A CN 202110513722A CN 113568462 A CN113568462 A CN 113568462A
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CN
China
Prior art keywords
mos transistor
circuit
amplifying circuit
power supply
high power
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Pending
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CN202110513722.7A
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Chinese (zh)
Inventor
林浩
张廉
冉成新
王宝峰
张力
夏银水
王志红
林丰成
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Ningbo Xinneng Microelectronic Technology Co ltd
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Ningbo Xinneng Microelectronic Technology Co ltd
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Application filed by Ningbo Xinneng Microelectronic Technology Co ltd filed Critical Ningbo Xinneng Microelectronic Technology Co ltd
Priority to CN202110513722.7A priority Critical patent/CN113568462A/en
Publication of CN113568462A publication Critical patent/CN113568462A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Abstract

The invention relates to the technical field of electronics, in particular to a circuit with high noise and power supply rejection ratio, which comprises: by an operational amplifier and a capacitor C1A first stage amplifying circuit; by MOS transistor M2、M3、M4、M5、M6、M7、M8And MPSAnd a resistance RCAnd a capacitor C, CCA second stage amplifying circuit; and a MOS transistor M1、MPCapacitor Cpar、CO、CbAnd a resistance Resr、RLA third pole amplifying circuit; the output end of the operational amplifier in the first-stage amplifying circuit is connected to the MOS transistor M in the second-stage amplifying circuit6The MOS transistor M in the second stage amplifying circuitPSGrid electrode of the MOS transistor M is connected with the third pole amplifying circuitPThe MOS transistor M in the second stage amplifying circuit2Grid electrode of the MOS transistor M is connected with the third pole amplifying circuit1A gate electrode of (1). On the basis, higher PSRR and better belt are realizedAnd (4) wide.

Description

High power supply of noise restraines than circuit
Technical Field
The invention relates to the technical field of electronics, in particular to a noise high power supply rejection ratio circuit.
Background
With the continuous development of electronic products, power management solutions are continuously pursuing high efficiency, small area, and low cost. The ldo (ldo drop out) linear regulator has been widely used in various mobile electronic systems, such as notebook computers, cellular phones, pagers, PDAs, etc., due to its outstanding features of simple structure, low cost, low noise, low power consumption, and small package size. It can greatly reduce the saturation voltage of the output transistor, so that the input voltage can be very close to the output voltage, thereby reducing power consumption and prolonging the service life of the battery. However, in the prior art, a zero point is introduced by a series resistor of an external capacitor in the rejection ratio circuit to offset a pole to achieve loop stability, and because a main pole value is in direct proportion to a load resistor, the change of output current can change the loop bandwidth; secondly, the parasitic resistance of the output capacitor is susceptible to temperature, etc., so that the offset between the zero and the pole is disabled, and the stability is deteriorated.
Disclosure of Invention
It is an object of the present invention to provide a noise high power supply rejection ratio circuit to solve the above-mentioned problems of the background art.
To achieve the above object, the present invention provides a noise high power supply rejection ratio circuit, comprising:
by an operational amplifier and a capacitor C1A first stage amplifying circuit;
by MOS transistor M2、M3、M4、M5、M6、M7、M8And MPSAnd a resistance RCAnd a capacitor C, CCA second stage amplifying circuit;
and a MOS transistor M1、MPCapacitor Cpar、CO、CbAnd a resistance Resr、RLA third pole amplifying circuit;
the output end of the operational amplifier in the first-stage amplifying circuit is connected to the MOS transistor M in the second-stage amplifying circuit6The MOS transistor M in the second stage amplifying circuitPSGrid electrode of the MOS transistor M is connected with the third pole amplifying circuitPThe MOS transistor M in the second stage amplifying circuit2Grid electrode of the MOS transistor M is connected with the third pole amplifying circuit1A gate electrode of (1).
As a further improvement of the technical scheme, the third pole amplifying circuit adopts an MOS tube MPAs the output stage of the regulating tube, sufficiently low input-output pressure difference is provided, and the output is fed back to the same-direction input end of the operational amplifier.
As a further improvement of the technical scheme, the MOS tube MP、MPS、M1And M2Constituting a current sampling circuit.
As a further improvement of the technical scheme, the MOS tube M7And M8Are interconnected, and the MOS transistor M8Via a resistor RCBack-connected to a capacitor CCThe MOS transistor M7Drain connected to the MOS transistor M4Is provided.
As a further improvement of the technical scheme, the MOS tube MPDrain connected to the MOS transistor M1Source electrode of (1), the MOS tube MPSDrain connected to the MOS transistor M2Of the substrate.
As a further improvement of the technical scheme, the MOS tube MPSAnd the MOS tube MPBetween them is connected with a capacitor CparAnd pulls the signal ground down.
As a further improvement of the technical scheme, the MOS tube M3、M4、M5Are interconnected, and the MOS transistor M3、M4、M5The source of (2) is connected to signal ground.
As a further improvement of the technical scheme, the MOS tube MPAnd is respectively connected with a capacitor COAnd CbAnd in the capacitor COAnd MOS transistor MPIs connected with a resistor ResrMOS transistor M as parasitic resistancePAnd is respectively connected with a capacitor COAnd CbAnd in the capacitor COAnd MOS transistor MPIs connected with a resistor ResrAs a parasitic resistance.
As a further improvement of the technical scheme, the MOS tube M2Is equal to the output voltage.
As a further improvement of the technical scheme, the MOS tube M8And the linear resistor is operated in a linear region and is used as a linear resistor with the resistance value changing along with the load current.
Compared with the prior art, the invention has the beneficial effects that:
the invention aims at a high-stability high-power-supply-rejection-ratio linear circuit with 100mA output current, adopts a three-stage amplifier structure to increase loop gain, utilizes the voltage-controlled resistance characteristic of an MOS (metal oxide semiconductor) tube working in a linear region, constructs a zero tracking circuit to offset a pole changing along with the output current, and adopts an improved Miller compensation scheme to ensure that a circuit system has 55-degree phase margin. On the basis, higher PSRR and better bandwidth are realized.
Drawings
FIG. 1 is a first circuit diagram of a conventional suppression ratio circuit;
FIG. 2 is a circuit diagram II of a conventional suppression ratio circuit;
FIG. 3 is a circuit diagram of the noise high power supply rejection ratio circuit of the present invention;
FIG. 4 is a circuit diagram of a first stage of amplification circuitry in the noise high power supply rejection ratio circuit of the present invention;
FIG. 5 is a circuit diagram of a second stage amplifier circuit in the noise high power supply rejection ratio circuit of the present invention;
fig. 6 is a circuit diagram of a third stage amplification circuit in the noise high power supply rejection ratio circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 and 2 show a prior art rejection ratio circuit, which achieves loop stability by introducing a zero through a series resistor of an external capacitor to cancel a pole. It has several disadvantages: first, since the main pole value is proportional to the load resistance, the change in output current changes the loop bandwidth; secondly, the parasitic resistance of the output capacitor is susceptible to temperature, etc., so that the offset between the zero and the pole is disabled, and the stability is deteriorated.
In view of this, the present embodiment provides a noise high power supply rejection ratio circuit, as shown in fig. 3 to 6, which includes: by an operational amplifier and a capacitor C1A first stage amplifying circuit; by MOS transistor M2、M3、M4、M5、M6、M7、M8And MPSAnd a resistance RCAnd a capacitor C, CCA second stage amplifying circuit; and a MOS transistor M1、MPCapacitor Cpar、CO、CbAnd a resistance Resr、RLA third pole amplifying circuit; the output end of the operational amplifier in the first-stage amplifying circuit is connected to the MOS transistor M in the second-stage amplifying circuit6The MOS transistor M in the second stage amplifying circuitPSGrid electrode of the MOS transistor M is connected with the third pole amplifying circuitPThe MOS transistor M in the second stage amplifying circuit2Grid electrode of the MOS transistor M is connected with the third pole amplifying circuit1A gate electrode of (1). The third-pole amplifying circuit adopts an MOS tube MPAs the output stage of the regulating tube, sufficiently low input-output pressure difference is provided, and the output is fed back to the same-direction input end of the operational amplifier. The MOS tube MP、MPS、M1And M2Constituting a current sampling circuit. The MOS tube M7And M8Are interconnected, and the MOS transistor M8Via a resistor RCBack-connected to a capacitor CCThe MOS transistor M7Drain connected to the MOS transistor M4Is provided. The MOS tube MPDrain connected to the MOS transistor M1Source electrode of (1), the MOS tube MPSDrain connected to the MOS transistor M2Of the substrate. The MOS tube MPSAnd the MOS tube MPBetween them is connected with a capacitor CparAnd pulls the signal ground down. The MOS tube M3、M4、M5Are interconnected, and the MOS transistor M3、M4、M5The source of (2) is connected to signal ground. MOS transistor MPAnd is respectively connected with a capacitor COAnd CbAnd in the capacitor COAnd MOS transistor MPIs connected with a resistor ResrMOS transistor M as parasitic resistancePAnd is respectively connected with a capacitor COAnd CbAnd in the capacitor COAnd MOS transistor MPIs connected with a resistor ResrAs a parasitic resistance.
In this example, VfbIs a feedback signal, VrefFrom a bandgap reference, the first stage is an error amplifier; the second stage is also an amplifier, and the loop gain of the circuit is increased, so that the circuit can drive a load with low resistance; using PMOS transistor MPAs a regulating tube output stage to provide a sufficiently low input-output pressure difference; the output is fed back directly to the operational amplifier input.
M1Has a small bias current M2W/L of (a) is so large that M1And M2All work near subthreshold region, therefore its voltage is infinitely close, sampling tube M2The drain terminal voltage of (1) is equal to the output voltage Vout. Thus MPSAnd MPThe source-drain gate voltages are equal, so the sampling circuit has high sampling precision.
MOS transistor M8Operating in the linear region, can be seen as a linear resistor with a resistance that varies with load current. Assuming that its equivalent resistance is rM8Then r isM8、RCAnd CCA load-dependent zero can be generated in the error amplifier's open-loop transfer function and this zero can be used to cancel the output pole that also varies with load. The pole splitting effect of the Miller capacitance C can move the dominant pole to the output of the first stage and push an additional pole towards high frequencies. CCAnd CbIs a compensation capacitor, where a resistor C is addedbBecause of the individual rM8It does not provide a resistance large enough to compensate and cancel the output pole.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and the preferred embodiments of the present invention are described in the above embodiments and the description, and are not intended to limit the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A noise high power supply rejection ratio circuit, comprising: the method comprises the following steps:
by an operational amplifier and a capacitor C1A first stage amplifying circuit;
by MOS transistor M2、M3、M4、M5、M6、M7、M8And MPSAnd a resistance RCAnd a capacitor C, CCA second stage amplifying circuit;
and a MOS transistor M1、MPCapacitor Cpar、CO、CbAnd a resistance Resr、RLA third pole amplifying circuit;
the output end of the operational amplifier in the first-stage amplifying circuit is connected to the MOS transistor M in the second-stage amplifying circuit6The MOS transistor M in the second stage amplifying circuitPsGrid electrode of the MOS transistor M is connected with the third pole amplifying circuitPThe MOS transistor M in the second stage amplifying circuit2Grid electrode of the MOS transistor M is connected with the third pole amplifying circuit1A gate electrode of (1).
2. The noise high power supply rejection ratio circuit of claim 1, wherein: the third-pole amplifying circuit adopts an MOS tube MPAs the output stage of the regulating tube, sufficiently low input-output pressure difference is provided, and the output is fed back to the same-direction input end of the operational amplifier.
3. The noise high power supply rejection ratio circuit of claim 1, wherein: the MOS tube MP、MPs、M1And M2Constituting a current sampling circuit.
4. The noise high power supply rejection ratio circuit of claim 1, wherein: the MOS tube M7And M8Are interconnected, and the MOS transistor M8Via a resistor RCBack-connected to a capacitor CCThe MOS transistor M7Drain connected to the MOS transistor M4Is provided.
5. The noise high power supply rejection ratio circuit of claim 1, wherein: the MOS tube MPIs connected to the drain ofMOS transistor M1Source electrode of (1), the MOS tube MPSDrain connected to the MOS transistor M2Of the substrate.
6. The noise high power supply rejection ratio circuit of claim 1, wherein: the MOS tube MPsAnd the MOS tube MPBetween them is connected with a capacitor CparAnd pulls the signal ground down.
7. The noise high power supply rejection ratio circuit of claim 1, wherein: the MOS tube M3、M4、M5Are interconnected, and the MOS transistor M3、M4、M5The source of (2) is connected to signal ground.
8. The noise high power supply rejection ratio circuit of claim 1, wherein: the MOS tube MPAnd is respectively connected with a capacitor COAnd CbAnd in the capacitor COAnd MOS transistor MPIs connected with a resistor ResrAs a parasitic resistance.
9. The noise high power supply rejection ratio circuit of claim 1, wherein: the MOS tube M2Is equal to the output voltage.
10. The noise high power supply rejection ratio circuit of claim 1, wherein: the MOS tube M8And the linear resistor is operated in a linear region and is used as a linear resistor with the resistance value changing along with the load current.
CN202110513722.7A 2021-05-11 2021-05-11 High power supply of noise restraines than circuit Pending CN113568462A (en)

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Application Number Priority Date Filing Date Title
CN202110513722.7A CN113568462A (en) 2021-05-11 2021-05-11 High power supply of noise restraines than circuit

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220308609A1 (en) * 2021-03-25 2022-09-29 Qualcomm Incorporated Power supply rejection enhancer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220308609A1 (en) * 2021-03-25 2022-09-29 Qualcomm Incorporated Power supply rejection enhancer
US11687104B2 (en) * 2021-03-25 2023-06-27 Qualcomm Incorporated Power supply rejection enhancer

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