CN216697088U - LDO (Low dropout regulator) structure without off-chip capacitor - Google Patents

LDO (Low dropout regulator) structure without off-chip capacitor Download PDF

Info

Publication number
CN216697088U
CN216697088U CN202123252617.7U CN202123252617U CN216697088U CN 216697088 U CN216697088 U CN 216697088U CN 202123252617 U CN202123252617 U CN 202123252617U CN 216697088 U CN216697088 U CN 216697088U
Authority
CN
China
Prior art keywords
voltage
tube
ldo
circuit
reference current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202123252617.7U
Other languages
Chinese (zh)
Inventor
陈长江
王彬
徐凯
张永生
程晨
程银
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Daoyuan Technology Group Co ltd
Original Assignee
Jiangsu Daoyuan Technology Group Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Daoyuan Technology Group Co ltd filed Critical Jiangsu Daoyuan Technology Group Co ltd
Priority to CN202123252617.7U priority Critical patent/CN216697088U/en
Application granted granted Critical
Publication of CN216697088U publication Critical patent/CN216697088U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The utility model discloses an LDO structure without an off-chip capacitor, which is characterized in that on the basis of the existing LDO, feedback voltage generated by a feedback resistor network is led back to a reference circuit of the LDO through an additional feedback branch circuit, so that the reference current generated by the reference circuit can be adjusted through the magnitude of the feedback voltage, the reference current is used as tail current of a tail current pipe of an input error amplifier, the slew rate of the error amplifier is improved by improving the tail current, the transient characteristic of the LDO is improved, and the overshoot voltage and the recovery time of the LDO are reduced. Compared with the mode of improving the transient response of the LDO by adding a digital control loop and a slew rate enhancement circuit, the method provided by the utility model is practical and effective, the circuit structure is simple and easy to realize, the static power consumption is low, no extra pole and zero point is introduced into an error amplifier circuit, and the stability of the system is not influenced.

Description

LDO (Low dropout regulator) structure without off-chip capacitor
Technical Field
The utility model relates to a linear voltage regulator, in particular to an LDO low dropout regulator.
Background
The LDO (low dropout regulator) is used for supplying power to other circuits, and provides high-precision output voltage and extremely low voltage ripple. LDOs are widely used in electronic products as one type of power management chip. The consumer electronic products not only require high noise and ripple rejection for the power supply used by the circuit, but also require low possibility of static power exhaustion, and occupy a small area of the PCB board. Low power consumption and no off-chip capacitance are desirable for such applications.
As shown in fig. 1, the structure of the LDO mainly includes a reference circuit, an error amplifier, a power tube, a feedback resistor network, and an auxiliary circuit. The error amplifier and the power tube are core modules of the LDO, and a negative feedback closed-loop system is formed through a feedback resistance network. The basic working principle is that a feedback resistance network samples output voltage to obtain feedback voltage, an error amplifier amplifies an error between the feedback voltage and reference voltage, and controls the conduction state of a power tube, so that extra output voltage is obtained. When the output voltage of the LDO decreases, a feedback signal is provided through a feedback resistance network, the voltage of the homodromous input end of the error amplifier decreases, and the output signal V of the error amplifier is adjusted by comparing the voltage with the reference voltage of the inverting input end of the error amplifierOPOUTTherefore, the power tube is driven to provide larger current to the outside, and the output voltage of the LDO is raised; on the contrary, when the output voltage of the LDO rises, a feedback signal is provided through the feedback resistance network, the voltage of the homodromous input end of the error amplifier rises, and the output signal V of the error amplifier is adjusted by comparing the voltage with the reference voltage of the inverting input end of the error amplifierOPOUTThe power tube is driven to reduce the externally provided current, and the output voltage of the LDO is pulled down.
When the load current of the LDO suddenly changes or the output current of the power tube suddenly changes, the output voltage of the LDO can be fluctuated severely,feedback voltage V generated by feedback resistance networkFBAnd also fluctuates dramatically. When V isFBThe error amplifier enters a saturation state after the voltage value of the error amplifier exceeds the input voltage range of the error amplifier. At this time, the error amplifier charges and discharges the gate capacitance of the power tube according to the output current characteristic of the error amplifier.
Therefore, the overshoot voltage and recovery time are troublesome problems in low power LDO designs without off-chip capacitors. Firstly, the low power consumption means that the quiescent current of the chip is necessarily designed to be very low, and the first-stage amplifier and the second-stage amplifier can only use little bias current, so that a longer time is required for charging and discharging the load capacitance, and the maximum overshoot voltage is increased. The design without off-chip capacitor causes the capacitance at the load end of the LDO to be reduced, and the influence on the overshoot voltage is very direct, and when the load capacitance is reduced from 1uF to 1nF, the overshoot voltage can directly rise by three orders of magnitude theoretically.
In the prior art, a method for solving the problem of low-power-consumption LDO transient response without off-chip capacitor is mainly based on the following two ideas: firstly, a digital control mode is utilized to supplement extra charging and discharging current for a power tube; and secondly, an additional analog control loop is added to the power tube so as to improve additional charging and discharging current, and the loop is generally called as a slew rate enhancement circuit. The first concept is based on using a digital switch to provide or bleed current to the load terminal through an additional branch when the output current of the power transistor is different from the load current. The method has the advantages that when the current at the load end does not change suddenly, the circuit branch of the digital part is turned off, and no static power consumption exists. And the digital control mode has high response speed, and can effectively reduce the overshoot voltage of the LDO. The defects that the magnitude of the additionally supplemented current is difficult to control, the LDO is unstable in work and the output voltage is easy to oscillate due to too large current, the recovery time of the LDO is too long due to too small current, and the effect of enhancing the transient response of the LDO is not obvious.
The second concept is common, and the common structure includes direct-feed detection, a push-pull stage circuit and dynamic bias current adjustment. The direct-feed detection mode adopts a mode of directly detecting a feedback voltage point, detected overshoot or drop voltage is directly amplified through an additional branch circuit, and amplified signals are respectively used for controlling secondary control tubes which are connected in parallel beside the adjusting tube and the feedback circuit, so that the transient response capability of the LDO is improved. The scheme has the advantages of simple structure, obvious adjustment effect and large static power consumption, and has the defects of low load current capability for adjustment. The push-pull stage circuit is connected between the output end of the error amplifier and the input end of the power tube, and the basic principle is to expand the change range of the grid voltage of the power tube, so that the change rate of the output current of the power tube is increased, and the transient response capability of the LDO is improved. The scheme not only can improve the transient response characteristic of the LDO, but also can effectively separate the primary and secondary poles, and improve the stability of the system. The disadvantages are that the voltage regulation capability is too small, the load current range for regulation is too small, the effect of enhancing the transient response of the LDO is not obvious, and the introduction of the circuit reduces the integral gain of the error amplifier and reduces the precision of the output voltage of the LDO. The dynamic bias current adjusting circuit adopts the voltage detection and amplification circuit to amplify the overshoot and the drop of the output voltage and then send the amplified output voltage to the bias current enhancing circuit, so that the bias current of the bias branch circuit is enhanced when the load current suddenly changes, the tail current source size of the comparison circuit is further improved, and the adjusting capacity of the adjusting tube is further improved. The scheme can effectively solve the contradiction between high transient response characteristic and low power consumption, and has the disadvantages of low sensitivity of the voltage detection and amplification circuit and high requirements on the size and the process deviation of a device.
Disclosure of Invention
The purpose of the utility model is as follows: in view of the above prior art, an LDO structure without an off-chip capacitor is provided, which can recover quickly when the current at the load end of the LDO suddenly changes.
The technical scheme is as follows: an LDO structure without off-chip capacitor comprises an LDO main body circuit and a reference current adjusting circuit;
the LDO main circuit comprises a reference circuit, an error amplifier, a power tube and a feedback resistance network;
the reference circuit is used for outputting a reference voltage and a reference current;
the error amplifier is used for outputting the adjusting voltage of the power tube after differentially amplifying the reference voltage and the feedback voltage of the feedback resistance network;
the power tube is used for obtaining a voltage drop voltage according to the input voltage and the adjusting voltage, and obtaining an output voltage when the voltage drop voltage is kept constant;
the feedback resistance network is used for sampling the output voltage to obtain the feedback voltage and outputting the feedback voltage to the error amplifier;
the reference current adjusting circuit is used for adjusting the size of a reference current output by the reference circuit according to the feedback voltage, the reference current is input into a tail current tube of the error amplifier, and the reference current is positively correlated with the feedback voltage.
Further, the reference current adjusting circuit comprises an in-phase proportional operator; the reference circuit comprises a reference current source, wherein the reference current source comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6 and a resistor R1; the source electrodes of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M5 are all connected with VDD, the drain electrode of the PMOS tube M1 is connected with the drain electrode of the NMOS tube M3, the drain electrode of the PMOS tube M2 is connected with the drain electrode of the NMOS tube M4, the grid electrodes of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M5 are connected with the drain electrode of the PMOS tube M2, the grid electrodes of the NMOS tube M3 and the NMOS tube M4 are connected with the drain electrode of the PMOS tube M1, the source electrode of the NMOS tube M3 is connected with the drain electrode of the NMOS tube M6, the source electrode of the NMOS tube M6 is connected with one end of the resistor R1, and the other end of the resistor R1 and the source electrode of the NMOS tube M4 are all grounded; the grid electrode of the NMOS tube M6 is connected with the output end of the in-phase proportional arithmetic unit, and the drain electrode of the PMOS tube M5 outputs the reference current.
Has the advantages that: the utility model enhances the transient response of the LDO without an off-chip capacitor by detecting the value of the feedback voltage to adjust the reference current. Compared with the mode of improving the transient response of the LDO by adding a digital control loop and a slew rate enhancement circuit, the LDO transient response control circuit has the advantages of simple structure, easy realization, low static power consumption, no introduction of extra poles and zeros into an error amplifier circuit and no influence on the stability of the system.
Drawings
FIG. 1 is a schematic diagram of a conventional LDO structure;
FIG. 2 is a schematic diagram of an LDO structure according to the present invention;
FIG. 3 is a circuit diagram of a reference current adjusting circuit and a reference current source according to the present invention;
fig. 4 is a schematic diagram of the present invention.
Detailed Description
The utility model is further explained below with reference to the drawings.
As shown in FIG. 2, an LDO structure without off-chip capacitor comprises an LDO main circuit and a reference current adjusting circuit.
The LDO main circuit comprises a reference circuit, an error amplifier, a power tube and a feedback resistance network. The reference circuit is used for outputting a reference voltage and a reference current. The error amplifier is used for outputting the regulated voltage of the power tube after differentially amplifying the reference voltage and the feedback voltage of the feedback resistance network. The power tube is used for obtaining voltage drop voltage according to the input voltage and the adjusting voltage, and obtaining output voltage when the voltage drop voltage is kept constant. The feedback resistance network is used for sampling the output voltage to obtain a feedback voltage and outputting the feedback voltage to the error amplifier.
The reference current adjusting circuit is used for adjusting the size of the reference current output by the reference circuit according to the feedback voltage, the reference current is input into a tail current tube of the error amplifier, and the reference current is positively correlated with the feedback voltage.
The utility model is based on the prior LDO structure and uses the feedback voltage V generated by the feedback resistance networkFBThe reference current generated by the reference circuit can be led back to the reference circuit of the LDO through an additional feedback branch circuit, namely a reference current adjusting circuit, so that the reference current can be generated by the reference circuit through the feedback voltage VFBIs adjusted. When the output voltage of LDO has overshoot voltage, the feedback voltage VFBIncreasing the reference current, outputting a voltage signal or a current signal to the reference circuit after passing through the reference current adjusting circuit, increasing the output reference current, which is used as an input error for amplificationThe tail current of the tail current tube of the device improves the slew rate of the error amplifier by improving the tail current, and improves the transient characteristic of the LDO, thereby reducing the overshoot voltage and the recovery time of the LDO.
From an overshoot voltage
Figure DEST_PATH_GDA0003596718430000041
It can be known that the main cause of the LDO overshoot voltage is the difference current between the power tube output current and the load current of the LDO. Wherein, CLIn the design of LDOs without off-chip capacitors for load capacitors, CLAre generally small; i isDS,POW(τ) is the drain current of PMOS power tube, IOUT(τ) is the output current of the LDO,. DELTA.IOUT(τ) is IDS,POW(τ) and IOUTDifferential current of (t), t0Is the starting time for the load to change. It can be seen that, as shown in fig. 4, the way to reduce the magnitude of the overshoot voltage can also be achieved by reducing the time during which the difference current exists, i.e. increasing the rate of change of the output current of the power tube. The power tube is a power tube, and the output current of the power tube is realized by controlling the grid electrode of the power tube through the output voltage of the error amplifier. Therefore, increasing the output voltage change rate of the error amplifier is to increase the change rate of the gate voltage of the power tube and the change rate of the output current of the power tube. The output voltage change rate of the error amplifier is positively correlated with the slew rate of the error amplifier, and the slew rate of the error amplifier is positively correlated with the tail current of the error amplifier, so that the transient response of the LDO is improved by dynamically adjusting the current of the tail current tube of the error amplifier when the load current is suddenly changed.
As shown in fig. 3, the reference current adjusting circuit includes an in-phase proportional operator, and the reference circuit includes a reference current source. The reference current source comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6 and a resistor R1. The source electrodes of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M5 are all connected with VDD; the drain electrode of the PMOS tube M1 is connected with the drain electrode of the NMOS tube M3, and the drain electrode of the PMOS tube M2 is connected with the drain electrode of the NMOS tube M4; the gates of the PMOS transistor M1, the PMOS transistor M2 and the PMOS transistor M5 are connected with the drain of the PMOS transistor M2(ii) a The grid electrodes of the NMOS tube M3 and the NMOS tube M4 are connected with the drain electrode of the PMOS tube M1; the source electrode of the NMOS tube M3 is connected with the drain electrode of the NMOS tube M6, the source electrode of the NMOS tube M6 is connected with one end of a resistor R1, and the other end of the resistor R1 and the source electrode of the NMOS tube M4 are grounded; the grid electrode of the NMOS tube M6 is connected with the output end of the in-phase proportional arithmetic unit, and the drain electrode of the PMOS tube M5 outputs the reference current IrefAnd the tail current is provided for a tail current tube of an error amplifier in the LDO.
In the circuit, the NMOS transistor M6 operates in the variable resistance region, and acts as a variable resistance. Feedback voltage VFBAmplified by an in-phase proportional operation circuit and then applied to the grid of an NMOS transistor M6 by the linear region resistance formula of an MOS transistor
Figure DEST_PATH_GDA0003596718430000051
It can be seen that changing the magnitude of the gate voltage changes its resistance. The drain-source current flowing through the PMOS transistor M1 and the PMOS transistor M2 is obtained from the reference current source circuit
Figure DEST_PATH_GDA0003596718430000052
Figure DEST_PATH_GDA0003596718430000053
Therefore, the output current of the reference current source is changed by changing the resistance value; wherein, W/L is the width-length ratio of PMOS transistor M1 and PMOSM2, and resistance RsIs the sum of the resistance values of the NMOS transistor M6 and the resistor R1, K is the ratio of the width-to-length ratios of the NMOS transistor M3 and the NMOS transistor M4, munIs the carrier mobility of NMOS tube, CoxIs a gate oxide capacitance.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (2)

1. An LDO structure without an off-chip capacitor is characterized by comprising an LDO main body circuit and a reference current adjusting circuit;
the LDO main circuit comprises a reference circuit, an error amplifier, a power tube and a feedback resistance network;
the reference circuit is used for outputting a reference voltage and a reference current;
the error amplifier is used for outputting the adjusting voltage of the power tube after differentially amplifying the reference voltage and the feedback voltage of the feedback resistance network;
the power tube is used for obtaining a voltage drop voltage according to the input voltage and the adjusting voltage, and obtaining an output voltage when the voltage drop voltage is kept constant;
the feedback resistance network is used for sampling the output voltage to obtain the feedback voltage and outputting the feedback voltage to the error amplifier;
the reference current adjusting circuit is used for adjusting the size of a reference current output by the reference circuit according to the feedback voltage, the reference current is input into a tail current tube of the error amplifier, and the reference current is positively correlated with the feedback voltage.
2. The LDO architecture without off-chip capacitor of claim 1, wherein the reference current regulation circuit comprises an in-phase proportional operator; the reference circuit comprises a reference current source, wherein the reference current source comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, an NMOS tube M3, an NMOS tube M4, an NMOS tube M6 and a resistor R1; the source electrodes of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M5 are all connected with VDD, the drain electrode of the PMOS tube M1 is connected with the drain electrode of the NMOS tube M3, the drain electrode of the PMOS tube M2 is connected with the drain electrode of the NMOS tube M4, the grid electrodes of the PMOS tube M1, the PMOS tube M2 and the PMOS tube M5 are connected with the drain electrode of the PMOS tube M2, the grid electrodes of the NMOS tube M3 and the NMOS tube M4 are connected with the drain electrode of the PMOS tube M1, the source electrode of the NMOS tube M3 is connected with the drain electrode of the NMOS tube M6, the source electrode of the NMOS tube M6 is connected with one end of the resistor R1, and the other end of the resistor R1 and the source electrode of the NMOS tube M4 are all grounded; the grid electrode of the NMOS tube M6 is connected with the output end of the in-phase proportional arithmetic unit, and the drain electrode of the PMOS tube M5 outputs the reference current.
CN202123252617.7U 2021-12-23 2021-12-23 LDO (Low dropout regulator) structure without off-chip capacitor Active CN216697088U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202123252617.7U CN216697088U (en) 2021-12-23 2021-12-23 LDO (Low dropout regulator) structure without off-chip capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202123252617.7U CN216697088U (en) 2021-12-23 2021-12-23 LDO (Low dropout regulator) structure without off-chip capacitor

Publications (1)

Publication Number Publication Date
CN216697088U true CN216697088U (en) 2022-06-07

Family

ID=81842638

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202123252617.7U Active CN216697088U (en) 2021-12-23 2021-12-23 LDO (Low dropout regulator) structure without off-chip capacitor

Country Status (1)

Country Link
CN (1) CN216697088U (en)

Similar Documents

Publication Publication Date Title
US10019023B2 (en) Low-dropout linear regulator with super transconductance structure
CN107688366B (en) LDO circuit and implementation method of LDO
CN102830742B (en) Linear stabilizer with low pressure difference
US9671805B2 (en) Linear voltage regulator utilizing a large range of bypass-capacitance
CN108776506B (en) high-stability low-dropout linear voltage regulator
CN102681582A (en) Linear voltage stabilizing circuit with low voltage difference
CN207488871U (en) A kind of CMOS low pressure difference linear voltage regulators using novel buffer
US11009901B2 (en) Methods and apparatus for voltage regulation using output sense current
KR20080082460A (en) Voltage regulator circuit and control method therefor
US9831757B2 (en) Voltage regulator
CN111176358B (en) Low-power-consumption low-dropout linear voltage regulator
CN113467559B (en) Adaptive dynamic zero compensation circuit applied to LDO (low dropout regulator)
CN111736652B (en) Capacitance multiplying circuit and linear voltage regulator
CN211878488U (en) Wide-input low-dropout linear voltage stabilizing circuit
US8890612B2 (en) Dynamically biased output structure
TW201821925A (en) Voltage regulator
CN216697088U (en) LDO (Low dropout regulator) structure without off-chip capacitor
CN116185115A (en) LDO composite zero tracking compensation circuit
CN114281142B (en) Off-chip capacitor LDO with high transient response
CN115981408A (en) Ultra-low dropout output transient enhanced LDO circuit without off-chip capacitor
US9367073B2 (en) Voltage regulator
CN107256055A (en) One kind is without electric capacity LDO circuit outside piece
CN115097893B (en) LDO circuit and MCU chip capable of outputting capacitor without plug-in
Liu et al. An output-capacitor-less low-dropout regulator with transient-improved technique
CN110703850B (en) Low dropout regulator

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant