CN108494232A - A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney - Google Patents
A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney Download PDFInfo
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- CN108494232A CN108494232A CN201810427374.XA CN201810427374A CN108494232A CN 108494232 A CN108494232 A CN 108494232A CN 201810427374 A CN201810427374 A CN 201810427374A CN 108494232 A CN108494232 A CN 108494232A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney, belongs to electronic circuit technology field.Including voltage detection module, Logic control module and drive module, voltage detection module is used to detect the voltage difference between external rectifying tube drain electrode and source electrode, judge the state of rectifying tube parasitic diode, Logic control module generates minimum turn-on time and the blanking time of rectifying tube, the current polarity of rectifying tube is detected in minimum turn-on time simultaneously, the generation electric current in minimum turn-on time is avoided to pour in down a chimney phenomenon, rectifying tube drive waveforms are shaken in the case of also avoiding low current, and drive module is used to provide the gate driving of rectifying tube.Control circuit provided by the invention is safe and reliable, while can realize lower conduction loss, improves generator whole efficiency, plays the role of energy saving and clean environment firendly.
Description
Technical field
The invention belongs to electronic circuit technologies, particularly relate to a kind of control of the rectification circuit for electric power generation
Circuit.
Background technology
Generation current machine rectifier mainly uses silicon diode as rectifier cell, and silicon diode forward voltage drop is about
0.3~1V, on-state power consumption is very big when high current.It is a large amount of universal with automobile, by silicon diode commutating zone Lai power consumption do not allow
Ignore.
Synchronous rectification (Synchronous Rectification, SR) uses power metal-oxide of low-voltage
Semiconductor field effect transistor (Power MOSFET) can be very good to drop as rectifying device using its raceway groove on state resistance
The overall power of low rectifier module.And the main difficulty of synchronous rectification is used to be that the grid of its rectifying tube controls, such as
The current polarity that fruit flows through rectifying tube changes suddenly, there is input/output end port at this time to battery or the electric current of ground level
Access, composition are poured in down a chimney, and the damage to rectifier and control circuit can be caused.
The driving of rectifying tube mainly uses pulse width modulation (PWM) mode, and realization is complex, needs to establish space arrow
Mathematical model is measured, complicated transformation is carried out and solves, therefore a large amount of logical process is needed on circuit composition, increases technology hardly possible
Degree and cost；And automobile current generator is influenced by automobile rotational speed, further increases the difficulty of control algolithm, application cost is too high, unfavorable
In the universal of synchronous rectification.
Invention content
The purpose of the present invention is big, of high cost aiming at technical difficulty present in current synchronous rectification, power consumption is big
The problem of, propose a kind of control circuit, the rectification circuit for controlling electric power generation, simple in structure, circuit power consumption is low, Neng Gouti
The whole efficiency of high motor, and can prevent electric current from pouring in down a chimney so that rectification circuit is more safe and reliable.
The technical scheme is that：
A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney is wrapped for controlling the rectifying tube in synchronous rectification system
Voltage detection module, Logic control module and drive module are included,
The voltage detection module is used to detect the drain-source voltage of the rectifying tube and generates first detection signal, the second inspection
Survey signal, third detection signal and the 4th detection signal；
The voltage detection module includes the 4th NDMOS pipes M4, the 4th comparator Comp4 and the 4th voltage source, the 4th ratio
In-phase input end compared with device Comp4 connects the source electrode of the 4th NDMOS pipes M4, and inverting input connects the forward direction of the 4th voltage source
End, output end output the 4th detection signal；The grid of 4th NDMOS pipes M4 connects supply voltage, drain electrode connection institute
State the drain electrode of rectifying tube；The negative end of 4th voltage source connects the source electrode of the rectifying tube；
The Logic control module is touched including the first d type flip flop D1, the second d type flip flop D2, third d type flip flop D3, the 4th D
Send out device D4, the 5th d type flip flop D5, the first counter Counter1, the second counter Counter2, the first phase inverter G1, second
Phase inverter G2, third phase inverter G5, the 4th phase inverter G7, the 5th phase inverter G9, hex inverter G13, the 7th phase inverter G14,
First nor gate G3, the second nor gate G4, third nor gate G6, four nor gate G8, the 5th nor gate G11, the first NAND gate
G10, the second NAND gate G12, first and door G15, the first monostable flipflop and the second monostable flipflop,
The input terminal of second phase inverter G2 connects the first detection signal, and output end connects the of the first nor gate G3
One input terminal；
The input terminal of first phase inverter G1 connects enable signal ENA, and the second of the first nor gate G3 of output end connection is defeated
Enter end；
The clock end of first d type flip flop D1 connects the first input of the clock end of the second d type flip flop D2, the second nor gate G4
The output end at end and the first nor gate G3, reset terminal connect the output end of the 7th phase inverter G14, Q output connection second
The second input terminal of nor gate G4, the first input end of the non-output end connection third nor gate G6 of Q；
The reset terminal of second d type flip flop D2 connects the enable signal ENA, the non-output end connection third nor gate G6 of Q
The second input terminal and the second nor gate G4 third input terminal；The output end connection third phase inverter G5's of second nor gate G4
The reset terminal of input terminal, third d type flip flop D3, four d flip-flop D4 and the 5th d type flip flop D5；
The output end of the Enable Pin connection third nor gate G6 of first counter Counter1, clock end connect clock letter
Number, the input terminal of the 7th phase inverter G14 of dominant bit output connection；
The Enable Pin of second counter Counter2 connects the output end of the 5th nor gate G11, described in clock end connection
Clock signal, the input terminal of the 5th phase inverter G9 of dominant bit output connection；
Input terminal connection the second detection signal of 4th phase inverter G7, output end connect the of four nor gate G8
One input terminal；
The second input terminal of four nor gate G8 connects the output end of the 5th phase inverter G9, and output end connects the 3rd D and touches
Send out the clock end of device D3；
The third that the input terminal of first monostable flipflop connects detects signal, and output end connects four d flip-flop
The clock end of D4；
The non-output ends of Q of the first input end connection third d type flip flop D3 of first NAND gate G10, the second input terminal connect
Connect the Q output of four d flip-flop D4；
The output end of the first input end connection third phase inverter G5 of 5th nor gate G11, the second input terminal connection the
The output end of one NAND gate G10, output end connect the first input end and first and the first of door G15 of the second NAND gate G12
Input terminal；
The second input terminal of second NAND gate G12 connects the non-output ends of Q of the 5th d type flip flop D5, output end connection the
The input terminal of hex inverter G13；
First connect the output end of the 5th phase inverter G9 with the second input terminal of door G15, and output end connects the voltage
The reset terminal of 4th comparator Comp4 in detection module；
Input terminal connection the 4th detection signal of second monostable flipflop, output end connect the 5th d type flip flop
The clock end of D5；
First d type flip flop D1, the second d type flip flop D2, third d type flip flop D3, four d flip-flop D4 and the 5th d type flip flop
The data input pin of D5 connects supply voltage；
The output end of the input terminal connection hex inverter G13 of the drive module, output end connect the rectifying tube
Grid.
Compare specifically, the voltage detection module further includes first comparator Comp1, the second comparator Comp2, third
Device Comp3, first voltage source, the second voltage source, tertiary voltage source, the first NDMOS pipes M1, the 2nd NDMOS pipes M2 and third
NDMOS pipe M3,
The drain electrode of first NDMOS pipes M1, the 2nd NDMOS pipes M2 and the 3rd NDMOS pipes M3 are all connected with the leakage of the rectifying tube
Pole, grid are all connected with supply voltage；
The in-phase input end of first comparator Comp1 connects the source electrode of the first NDMOS pipes M1, inverting input connection the
The forward end of one voltage source, output end export the first detection signal；
The in-phase input end of second comparator Comp2 connects the source electrode of the 2nd NDMOS pipes M2, inverting input connection the
The forward end of two voltage sources, output end output the second detection signal；
The in-phase input end of third comparator Comp3 connects the source electrode of the 3rd NDMOS pipes M3, inverting input connection the
The forward end of three voltage sources, output end export the third and detect signal；
First comparator Comp1, the second comparator Comp2 connect the voltage with the reset terminal of third comparator Comp3
The output end of second nor gate G4 in detection module；
First voltage source, the second voltage source connect the source electrode of the rectifying tube with the negative end in tertiary voltage source.
Specifically, the clock signal is generated by oscillator OSC, it is 320Khz that the oscillator OSC, which generates concussion frequency,
Square-wave signal as the clock signal.
Specifically, first monostable flipflop and the second monostable flipflop structure having the same,
First monostable flipflop includes the 8th phase inverter G16, the 9th phase inverter G17, the tenth phase inverter G18 and the
Six nor gate G19,
The first input end of the 6th nor gate G19 of input terminal connection of 8th phase inverter G16 is simultaneously monostable as described first
The input terminal of state trigger；
The input terminal of 9th phase inverter G17 connects the output end of the 8th phase inverter G16, and output end connects the tenth phase inverter
The input terminal of G18；
The second input terminal of 6th nor gate G19 connects the output end of the tenth phase inverter G18, and output end is as described the
The output end of one monostable flipflop.
Specifically, the first counter Comp1 and the second counter Comp2 is made of d type flip flop cascade.
Specifically, the drive module includes the cascade phase inverter of even number.
Beneficial effects of the present invention are：Control circuit proposed by the present invention, the rectification circuit for controlling electric power generation, knot
Structure is simple, and the power consumption of rectification circuit can be greatly lowered, and reduces the temperature of rectifier bridge, improves system reliability；Have
Lower conduction loss can improve generator whole efficiency, play the role of energy saving, clean environment firendly；Simultaneously by anti-
Electric current back flow circuit so that rectification circuit is more safe and reliable.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of synchronous commutating control circuit for preventing electric current from pouring in down a chimney proposed by the present invention.
Fig. 2 is the internal structure schematic diagram of the first monostable flipflop provided in embodiment.
Fig. 3 is a kind of work flow diagram of synchronous commutating control circuit for preventing electric current from pouring in down a chimney proposed by the present invention.
Specific implementation mode
In the following with reference to the drawings and specific embodiments, detailed description of the present invention technical solution.
A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney proposed by the present invention, for controlling in synchronous rectification system
Rectifying tube, below using using power MOSFET as the operation principle that the present invention will be described in detail for rectifying tube.
As shown in Figure 1, control circuit proposed by the present invention, including voltage detection module, Logic control module and driving mould
Block controls being switched on and off for power MOSFET by detecting the drain-source pressure difference of power MOSFET to generate control signal, wherein
Voltage detection module is used to detect the voltage difference between external power MOSFET drain electrodes and source electrode, judges power MOSFET parasitisms two
Pole pipe state, Logic control module generate power MOSFET minimums turn-on time and blanking time, while in minimum turn-on time
Interior detection power MOSFET current polarities avoid the generation electric current in minimum turn-on time from pouring in down a chimney phenomenon, it is thus also avoided that low current
In the case of power MOSFET drive waveforms shake, drive module is used to provide the gate driving of power MOSFET.
Voltage detection module be used for detect rectifying tube drain-source voltage and generate first detection signal, second detection signal,
Third detects signal and the 4th detection signal；A kind of realization circuit structure of voltage detecting circuit, including first are given in Fig. 1
Comparator Comp1, the second comparator Comp2, third comparator Comp3, the 4th comparator Comp4, first voltage source, the second electricity
Potential source, tertiary voltage source, the 4th voltage source, the first NDMOS pipes M1, the 2nd NDMOS pipes M2, the 3rd NDMOS pipes M3 and the 4th
NDMOS pipes M4, the drain electrode of the first NDMOS pipes M1, the 2nd NDMOS pipes M2, the 3rd NDMOS pipes M3 and the 4th NDMOS pipes M4 connect
The drain electrode of rectifying tube is connect, grid is all connected with supply voltage；The in-phase input end of first comparator Comp1 connects the first NDMOS
The source electrode of pipe M1, inverting input connect the forward end of first voltage source, and output end exports first detection signal；Second ratio
In-phase input end compared with device Comp2 connects the source electrode of the 2nd NDMOS pipes M2, and inverting input connects the forward direction of the second voltage source
End, output end output the second detection signal；The in-phase input end of third comparator Comp3 connects the source of the 3rd NDMOS pipes M3
Pole, inverting input connect the forward end in tertiary voltage source, and output end exports third and detects signal；4th comparator
The in-phase input end of Comp4 connects the source electrode of the 4th NDMOS pipes M4, and inverting input connects the forward end of the 4th voltage source,
The 4th detection signal of its output end output；First comparator Comp1, the second comparator Comp2 and third comparator Comp3's answers
The output end of second nor gate G4 in position end connection voltage detection module；The reset terminal connection voltage inspection of 4th comparator Comp4
Survey the output end of first and door G15 in module；First voltage source, the second voltage source, tertiary voltage source and the 4th voltage source it is negative
To the source electrode of end connection rectifying tube.
Wherein first comparator Comp1, the second comparator Comp2, third comparator Comp3 and the 4th comparator Comp4
Comparison voltage for voltage comparator, first comparator Comp1 is reset threshold voltage VTH3, the comparison of the second comparator Comp2
Voltage is off threshold voltage VTH2, the comparison voltage of third comparator Comp3 is turn-on threshold voltage VTH1, the 4th comparator
The comparison voltage of Comp4 is to pour in down a chimney threshold voltage VTH4.Turn-on threshold voltage VTH1, shutdown threshold voltage VTH2, reset threshold voltage
VTH3With pour in down a chimney threshold voltage VTH4It can be set by adjusting the size of voltage source.
As shown in Figure 1, Logic control module include the first d type flip flop D1, the second d type flip flop D2, third d type flip flop D3,
Four d flip-flop D4, the 5th d type flip flop D5, the first counter Counter1, the second counter Counter2, the first phase inverter
G1, the second phase inverter G2, third phase inverter G5, the 4th phase inverter G7, the 5th phase inverter G9, hex inverter G13, the 7th reverse phase
Device G14, the first nor gate G3, the second nor gate G4, third nor gate G6, four nor gate G8, the 5th nor gate G11, first
NAND gate G10, the second NAND gate G12, first and door G15, the first monostable flipflop and the second monostable flipflop, second is anti-
The input terminal of phase device G2 connects first detection signal, and output end connects the first input end of the first nor gate G3；First reverse phase
The input terminal of device G1 connects enable signal ENA, and output end connects the second input terminal of the first nor gate G3；First d type flip flop
The clock end of D1 connects the clock end of the second d type flip flop D2, the first input end of the second nor gate G4 and the first nor gate G3's
Output end, reset terminal connect the output end of the 7th phase inverter G14, and Q output connects the second input of the second nor gate G4
End, the first input end of the non-output end connection third nor gate G6 of Q；The reset terminal of second d type flip flop D2 connects enable signal
The third input terminal of the second input terminal and the second nor gate G4 of the non-output end connection third nor gate G6 of ENA, Q；Second or
Input terminal, third d type flip flop D3, four d flip-flop D4 and the 5th D triggerings of the output end connection third phase inverter G5 of NOT gate G4
The reset terminal of device D5；The output end of the Enable Pin connection third nor gate G6 of first counter Counter1, clock end connection
Clock signal, the input terminal of the 7th phase inverter G14 of dominant bit output connection；The Enable Pin of second counter Counter2 connects
The output end of 5th nor gate G11, clock end connect clock signal, the input of the 5th phase inverter G9 of dominant bit output connection
End；Input terminal connection the second detection signal of 4th phase inverter G7, output end connect the first input end of four nor gate G8；
The second input terminal of four nor gate G8 connects the output end of the 5th phase inverter G9, and output end connects third d type flip flop D3's
Clock end；The input terminal connection third of first monostable flipflop detects signal, output end connect four d flip-flop D4 when
Zhong Duan；The non-output ends of Q of the first input end connection third d type flip flop D3 of first NAND gate G10, the second input terminal connection the
The Q output of four d flip-flop D4；The output end of the first input end connection third phase inverter G5 of 5th nor gate G11, second
Input terminal connect the first NAND gate G10 output end, output end connect the second NAND gate G12 first input end and first with
The first input end of door G15；The second input terminal of second NAND gate G12 connects the non-output ends of Q of the 5th d type flip flop D5, defeated
Outlet connects the input terminal of hex inverter G13；First connect the output of the 5th phase inverter G9 with the second input terminal of door G15
End, output end connect the reset terminal of the 4th comparator Comp4 in voltage detection module；The input terminal of second monostable flipflop
The 4th detection signal is connected, output end connects the clock end of the 5th d type flip flop D5；First d type flip flop D1, the second d type flip flop
The data input pin connection supply voltage of D2, third d type flip flop D3, four d flip-flop D4 and the 5th d type flip flop D5；6th is anti-
The input terminal of the output end connection drive module of phase device G13.
Drive module includes output-stage power driving B0, and wherein the input terminal of output-stage power driving B0 is as drive module
Input terminal connection hex inverter G13 output end, grid of the output end as the output end connection rectifying tube of drive module
Pole, output-stage power driving B0 can be made of the cascade phase inverter of even number.
In some embodiments, clock signal can be generated by oscillator OSC, such as generate concussion frequency using oscillator OSC
For 320Khz square-wave signal as clock signal.
The digit of first counter Comp1 and the second counter Comp2 can adjust according to the design needs, gate time
Can arbitrarily it be arranged, the first counter Comp1 and the second counter Comp2 can be cascaded by d type flip flop and be constituted.
First monostable flipflop and the second monostable flipflop can as shown in Figure 2 be given with structure having the same
A kind of circuit implementation of first monostable flipflop, including the 8th phase inverter G16, the 9th phase inverter G17, the tenth phase inverter
The input terminal of G18 and the 6th nor gate G19, the 8th phase inverter G16 connects the first input end of the 6th nor gate G19 and as the
The input terminal of one monostable flipflop；The input terminal of 9th phase inverter G17 connects the output end of the 8th phase inverter G16, output
The input terminal of the tenth phase inverter G18 of end connection；The second input terminal of 6th nor gate G19 connects the output of the tenth phase inverter G18
End, output end of the output end as the first monostable flipflop.
First comparator Comp1, the first d type flip flop D1, the second d type flip flop D2, the first counter Counter1, second are instead
Phase device G2, third phase inverter G5, the 7th phase inverter G14, the second nor gate G4 and third nor gate G6 constitute reseting logic circuit,
When the power MOSFET drain-source pressure differences detected are more than reset threshold voltage VTH3When, the first counter Counter1 is started counting up,
During this period of time all logics of chip and comparator reset.
Second voltage comparator Comp2, the 4th phase inverter G7, the 5th phase inverter G9, third nor gate G8, the 3rd D triggerings
Device D3 and the second counter Counter2 constitute minimum turn-on time circuit, when the power MOSFET drain-source pressure differences detected are less than
Turn-on threshold voltage VTH1When, power MOSFET ON, the second counter Counter2 is started counting up, when the second counter
The second comparator Comp2 just starts to detect whether power MOSFET reaches shutdown when the highest order output MSB of Counter2 is got higher
Threshold voltage VTH2。
Third comparator Comp3, the first monostable flipflop, four d flip-flop D4, the first NAND gate G10 and the 5th or
NOT gate G11, which is constituted, to be judged to open power MOSFET circuit, when the power MOSFET detected meets unlocking condition, that is, is detected
Power MOSFET drain-source pressure differences are less than turn-on threshold voltage VTH1When, the first monostable flipflop generates the height of a narrower width
Pulse, four d flip-flop D4 overturnings, drives B0 to open power MOSFET by output-stage power.
4th comparator Comp4, the second monostable flipflop, the 5th d type flip flop D5 and first and door G15 constitute anti-electric current
Back flow circuit, power MOSFET mono- are connected, and the second counter Counter2 is started counting up, and power MOSFET forces the second meter of conducting
Number device Counter2 gate times, the 4th comparator Comp4, which is during this period of time detected, flows through open MOSFET current polarities.
Such as the work flow diagram that Fig. 3 is the present invention, a kind of synchronous commutating control circuit provided by the invention is integrated into core
In piece, control circuit starts to work and (enters ready mode) after enable signal EN is high (i.e. enable pin is enabled), simultaneously
Detection chip supply voltage (i.e. supply voltage VDD) and environment temperature it is whether normal；When supply voltage and environment temperature meet condition
(i.e. power MOSFET drain-sources pressure difference is more than reset threshold voltage V to the reset signal of first comparator Comp1 waitings laterTH3), work as inspection
The power MOSFET drain-source pressure differences measured are more than reset threshold voltage VTH3, all logic resets of chip, and trigger the first counter
Counter1 is counted, and all logics do not work during this period of time；It undergoes first after the first counter Counter1 gate times
Whether comparator Comp1 and logic circuit detection power MOSFET drain-sources pressure difference are in shutdown threshold voltage VTH2With reset threshold electricity
Press VTH3Between, logic exits reset if meeting condition, starts to detect whether power MOSFET drain-sources pressure difference meets turn-on condition
(i.e. power MOSFET drain-sources pressure difference is less than turn-on threshold voltage VTH1)；When third comparator Comp3 detects power MOSFET leakages
Source pressure difference is less than turn-on threshold voltage VTH1When, power MOSFET ON, the 2nd Counter2 is started counting up, and power MOSFET is strong
System conducting, detections of the second comparator Comp2 of shielding to power MOSFET drain-source pressure differences, the 4th comparator Comp4 start to detect
Power MOSFET current polarities are flowed through, are poured in down a chimney using whether the 4th comparator Comp4 detection power MOSFET drain-sources pressure differences reach
Threshold voltage VTH4, not up to pour in down a chimney threshold voltage VTH4Indicate that electric current does not pour in down a chimney phenomenon at this time, then the second counter
Second comparator Comp2 starts to detect whether power MOSFET drain-sources pressure difference is more than shutdown threshold voltage after Counter2 meters are full
VTH2, power MOSFET is closed if power MOSFET drain-source pressure differences meet condition；4th comparator Comp4 detects power
MOSFET drain-source pressure differences, which reach, pours in down a chimney threshold voltage VTH4Indicate that electric current pours in down a chimney phenomenon at this time, then horse back switch-off power
MOSFET；Then reset signal Reset is started waiting for, enters above-mentioned flow again when next reset signal Reset comes.
In conclusion the present invention proposes a kind of control circuit for controlling the rectification circuit of electric power generation, pass through inspection
Power scale MOSFET drain-sources pressure difference detects whether the body diode of power MOSFET is connected, to control power MOSFET ON
And shutdown, when body diode is connected, driving output is high, and the raceway groove of power MOSFET ON, power MOSFET flows through high current,
When body diode is reverse-biased, driving output is low, and power MOSFET pressure resistances can substantially be dropped using control circuit provided by the invention
The power consumption of low synchronous rectification system, reduces the temperature of rectifier bridge, improves system reliability.
Rectified power MOSFET pipes are operated in backward resistance area in the present invention, are mainly power MOSFET in switching process
Channel resistance flow through high current, realize lower conduction loss, improve generator whole efficiency, play energy saving, clear
The effect of clean environmental protection；Simultaneously in power MOSFET ON, anti-electric current back flow circuit is added so that rectification circuit is safer
Reliably.
It is understood that the present invention is not limited to the accurate configuration being illustrated above and components.Claims are not being departed from
Protection domain on the basis of, can be to method and structure above the step of sequence, details and operation make various modifications, change and
Optimization.
Claims (6)
1. a kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney, which is characterized in that for controlling in synchronous rectification system
Rectifying tube, including voltage detection module, Logic control module and drive module,
The voltage detection module is used to detect the drain-source voltage of the rectifying tube and generates first detection signal, the second detection letter
Number, third detection signal and the 4th detection signal；
The voltage detection module includes the 4th NDMOS pipes (M4), the 4th comparator (Comp4) and the 4th voltage source, the 4th ratio
Compared with the source electrode that the in-phase input end of device (Comp4) connects the 4th NDMOS pipes (M4), inverting input connects the 4th voltage source
Forward end, output end output the 4th detection signal；The grid that 4th NDMOS manages (M4) connects supply voltage, drain electrode
Connect the drain electrode of the rectifying tube；The negative end of 4th voltage source connects the source electrode of the rectifying tube；
The Logic control module includes the first d type flip flop (D1), the second d type flip flop (D2), third d type flip flop (D3), the 4th D
Trigger (D4), the 5th d type flip flop (D5), the first counter (Counter1), the second counter (Counter2), the first reverse phase
Device (G1), the second phase inverter (G2), third phase inverter (G5), the 4th phase inverter (G7), the 5th phase inverter (G9), hex inverter
(G13), the 7th phase inverter (G14), the first nor gate (G3), the second nor gate (G4), third nor gate (G6), four nor gate
(G8), the 5th nor gate (G11), the first NAND gate (G10), the second NAND gate (G12), first and door (G15), the first monostable
Trigger and the second monostable flipflop,
The input terminal of second phase inverter (G2) connects the first detection signal, and output end connects the of the first nor gate (G3)
One input terminal；
The input terminal connection enable signal (ENA) of first phase inverter (G1), output end connect the second of the first nor gate (G3)
Input terminal；
The clock end of first d type flip flop (D1) connect the clock end of the second d type flip flop (D2), the second nor gate (G4) it is first defeated
Enter the output end of end and the first nor gate (G3), reset terminal connects the output end of the 7th phase inverter (G14), and Q output connects
Connect the second input terminal of the second nor gate (G4), the first input end of the non-output end connection third nor gates (G6) of Q；
The reset terminal of second d type flip flop (D2) connects the enable signal (ENA), and the non-output ends of Q connect third nor gate
(G6) the third input terminal of the second input terminal and the second nor gate (G4)；The output end connection third of second nor gate (G4) is anti-
The input terminal of phase device (G5), the reset terminal of third d type flip flop (D3), four d flip-flop (D4) and the 5th d type flip flop (D5)；
The output end of the Enable Pin connection third nor gate (G6) of first counter (Counter1), clock end connect clock letter
Number, the input terminal of dominant bit output the 7th phase inverter (G14) of connection；
The Enable Pin of second counter (Counter2) connects the output end of the 5th nor gate (G11), described in clock end connection
Clock signal, the input terminal of dominant bit output the 5th phase inverter (G9) of connection；
Input terminal connection the second detection signal of 4th phase inverter (G7), output end connect the of four nor gate (G8)
One input terminal；
Second input terminal of four nor gate (G8) connects the output end of the 5th phase inverter (G9), and output end connects the 3rd D and touches
Send out the clock end of device (D3)；
The third that the input terminal of first monostable flipflop connects detects signal, and output end connects four d flip-flop (D4)
Clock end；
The non-output ends of Q of the first input end connection third d type flip flop (D3) of first NAND gate (G10), the second input terminal connect
Connect the Q output of four d flip-flop (D4)；
The output end of the first input end connection third phase inverter (G5) of 5th nor gate (G11), the second input terminal connection the
The output end of one NAND gate (G10), output end connect the second NAND gate (G12) first input end and first with door (G15)
First input end；
Second input terminal of the second NAND gate (G12) connects the non-output ends of Q of the 5th d type flip flop (D5), output end connection the
The input terminal of hex inverter (G13)；
First connect the output end of the 5th phase inverter (G9) with the second input terminal of door (G15), and output end connects the voltage
The reset terminal of 4th comparator (Comp4) in detection module；
Input terminal connection the 4th detection signal of second monostable flipflop, output end connect the 5th d type flip flop (D5)
Clock end；
First d type flip flop (D1), the second d type flip flop (D2), third d type flip flop (D3), four d flip-flop (D4) and the 5th D are touched
The data input pin for sending out device (D5) connects supply voltage；
The output end of the input terminal connection hex inverter (G13) of the drive module, output end connect the rectifying tube
Grid.
2. according to claim 1 prevent the synchronous commutating control circuit that electric current pours in down a chimney, which is characterized in that the voltage inspection
Survey module further include first comparator (Comp1), the second comparator (Comp2), third comparator (Comp3), first voltage source,
The second voltage source, tertiary voltage source, the first NDMOS pipes (M1), the 2nd NDMOS pipes (M2) and the 3rd NDMOS pipes (M3),
The drain electrode of first NDMOS pipes (M1), the 2nd NDMOS pipes (M2) and the 3rd NDMOS pipes (M3) is all connected with the rectifying tube
Drain electrode, grid are all connected with supply voltage；
The in-phase input end of first comparator (Comp1) connects the source electrode of the first NDMOS pipes (M1), inverting input connection the
The forward end of one voltage source, output end export the first detection signal；
The in-phase input end of second comparator (Comp2) connects the source electrode of the 2nd NDMOS pipes (M2), inverting input connection the
The forward end of two voltage sources, output end output the second detection signal；
The in-phase input end of third comparator (Comp3) connects the source electrode of the 3rd NDMOS pipes (M3), inverting input connection the
The forward end of three voltage sources, output end export the third and detect signal；
First comparator (Comp1), the second comparator (Comp2) connect the electricity with the reset terminal of third comparator (Comp3)
Press the output end of the second nor gate (G4) in detection module；
First voltage source, the second voltage source connect the source electrode of the rectifying tube with the negative end in tertiary voltage source.
3. according to claim 1 prevent the synchronous commutating control circuit that electric current pours in down a chimney, which is characterized in that the clock letter
It number is generated by oscillator (OSC), it is the square-wave signal of 320Khz as the clock that the oscillator (OSC), which generates concussion frequency,
Signal.
4. according to claim 1 prevent the synchronous commutating control circuit that electric current pours in down a chimney, which is characterized in that described first is single
Steady state trigger and the second monostable flipflop structure having the same,
First monostable flipflop include the 8th phase inverter (G16), the 9th phase inverter (G17), the tenth phase inverter (G18) and
6th nor gate (G19),
The first input end of input terminal the 6th nor gate (G19) of connection of 8th phase inverter (G16) is simultaneously monostable as described first
The input terminal of state trigger；
The input terminal of 9th phase inverter (G17) connects the output end of the 8th phase inverter (G16), and output end connects the tenth phase inverter
(G18) input terminal；
Second input terminal of the 6th nor gate (G19) connects the output end of the tenth phase inverter (G18), and output end is as described the
The output end of one monostable flipflop.
5. according to claim 1 prevent the synchronous commutating control circuit that electric current pours in down a chimney, which is characterized in that first meter
Number device (Comp1) and the second counter (Comp2) are made of d type flip flop cascade.
6. according to claim 1 prevent the synchronous commutating control circuit that electric current pours in down a chimney, which is characterized in that the driving mould
Block includes the cascade phase inverter of even number.
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