CN203883456U - Multiplexing detection circuit, switching power supply controller and fly-back converter - Google Patents
Multiplexing detection circuit, switching power supply controller and fly-back converter Download PDFInfo
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- CN203883456U CN203883456U CN201420160972.2U CN201420160972U CN203883456U CN 203883456 U CN203883456 U CN 203883456U CN 201420160972 U CN201420160972 U CN 201420160972U CN 203883456 U CN203883456 U CN 203883456U
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Abstract
The utility model relates to a multiplexing detection circuit, an acquisition circuit acquires the voltage between a filtering unit and a rectifying unit, the voltage between the filtering unit and the rectifying unit is proportional to the input voltage, a negative temperature coefficient thermistor in the acquisition circuit acquires environmental temperature information, a BNO/OTP pin of a control circuit acquires the voltage between the filtering unit and the rectifying unit and the environmental temperature information in a time sharing manner, and the detection of the voltage and the environmental temperature information are achieved, the control of a power switch tube is achieved through the output signal of an OUT pin of the control circuit, the protection of too low input voltage and the protection of two high environmental temperature are achieved, and the problem existing in the prior art that two independent end points are needed to achieve the protection of too low input voltage and the protection of two high environmental temperature is solved. The utility model also discloses a switching power supply controller and a fly-back converter.
Description
Technical field
The utility model relates to electric and electronic technical field, relates in particular to a kind of multiplexing testing circuit, switch power controller and flyback converter.
Background technology
Fig. 1 is a kind of typical flyback converter in electric pressure converter, comprising: alternating-current voltage source VAC, filter unit 101, rectification unit 102, the first capacitor C 1, the first resistance R 1, the second capacitor C 2, the first diode D1, auxiliary winding 103, control circuit 104, the 3rd capacitor C 3, the second resistance R 2, the 3rd resistance R 3, negative tempperature coefficient thermistor R
n, first side winding 105, power switch pipe Q, sampling resistor Rs, secondary side winding 106, the second diode D2, the 4th resistance R 4, the 5th resistance R 5, the 4th capacitor C 4, optocoupler unit 107, and the 3rd diode D3.
Wherein, the BNO pin of control circuit 104 receives the voltage that Acquisition Circuit that the second resistance R 2 and the 3rd resistance R 3 form gathers, the voltage of this voltage and alternating voltage VAC output is proportional, when the magnitude of voltage of described collection is during lower than a preset value, control circuit 104 turn-offs by the output signal power ratio control switching tube Q of OUT pin, and object is that avoiding filling parallel operation is operated in the too low abnormal conditions of input voltage and causes damage.
The external negative tempperature coefficient thermistor R of OTP pin of control circuit 104
n, the electric current of the control circuit 104 inside negative tempperature coefficient thermistor R that flows through
nproduce voltage, when this voltage is less than a threshold voltage, control circuit 104 turn-offs by the output signal power ratio control switching tube Q of OUT pin, can avoid the too high abnormal conditions of working temperature of transducer.
But control circuit of the prior art 104 needs two, independently terminal B NO pin and OTP pin are realized the too low protection of input voltage and the too high protection of ambient temperature.
Utility model content
In view of this, the utility model provides a kind of multiplexing testing circuit, switch power controller and flyback converter, to solve in prior art, needs two individual end points to realize the problem of the too low protection of input voltage and the too high protection of ambient temperature.
To achieve these goals, the existing scheme proposing is as follows:
A kind of multiplexing testing circuit, be applied to flyback converter, described flyback converter comprises: the power switch pipe that filter unit, the rectification unit being connected with described filter unit, first side winding, secondary side winding, auxiliary winding and input are connected with described first side winding Same Name of Ends; Described multiplexing testing circuit comprises:
The Acquisition Circuit that input is connected with the tie point of described filter unit and rectification unit; Described Acquisition Circuit comprises negative tempperature coefficient thermistor;
Timesharing detects the control circuit of input voltage and ambient temperature; The BNO/OTP pin of described control circuit is connected with described Acquisition Circuit output, and the OUT pin of described control circuit is connected with the control end of described power switch pipe.
Preferably, described Acquisition Circuit comprises:
One end is as the first resistance of described Acquisition Circuit input;
The second resistance that one end is connected with the described first resistance other end; The other end ground connection of described the second resistance;
The first diode that the tie point of anodal and described the first resistance and the second resistance is connected;
The second diode that anodal and described the first diode cathode is connected;
The negative tempperature coefficient thermistor that one end is connected with described the second diode cathode; The other end ground connection of described negative tempperature coefficient thermistor;
The first electric capacity that one end is connected with the tie point of described the first resistance and the second resistance; The other end ground connection of described the first electric capacity; The tie point of described the first resistance, the second resistance and the first electric capacity is as the output of described Acquisition Circuit.
Preferably, described control circuit comprises:
One end receives the first current source of biasing voltage signal;
The first switch that input is connected with the described first current source other end;
The first comparator that in-phase input end is connected with described the first output switching terminal;
The second switch that one end is connected with the first inverting input of described the first comparator; The other end of described second switch receives 1V voltage signal;
The 3rd switch that one end is connected with the second inverting input of described the first comparator; The other end of described the 3rd switch receives 0.1V voltage signal;
The 4th switch that one end is connected with described the first output switching terminal; The tie point of described the first comparator, the first switch and the 4th switch is as described control circuit BNO/OTP pin;
The 5th switch that one end is connected with described the 4th switch other end;
The second comparator that normal phase input end is connected with the tie point of described the 4th switch and the 5th switch;
The 6th switch that one end is connected with described the second comparator inverting input respectively and minion are closed; The other end of described the 6th switch receives 0.325V or 0.3V voltage signal; The other end that described minion is closed receives 1V voltage signal;
Power supply;
The second current source that one end is connected with described the 5th switch other end; The other end of described the second current source is connected with described power supply;
The 8th switch and the first electric capacity that one end is connected with the tie point of described the 5th switch and the second current source respectively; The other end ground connection of described the 8th switch and the first electric capacity;
Receive primary side current detection signal and feedback loading detection signal, and the equal sub-control circuit of sequential that is connected with described the first comparator output terminal and the second comparator output terminal respectively of input; The output of the equal sub-control circuit of described sequential is as the OUT pin of described control circuit.
Preferably, the equal sub-control circuit of described sequential comprises:
Input is respectively as the first logic controller of the equal sub-control circuit input of described sequential;
Receive primary side current detection signal and feedback loading detection signal, and the second logic controller being connected with the output of described the first logic controller;
The voltage and current reference module, oscillator and the driver that are connected with described the second logic controller respectively; The output of described driver is as the output of the equal sub-control circuit of described sequential.
Preferably, in described control circuit, the equal sub-control circuit of sequential also comprises:
Generate and export the 3rd comparator of described primary side current detection signal; The normal phase input end of described the 3rd comparator receives reference voltage signal; The CS pin that the inverting input of described the 3rd comparator receives described control circuit receives signal and line voltage compensation signal;
Generate and export the 4th comparator of described feedback loading detection signal; The normal phase input end of described the 4th comparator is as the COMP pin of described control circuit; The CS pin that the inverting input of described the 4th comparator receives described control circuit receives signal and harmonic compensation signal.
Preferably, described the first logic controller comprises:
The OTP enable circuits that input is connected with current reference module output with described the first comparator output terminal, the second comparator output terminal and voltage respectively;
The BNO enable circuits that input is connected with current reference module output with described the first comparator output terminal, the second comparator output terminal and voltage respectively; Described OTP enable circuits and described BNO enable circuits interconnect;
Input be connected with described OTP enable circuits output and BNO enable circuits output respectively with door, described with the output of door as the output of described the first logic controller.
Preferably, described OTP enable circuits comprises:
The first not gate that input is connected with described the first comparator output terminal;
The first NOR gate that input is connected with described the first non-gate output terminal and described BNO enable circuits respectively;
The first d type flip flop that CLK pin is connected with described the first NOR gate output; The D pin of described the first d type flip flop is connected with described power supply; The QB pin of described the first d type flip flop is connected with described BNO enable circuits;
The second not gate that input is connected with the output of described the second comparator;
The NAND gate that input is connected with current reference module output with output and the described voltage of described the second not gate respectively; The output of described NAND gate is connected with the R pin of described the first d type flip flop;
That input is connected with the QB pin of described the first d type flip flop and described the first comparator output terminal respectively or door; Output described or door is the output of described OTP enable circuits.
Preferably, described BNO enable circuits comprises:
The second d type flip flop that CLK pin is connected with described the first comparator output terminal; The D pin of described the second d type flip flop is connected with described power supply; The SB pin of described the second d type flip flop is connected with current reference module output with described voltage; The RB pin of described the second d type flip flop is connected with the QB pin of described the first d type flip flop; The QB pin of described the second d type flip flop is connected with described the first NOR gate input;
The second NOR gate that input is connected with QB pin and second comparator output terminal of described the second d type flip flop respectively; The output of described the second NOR gate is the output of described BNO enable circuits.
A kind of switch power controller, be applied to flyback converter, described flyback converter comprises: the power switch pipe that filter unit, the rectification unit being connected with described filter unit, first side winding, secondary side winding, auxiliary winding and input are connected with described first side winding Same Name of Ends; Described switch power controller comprises:
Grounding pin;
With auxiliary winding coupled and for described switch power controller, provide the VCC power pins of power supply;
By described power switch pipe and described first side winding, be coupled, detect the first side winding current detecting pin CS of the electric current flowing through in described first side winding;
The feedback signal that detects the output situation being coupled with described secondary side winding detects pin COMP;
Be coupled with the control end of described power switch pipe and control the output pin OUT of conducting and the cut-off of described power switch pipe;
Timesharing detects the BON/OTP multiplexing pins of input voltage and ambient temperature;
And as above-mentioned control circuit as described in arbitrary.
A flyback converter, comprising:
Receive the filter unit of AC supply voltage signal;
The rectification unit being connected with described filter unit;
The first electric capacity and the first resistance that one end is connected with described rectification unit output respectively; The other end ground connection of described the first electric capacity;
The first side winding that different name end is connected with described rectification unit output;
The power switch pipe that input is connected with the Same Name of Ends of described first side winding;
The second electric capacity being connected with the described first resistance other end; The other end ground connection of described the second electric capacity;
The first diode that negative pole is connected with described the first resistance and the second electric capacity tie point;
The auxiliary winding that Same Name of Ends is connected with described the first diode cathode; The different name end ground connection of described auxiliary winding;
Above-mentioned arbitrary described multiplexing testing circuit; Described in described multiplexing testing circuit, the VCC pin of control circuit is connected with the negative pole of described the first diode;
The second resistance being connected with the CS pin of control circuit described in described multiplexing testing circuit; Described the second resistance is connected with the output of described power switch pipe with the tie point of described control circuit CS pin, the other end ground connection of described the second resistance;
The optocoupler unit that the first output is connected with the COMP pin of control circuit described in described multiplexing testing circuit;
The second diode that negative pole is connected with described optocoupler unit the second output; The plus earth of described the second diode;
The 3rd resistance that one end is connected with described optocoupler unit input;
The 3rd diode that negative pole is connected with described the 3rd resistance other end;
The secondary side winding that Same Name of Ends is connected with described the 3rd diode cathode; The different name end ground connection of described secondary side winding;
The 4th resistance and the 3rd electric capacity that one end is connected with described the 3rd diode cathode; The equal ground connection of the other end of described the 4th resistance and the 3rd electric capacity.
From above-mentioned technical scheme, can find out, the disclosed multiplexing testing circuit of the utility model, by Acquisition Circuit, gather the voltage between filter unit and rectification unit, and the voltage between described filter unit and rectification unit becomes certain proportionate relationship with input voltage, and gather ambient temperature information by the negative tempperature coefficient thermistor in described Acquisition Circuit, again by voltage and ambient temperature information between filter unit described in the BNO/OTP pin acquisition time of control circuit and rectification unit, to realize respectively the detection to both, and the output signal of the OUT pin by described control circuit realizes the control for power switch pipe, finally realize respectively the too low protection of input voltage and the too high protection of ambient temperature, having solved prior art needs two individual end points to realize the problem of the too low protection of input voltage and the too high protection of ambient temperature.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the flyback converter circuit diagram of this prior art;
Fig. 2 is the disclosed flyback converter circuit diagram of the utility model embodiment;
Fig. 3 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Fig. 4 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Fig. 5 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Fig. 6 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Fig. 7 is disclosed the first logic controller circuit diagram of another embodiment of the utility model;
Fig. 8 is disclosed the first logic controller circuit diagram of another embodiment of the utility model;
Fig. 9 is the disclosed signal timing diagram of another embodiment of the utility model;
Figure 10 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Figure 11 is the disclosed flyback converter circuit diagram of another embodiment of the utility model.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The utility model provides a kind of multiplexing testing circuit, to solve prior art, needs two individual end points to realize the problem of the too low protection of input voltage and the too high protection of ambient temperature.
Concrete, as shown in Figure 2, described multiplexing testing circuit, be applied to flyback converter, described flyback converter comprises: the power switch pipe Q that filter unit 201, the rectification unit 202 being connected with filter unit 201, first side winding 203, secondary side winding 204, auxiliary winding 205 and input are connected with first side winding 203 Same Name of Ends; Described multiplexing testing circuit comprises:
The Acquisition Circuit 206 that input is connected with the tie point of filter unit 201 and rectification unit 202; Acquisition Circuit 206 comprises negative tempperature coefficient thermistor;
The control circuit 207 that BNO/OTP pin is connected with Acquisition Circuit 206 outputs; The OUT pin of control circuit 207 is connected with the control end of power switch pipe Q.
Concrete operation principle is:
The voltage that Acquisition Circuit 206 gathers between filter unit 201 and rectification unit 202, and the voltage between described filter unit 201 and rectification unit 202 becomes certain proportionate relationship with input voltage VAC, and gather ambient temperature information by the described negative tempperature coefficient thermistor in Acquisition Circuit 206, again by voltage and ambient temperature information between filter unit 201 described in the BNO/OTP pin acquisition time of control circuit 207 and rectification unit 202, to realize respectively the detection to both, and the output signal of passing through the OUT pin of control circuit 207 realizes the control for power switch pipe Q, finally realize respectively the too low protection of input voltage and the too high protection of ambient temperature, having solved prior art needs two individual end points to realize the problem of the too low protection of input voltage and the too high protection of ambient temperature.
Preferably, as shown in Figure 3, Acquisition Circuit 204 comprises:
One end is as the first resistance R 1 of Acquisition Circuit 206 inputs;
The second resistance R 2 that one end is connected with first resistance R 1 other end; The other end ground connection of the second resistance R 2;
Anodal the first diode D1 being connected with the tie point of the first resistance R 1 and the second resistance R 2;
Anodal the second diode D2 being connected with the first diode D1 negative pole;
The negative tempperature coefficient thermistor R that one end is connected with the second diode D2 negative pole
n; Negative tempperature coefficient thermistor R
nother end ground connection;
The first capacitor C 1 that one end is connected with the tie point of the first resistance R 1 and the second resistance R 2; The other end ground connection of the first capacitor C 1; The tie point of the first resistance R 1, the second resistance R 2 and the first capacitor C 1 is as the output of Acquisition Circuit 206.
Concrete operation principle is:
Preferably, as shown in Figure 4, control circuit 207 comprises:
One end receives the first current source 401 of biasing voltage signal Vbias;
The first switch S 1 that input is connected with first current source 401 other ends;
The first comparator A1 that in-phase input end is connected with the first switch S 1 output;
The second switch S2 that one end is connected with the first inverting input of the first comparator A1; The other end of second switch S2 receives 1V voltage signal;
The 3rd switch S 3 that one end is connected with the second inverting input of the first comparator A1; The other end of the 3rd switch S 3 receives 0.1V voltage signal;
The 4th switch S 4 that one end is connected with the first switch S 1 output; The tie point of the first comparator A1, the first switch S 1 and the 4th switch S 4 is as the BNO/OTP pin of control circuit 207;
The 5th switch S 5 that one end is connected with the 4th switch S 4 other ends;
The second comparator A2 that normal phase input end is connected with the tie point of the 4th switch S 4 and the 5th switch S 5;
The 6th switch S 6 that one end is connected with the second comparator A2 inverting input respectively and minion are closed S7; The other end of the 6th switch S 6 receives 0.325V or 0.3V voltage signal; The other end that minion is closed S7 receives 1V voltage signal;
Power supply;
The second current source 402 that one end is connected with the 5th switch S 5 other ends; The other end of the second current source 402 is connected with described power supply;
The 8th switch S8 and the first capacitor C 1 that one end is connected with the tie point of the 5th switch S 5 and the second current source 402 respectively; The other end ground connection of the 8th switch S8 and the first capacitor C 1;
Receive primary side current detection signal VCS and feedback loading detection signal FB, and the equal sub-control circuit 403 of sequential that is connected with the first comparator A1 output and the second comparator A2 output respectively of input; The output of the equal sub-control circuit 403 of sequential is as the OUT pin of control circuit 207.
Concrete operation principle is:
Described power supply is the internal work power supply of control circuit 207 place chips, and described internal work power supply is that the outer power voltage that described chip receives obtains after conversion.
The first comparator A1 is the too low and multiplexing comparator of input voltage zero passage of temperature; The second comparator A2 is that line brownout and OTP detect the multiplexing comparator of timing.
When the first comparator A1 detects voltage between filter unit 201 and rectification unit 202 in positive half cycle, also be that input voltage VAC is when positive half cycle, control circuit 207 is by the BNO/OTP pin detection line voltage as multiplexing end, when the line voltage detecting when multiplexing end is less than certain threshold voltage, the second comparator A2 turn-offs power switch pipe Q, realizes the too low protection of input voltage;
When the first comparator A1 detects voltage between filter unit 201 and rectification unit 202 in negative half period, also be that input voltage VAC is when negative half period, control circuit 207 is by the BNO/OTP pin testing environment temperature as multiplexing end, and control circuit 207 flows out a road electric current at negative tempperature coefficient thermistor R
nupper generation pressure drop, when the line voltage detecting when multiplexing end is less than certain threshold voltage, the first comparator A1 turn-offs power switch pipe Q, realizes the too low protection of ambient temperature.
Preferably, as shown in Figure 5, the equal sub-control circuit 403 of sequential comprises:
Input is respectively as the first logic controller 501 of equal sub-control circuit 403 inputs of sequential;
Receive primary side current detection signal VCS and feedback loading detection signal FB, and the second logic controller 502 being connected with the output of the first logic controller 501;
The voltage being connected with the second logic controller 502 respectively and current reference module 503, oscillator 504 and driver 505; The output of driver 505 is as the output of the equal sub-control circuit 403 of sequential.
Output output error signal Fault to the second logic controller 502 of the first logic controller 501, voltage and current reference module 503 output references are set up signal BG to the second logic controller 502, oscillator 504 clock signal CLK to the second logic controllers 502, the second logic controller 502 output pulse-modulated signal PWM are to driver 505, and driver 505 outputs signal to OUT pin.
Figure 5 shows that a kind of specific implementation form of the equal sub-control circuit 403 of sequential, by the first logic controller 501, the second logic controller 502, voltage and current reference module 503, oscillator 504 and driver 505, realize the time-sharing facility of control circuit 207; In concrete practical application, can also adopt other components and parts or connected mode to realize described time-sharing facility according to its concrete applied environment, and be not specifically limited herein.
Preferably, as shown in Figure 6, the equal sub-control circuit 403 of sequential in control circuit 207 also comprises:
Generate and export the 3rd comparator A3 of described primary side current detection signal VCS; The normal phase input end of the 3rd comparator A3 receives reference voltage signal Vref; The CS pin of the inverting input reception control circuit 207 of the 3rd comparator A3 receives signal and line voltage compensation signal Saw Comp;
Generate and export the 4th comparator A4 of described feedback loading detection signal FB; The normal phase input end of the 4th comparator A4 is as the COMP pin of control circuit 207; The CS pin of the inverting input reception control circuit 207 of the 4th comparator A4 receives signal and harmonic compensation signal Slop Comp.
The signal that the signal that control circuit 207 receives according to COMP pin and CS pin receive decides the duty ratio of OUT pin output signal, so that the output voltage that whole flyback converter can be stable.
Preferably, as shown in Figure 7, the first logic controller 501 comprises:
The OTP enable circuits 701 that input is connected with current reference module output with described the first comparator output terminal, the second comparator output terminal and voltage respectively;
The BNO enable circuits 702 that input is connected with current reference module output with described the first comparator output terminal, the second comparator output terminal and voltage respectively; OTP enable circuits 701 interconnects with BNO enable circuits 702;
Input be connected with OTP enable circuits 701 outputs and BNO enable circuits 702 outputs respectively with door 703, with the output of door 703 output as the first logic controller 501.
Concrete operation principle is:
OTP enable circuits 701 receives the zero cross signal Z0 of described the first comparator output, the benchmark of the timing signal BT of the second comparator output, voltage and the output of current reference module is set up signal BG, and the line brownout enable signal BNO_ENB of BNO enable circuits 702 outputs, output excess temperature enable signal OTP_ENB and excess temperature signal OTP.
BNO enable circuits 702 receives the zero cross signal Z0 of described the first comparator output, the benchmark of the timing signal BT of the second comparator output, voltage and the output of current reference module is set up signal BG, and excess temperature enable signal OTP_ENB, the too low enable signal BNO_ENB of output line voltage and the line brownout signal BOK of 701 outputs of OTP enable circuits.
Receive excess temperature signal OTP and line brownout signal BOK with door 703, generate and output error signal Fault.
Preferably, as shown in Figure 8, OTP enable circuits 701 comprises:
The first not gate 801 that input is connected with described the first comparator output terminal;
The first NOR gate 802 that input is connected with the first not gate 801 outputs and BNO enable circuits 702 respectively;
The first d type flip flop 803 that CLK pin is connected with the first NOR gate 802 outputs; The D pin of the first d type flip flop 803 is connected with described power supply; The QB pin of the first d type flip flop 803 is connected with BNO enable circuits 702;
The second not gate 804 that input is connected with the output of described the second comparator;
The NAND gate 805 that input is connected with current reference module output with output and the described voltage of the second not gate 804 respectively; The output of NAND gate 805 is connected with the R pin of the first d type flip flop 803;
That input is connected with the QB pin of the first d type flip flop 803 and described the first comparator output terminal respectively or door 806; Or the output of door 806 is the output of OTP enable circuits 701;
BNO enable circuits 702 comprises:
The second d type flip flop 807 that CLK pin is connected with described the first comparator output terminal; The D pin of the second d type flip flop 807 is connected with described power supply; The SB pin of the second d type flip flop 807 is connected with current reference module output with described voltage; The RB pin of the second d type flip flop 807 is connected with the QB pin of the first d type flip flop 803; The QB pin of the second d type flip flop 807 is connected with the first NOR gate 802 inputs;
The second NOR gate 808 that input is connected with QB pin and second comparator output terminal of the second d type flip flop 807 respectively; The output of the second NOR gate 808 is the output of BNO enable circuits 702.
Concrete operation principle is:
As shown in Figure 9:
At initial state T0 constantly, the comparative level of the first comparator A1 shown in Fig. 4 is 0.1V, the 3rd switch S 3 conductings, and second switch S2 disconnects; When the first comparator A1 detects voltage Vline between filter unit 201 and rectification unit 202 in positive half cycle, be that input voltage VAC is when positive half cycle, the zero cross signal Z0 upset of the first comparator A1 output is high level, the second d type flip flop 807 in zero cross signal Z0 control chart 8, the line brownout enable signal BNO_ENB of its BQ pin output is enabled, initial voltage sample, wherein the first switch S 1 disconnects, and the first current source 401 does not provide current to the BNO/OTP pin as multiplexing end.The 6th switch S 6 conductings; minion is closed S7 and is disconnected; the input comparative level of the second comparator A2 is 0.3V; when the voltage on the BNO/OTP pin as multiplexing end is less than threshold voltage 0.3V; the line brownout signal BOK of BNO enable circuits 702 outputs closes power switch pipe Q, realizes the too low protection of input voltage.
T1 constantly, the comparative level of the first comparator A1 shown in Fig. 4 is 0.1V, the 3rd switch S 3 conductings, second switch S2 disconnects, when the first comparator A1 detects voltage Vline between filter unit 201 and rectification unit 202 in positive half cycle, be that input voltage VAC is when negative half period, the zero cross signal Z0 of the first comparator A1 output is low level by high level upset, zero cross signal Z0 controls the first d type flip flop 803, the excess temperature enable signal OTP_ENB of its QB pin output is enabled, start testing environment temperature information, excess temperature enable signal OTP_ENB resets the second d type flip flop 807 simultaneously, BNO_ENB is invalid for line brownout enable signal, finishing input voltage detects.Excess temperature enable signal OTP_ENB enables to make the first switch S 1 and second switch S2 conducting, and the 3rd switch S 3 disconnects, and the first current source 401 provides current to the BNO/OTP pin as multiplexing end, at negative tempperature coefficient thermistor R
nupper generation pressure drop, when the voltage on the BNO/OTP pin as multiplexing end is less than threshold voltage 1V, the excess temperature signal OTP of OTP enable circuits 701 outputs closes power switch pipe Q, realizes the too low protection of ambient temperature.
Constantly, because the first current source 401 provides current to the first capacitor C 1 being connected with BNO/OTP pin in Acquisition Circuit 206, and the first capacitor C 1 charging needs the regular hour to T2, and control circuit 207 inside arrange OTP detection time.Excess temperature signal OTP sampling enables to start, the 8th switch S8, the 4th switch S 4, and the 6th switch S 6 disconnections, and the 5th switch S 5 and minion are closed S7 conducting.The second current source 402 starts to the first capacitor C 1 charging in control circuit 207, with voltage 1V comparison, when the first capacitor C 1 terminal voltage in control circuit 207 is greater than threshold voltage 1V, the timing signal BT upset of the second comparator A2 output is high level, timing signal BT is that high level resets the first d type flip flop 803, OTP_ENB is invalid for excess temperature enable signal, and ambient temperature detects and finishes.
The utility model another embodiment also provide a kind of switch power controller, be applied to flyback converter, described flyback converter as shown in figure 10, comprising: the power switch pipe Q that filter unit 201, the rectification unit 202 being connected with filter unit 201, first side winding 203, secondary side winding 204, auxiliary winding 205 and input are connected with first side winding 203 Same Name of Ends; Wherein, switch power controller 200 comprises:
Grounding pin;
VCC power pins;
First side winding current detecting pin CS;
Feedback signal detects pin COMP;
Output pin OUT;
BON/OTP multiplexing pins;
And the control circuit 207 as described in as arbitrary in Fig. 2 to Fig. 6.
Concrete operation principle is:
VCC power pins and auxiliary winding 205 couplings are merged into switch power controller 200 provides power supply; First side winding current detecting pin CS, by power switch pipe Q and first side winding 203 couplings, detects the electric current flowing through in first side winding 203; Feedback signal detects the situation that pin COMP detects the output being coupled with secondary side winding 204; The control end coupling of output pin OUT and power switch pipe Q conducting and the cut-off of power ratio control switching tube Q; The timesharing of BON/OTP multiplexing pins detects input voltage and ambient temperature; Control circuit 207 coordinates the operation principle of Acquisition Circuit 206 identical with above-mentioned arbitrary embodiment, repeats no more herein.
The utility model another embodiment also provide a kind of flyback converter, as shown in figure 11, comprising:
Receive the filter unit 101 of AC supply voltage signal VAC;
The rectification unit 102 being connected with filter unit 101;
The first capacitor C 1 that one end is connected with rectification unit 102 outputs respectively and the first resistance R 1; The other end ground connection of the first capacitor C 1;
The first side winding 103 that different name end is connected with rectification unit 102 outputs;
The power switch pipe Q that input is connected with the Same Name of Ends of first side winding 103;
The second capacitor C 2 being connected with first resistance R 1 other end; The other end ground connection of the second capacitor C 2;
The first diode D1 that negative pole is connected with the first resistance R 1 and the second capacitor C 2 tie points;
Same Name of Ends and the anodal auxiliary winding 104 being connected of the first diode D1; The different name end ground connection of auxiliary winding 104;
The arbitrary described multiplexing testing circuit 105 of above-described embodiment; In multiplexing testing circuit 105, the VCC pin of control circuit 111 is connected with the negative pole of the first diode D1;
The second resistance R 2 being connected with the CS pin of control circuit 111 in multiplexing testing circuit 105; The second resistance R 2 is connected with the output of power switch pipe Q with the tie point of control circuit 111CS pin, the other end ground connection of the second resistance R 2;
The optocoupler unit 106 that the first output is connected with the COMP pin of control circuit 111 in multiplexing testing circuit 105;
The second diode D2 that negative pole is connected with optocoupler unit 106 second outputs; The plus earth of the second diode D2;
The 3rd resistance R 3 that one end is connected with optocoupler unit 106 inputs;
The 3rd diode D3 that negative pole is connected with the 3rd resistance R 3 other ends;
Same Name of Ends and the anodal secondary side winding 107 being connected of the 3rd diode D3; The different name end ground connection of secondary side winding 107;
The 4th resistance R 4 and the 3rd capacitor C 3 that one end is connected with the 3rd diode D3 negative pole; The equal ground connection of the other end of the 4th resistance R 4 and the 3rd capacitor C 3.
Concrete operation principle is:
The AC supply voltage signal VAC of the alternating-current voltage source output after filtering voltage after unit 101 and rectification unit 102 is input voltage vin, input voltage vin is coupled to first side winding 103, power switch pipe Q is controlled by the pulse width modulation control signal that the OUT pin of control circuit 111 is exported, the second resistance R 2 is in order to detect the primary side current of the power switch pipe Q that flows through, the primary side current that the feedback signal that control circuit 111 receives according to COMP pin and CS pin receive decides the duty ratio of described pulse width modulation control signal, thereby regulated output voltage Vo.
In control circuit 111 start-up courses, when the voltage that VCC pin receives is less than internal reservoir threshold value, the OUT pin of control circuit 111 is not exported described pulse width modulation control signal, therefore input voltage vin is by the first resistance R 1, give the second capacitor C 2 chargings, when the voltage of VCC pin reception is greater than described internal reservoir threshold value, the described pulse width modulation control signal of control circuit 111 output, auxiliary winding 104 gives control circuit 111 power supplies after the first diode D1 rectification, the second capacitor C 2 filtering.
The control circuit 111 of multiplexing testing circuit 105 inside and the operation principle of Acquisition Circuit 112 are same as the previously described embodiments, repeat no more herein.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and each embodiment stresses is the difference with other embodiment, between each embodiment identical similar part mutually referring to.
Above-mentioned explanation to the disclosed embodiments, makes professional and technical personnel in the field can realize or use the utility model.To the multiple modification of these embodiment, will be apparent for those skilled in the art, General Principle as defined herein can, in the situation that not departing from spirit or scope of the present utility model, realize in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a multiplexing testing circuit, it is characterized in that, be applied to flyback converter, described flyback converter comprises: the power switch pipe that filter unit, the rectification unit being connected with described filter unit, first side winding, secondary side winding, auxiliary winding and input are connected with described first side winding Same Name of Ends; Described multiplexing testing circuit comprises:
The Acquisition Circuit that input is connected with the tie point of described filter unit and rectification unit; Described Acquisition Circuit comprises negative tempperature coefficient thermistor;
Timesharing detects the control circuit of input voltage and ambient temperature; The BNO/OTP pin of described control circuit is connected with described Acquisition Circuit output, and the OUT pin of described control circuit is connected with the control end of described power switch pipe.
2. multiplexing testing circuit according to claim 1, is characterized in that, described Acquisition Circuit comprises:
One end is as the first resistance of described Acquisition Circuit input;
The second resistance that one end is connected with the described first resistance other end; The other end ground connection of described the second resistance;
The first diode that the tie point of anodal and described the first resistance and the second resistance is connected;
The second diode that anodal and described the first diode cathode is connected;
The negative tempperature coefficient thermistor that one end is connected with described the second diode cathode; The other end ground connection of described negative tempperature coefficient thermistor;
The first electric capacity that one end is connected with the tie point of described the first resistance and the second resistance; The other end ground connection of described the first electric capacity; The tie point of described the first resistance, the second resistance and the first electric capacity is as the output of described Acquisition Circuit.
3. multiplexing testing circuit according to claim 1, is characterized in that, described control circuit comprises:
One end receives the first current source of biasing voltage signal;
The first switch that input is connected with the described first current source other end;
The first comparator that in-phase input end is connected with described the first output switching terminal;
The second switch that one end is connected with the first inverting input of described the first comparator; The other end of described second switch receives 1V voltage signal;
The 3rd switch that one end is connected with the second inverting input of described the first comparator; The other end of described the 3rd switch receives 0.1V voltage signal;
The 4th switch that one end is connected with described the first output switching terminal; The tie point of described the first comparator, the first switch and the 4th switch is as described control circuit BNO/OTP pin;
The 5th switch that one end is connected with described the 4th switch other end;
The second comparator that normal phase input end is connected with the tie point of described the 4th switch and the 5th switch;
The 6th switch that one end is connected with described the second comparator inverting input respectively and minion are closed; The other end of described the 6th switch receives 0.325V or 0.3V voltage signal; The other end that described minion is closed receives 1V voltage signal;
Power supply;
The second current source that one end is connected with described the 5th switch other end; The other end of described the second current source is connected with described power supply;
The 8th switch and the first electric capacity that one end is connected with the tie point of described the 5th switch and the second current source respectively; The other end ground connection of described the 8th switch and the first electric capacity;
Receive primary side current detection signal and feedback loading detection signal, and the equal sub-control circuit of sequential that is connected with described the first comparator output terminal and the second comparator output terminal respectively of input; The output of the equal sub-control circuit of described sequential is as the OUT pin of described control circuit.
4. multiplexing testing circuit according to claim 3, is characterized in that, the equal sub-control circuit of described sequential comprises:
Input is respectively as the first logic controller of the equal sub-control circuit input of described sequential;
Receive primary side current detection signal and feedback loading detection signal, and the second logic controller being connected with the output of described the first logic controller;
The voltage and current reference module, oscillator and the driver that are connected with described the second logic controller respectively; The output of described driver is as the output of the equal sub-control circuit of described sequential.
5. multiplexing testing circuit according to claim 3, is characterized in that, in described control circuit, the equal sub-control circuit of sequential also comprises:
Generate and export the 3rd comparator of described primary side current detection signal; The normal phase input end of described the 3rd comparator receives reference voltage signal; The CS pin that the inverting input of described the 3rd comparator receives described control circuit receives signal and line voltage compensation signal;
Generate and export the 4th comparator of described feedback loading detection signal; The normal phase input end of described the 4th comparator is as the COMP pin of described control circuit; The CS pin that the inverting input of described the 4th comparator receives described control circuit receives signal and harmonic compensation signal.
6. multiplexing testing circuit according to claim 4, is characterized in that, described the first logic controller comprises:
The OTP enable circuits that input is connected with current reference module output with described the first comparator output terminal, the second comparator output terminal and voltage respectively;
The BNO enable circuits that input is connected with current reference module output with described the first comparator output terminal, the second comparator output terminal and voltage respectively; Described OTP enable circuits and described BNO enable circuits interconnect;
Input be connected with described OTP enable circuits output and BNO enable circuits output respectively with door, described with the output of door as the output of described the first logic controller.
7. multiplexing testing circuit according to claim 6, is characterized in that, described OTP enable circuits comprises:
The first not gate that input is connected with described the first comparator output terminal;
The first NOR gate that input is connected with described the first non-gate output terminal and described BNO enable circuits respectively;
The first d type flip flop that CLK pin is connected with described the first NOR gate output; The D pin of described the first d type flip flop is connected with described power supply; The QB pin of described the first d type flip flop is connected with described BNO enable circuits;
The second not gate that input is connected with the output of described the second comparator;
The NAND gate that input is connected with current reference module output with output and the described voltage of described the second not gate respectively; The output of described NAND gate is connected with the R pin of described the first d type flip flop;
That input is connected with the QB pin of described the first d type flip flop and described the first comparator output terminal respectively or door; Output described or door is the output of described OTP enable circuits.
8. multiplexing testing circuit according to claim 7, is characterized in that, described BNO enable circuits comprises:
The second d type flip flop that CLK pin is connected with described the first comparator output terminal; The D pin of described the second d type flip flop is connected with described power supply; The SB pin of described the second d type flip flop is connected with current reference module output with described voltage; The RB pin of described the second d type flip flop is connected with the QB pin of described the first d type flip flop; The QB pin of described the second d type flip flop is connected with described the first NOR gate input;
The second NOR gate that input is connected with QB pin and second comparator output terminal of described the second d type flip flop respectively; The output of described the second NOR gate is the output of described BNO enable circuits.
9. a switch power controller, be applied to flyback converter, described flyback converter comprises: the power switch pipe that filter unit, the rectification unit being connected with described filter unit, first side winding, secondary side winding, auxiliary winding and input are connected with described first side winding Same Name of Ends; It is characterized in that, described switch power controller comprises:
Grounding pin;
With auxiliary winding coupled and for described switch power controller, provide the VCC power pins of power supply;
By described power switch pipe and described first side winding, be coupled, detect the first side winding current detecting pin CS of the electric current flowing through in described first side winding;
The feedback signal that detects the output situation being coupled with described secondary side winding detects pin COMP;
Be coupled with the control end of described power switch pipe and control the output pin OUT of conducting and the cut-off of described power switch pipe;
Timesharing detects the BON/OTP multiplexing pins of input voltage and ambient temperature;
And the control circuit as described in as arbitrary in claim 1 to 8.
10. a flyback converter, is characterized in that, comprising:
Receive the filter unit of AC supply voltage signal;
The rectification unit being connected with described filter unit;
The first electric capacity and the first resistance that one end is connected with described rectification unit output respectively; The other end ground connection of described the first electric capacity;
The first side winding that different name end is connected with described rectification unit output;
The power switch pipe that input is connected with the Same Name of Ends of described first side winding;
The second electric capacity being connected with the described first resistance other end; The other end ground connection of described the second electric capacity;
The first diode that negative pole is connected with described the first resistance and the second electric capacity tie point;
The auxiliary winding that Same Name of Ends is connected with described the first diode cathode; The different name end ground connection of described auxiliary winding;
The arbitrary described multiplexing testing circuit of claim 1 to 8; Described in described multiplexing testing circuit, the VCC pin of control circuit is connected with the negative pole of described the first diode;
The second resistance being connected with the CS pin of control circuit described in described multiplexing testing circuit; Described the second resistance is connected with the output of described power switch pipe with the tie point of described control circuit CS pin, the other end ground connection of described the second resistance;
The optocoupler unit that the first output is connected with the COMP pin of control circuit described in described multiplexing testing circuit;
The second diode that negative pole is connected with described optocoupler unit the second output; The plus earth of described the second diode;
The 3rd resistance that one end is connected with described optocoupler unit input;
The 3rd diode that negative pole is connected with described the 3rd resistance other end;
The secondary side winding that Same Name of Ends is connected with described the 3rd diode cathode; The different name end ground connection of described secondary side winding;
The 4th resistance and the 3rd electric capacity that one end is connected with described the 3rd diode cathode; The equal ground connection of the other end of described the 4th resistance and the 3rd electric capacity.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420160972.2U CN203883456U (en) | 2014-04-03 | 2014-04-03 | Multiplexing detection circuit, switching power supply controller and fly-back converter |
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| CN201420160972.2U CN203883456U (en) | 2014-04-03 | 2014-04-03 | Multiplexing detection circuit, switching power supply controller and fly-back converter |
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| CN203883456U true CN203883456U (en) | 2014-10-15 |
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| CN107147294A (en) * | 2017-05-17 | 2017-09-08 | 成都启臣微电子股份有限公司 | A kind of flyback power supply control system |
| CN107171533A (en) * | 2016-03-07 | 2017-09-15 | 精工半导体有限公司 | Switching regulaor |
| CN107565823A (en) * | 2016-06-30 | 2018-01-09 | 意法半导体股份有限公司 | Quasi-resonance AC/DC flyback converter primary side adjustment control methods and equipment |
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| US10468991B2 (en) | 2014-12-16 | 2019-11-05 | Stmicroelectronics S.R.L. | Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter |
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| CN111490682A (en) * | 2016-04-08 | 2020-08-04 | 昂宝电子（上海）有限公司 | Flyback power supply system |
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| US10468991B2 (en) | 2014-12-16 | 2019-11-05 | Stmicroelectronics S.R.L. | Control method and device employing primary side regulation in a quasi-resonant AC/DC flyback converter |
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| CN107171533A (en) * | 2016-03-07 | 2017-09-15 | 精工半导体有限公司 | Switching regulaor |
| CN111490682A (en) * | 2016-04-08 | 2020-08-04 | 昂宝电子（上海）有限公司 | Flyback power supply system |
| CN107565823A (en) * | 2016-06-30 | 2018-01-09 | 意法半导体股份有限公司 | Quasi-resonance AC/DC flyback converter primary side adjustment control methods and equipment |
| CN107565823B (en) * | 2016-06-30 | 2020-04-24 | 意法半导体股份有限公司 | Method and device for regulating and controlling primary side of quasi-resonant AC/DC flyback converter |
| CN107147294A (en) * | 2017-05-17 | 2017-09-08 | 成都启臣微电子股份有限公司 | A kind of flyback power supply control system |
| CN109638772B (en) * | 2017-10-06 | 2020-07-03 | 新唐科技股份有限公司 | Temperature judging circuit and power supply management circuit |
| CN109638772A (en) * | 2017-10-06 | 2019-04-16 | 新唐科技股份有限公司 | Temperature decision circuitry and electric power management circuit |
| CN110690823A (en) * | 2018-07-04 | 2020-01-14 | 立锜科技股份有限公司 | Switching power supply and power switch control circuit thereof |
| CN110690823B (en) * | 2018-07-04 | 2021-03-23 | 立锜科技股份有限公司 | Switching power supply and power switch control circuit thereof |
| CN109799721A (en) * | 2019-01-31 | 2019-05-24 | 海信（山东）空调有限公司 | A kind of control circuit of household electrical appliance, control method and household electrical appliance |
| CN109799721B (en) * | 2019-01-31 | 2021-12-14 | 海信（山东）空调有限公司 | Control circuit and control method of household appliance and household appliance |
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Effective date of registration: 20210203 Address after: No. 1600, Zixing Road, Minhang District, Shanghai 200241 Patentee after: BCD (SHANGHAI) MICRO-ELECTRONICS Ltd. Address before: 200233 No. 800, Xuhui District, Shanghai, Yishan Road Patentee before: BCD Semiconductor Manufacturing Limited |
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