CN203883690U - Multiplexing detection circuit, switching power supply controller and fly-back converter - Google Patents
Multiplexing detection circuit, switching power supply controller and fly-back converter Download PDFInfo
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- CN203883690U CN203883690U CN201420160762.3U CN201420160762U CN203883690U CN 203883690 U CN203883690 U CN 203883690U CN 201420160762 U CN201420160762 U CN 201420160762U CN 203883690 U CN203883690 U CN 203883690U
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Abstract
The utility model relates to a multiplexing detection circuit, a voltage division circuit acquires the auxiliary winding voltage, a negative temperature coefficient thermistor in the voltage division circuit acquires environmental temperature information, a SOVP/OTP pin of a control circuit acquires the auxiliary winding voltage and the environmental temperature information in a time sharing manner, and detection of the auxiliary winding voltage and the environmental temperature information is achieved, the control of a power switch tube is achieved through the output signal of an OUT pin of the control circuit, and overvoltage protection and over-temperature protection are finally achieved; and the output voltage of a fly-back converter and the auxiliary winding voltage can maintain a stable multiple relation even under conditions of different line voltages and different loads. By employing the multiplexing detection circuit, the overvoltage protection effect can be effectively improved, pins or other components do not need to be added, and the cost is not increased.
Description
Technical field
The utility model relates to electric and electronic technical field, relates in particular to a kind of multiplexing testing circuit, switch power controller and flyback converter.
Background technology
Fig. 1 is a kind of typical flyback converter in electric pressure converter, comprise: alternating-current voltage source VAC, filter unit 101, rectification unit 102, the first capacitor C 1, the first resistance R 1, the second capacitor C 2, the first diode D1, voltage-stabiliser tube D2, the second resistance R 2, negative tempperature coefficient thermistor R3, control circuit 103, auxiliary winding 104, first side winding 105, power switch pipe Q1, sampling resistor Rs, secondary side winding 106, the 3rd diode D3, the 4th resistance R 4, the 3rd capacitor C 3, the 5th resistance R 5, optocoupler unit 107, and the 4th diode D4.
Wherein, the SOVP/OTP pin of control circuit 103 is multiplexing functional pin, can realize the too high protection of VCC overvoltage protection and ambient temperature.
The external negative tempperature coefficient thermistor R3 of SOVP/OTP pin, the electric current of control circuit 103 inside flow through negative tempperature coefficient thermistor R3 produce voltage, in the time that this voltage is less than a threshold voltage, control circuit 103 makes power switch pipe Q1 stop output, can avoid the too high abnormal conditions of working temperature of transducer.
The voltage receiving when VCC pin is wide enough so that voltage-stabiliser tube D2 punctures, the SOVP/OTP pin of control circuit 103 detects by voltage-stabiliser tube D2 and the second resistance R 2 voltage that now VCC pin receives, in the time detecting that the voltage of described VCC pin reception is greater than certain threshold voltage, control circuit 103 makes power switch pipe Q1 stop output.Control circuit 103 can reflect output voltage V o to a certain extent by the voltage that detects VCC reception, and VCC overvoltage protection can reflect output over-voltage protection to a certain extent.But due to the existence of the cross regulation rate of flyback converter; relation between the voltage that output voltage V o and VCC receive under different line voltage, different loading condition can not ensure to stablize constant, so the over-voltage protection point of scheme shown in Fig. 1 exists certain difference.
In prior art, for improving the effect of output over-voltage protection, Fig. 1 is revised, but corresponding modification brings the situation that increases control circuit pin or other circuit elements devices simultaneously, has caused the increase of circuit cost.
Utility model content
In view of this, the utility model provides a kind of multiplexing testing circuit, switch power controller and flyback converter, to solve in prior art to increase into the original problem of improving output over-voltage protection effect.
To achieve these goals, the existing scheme proposing is as follows:
A kind of multiplexing testing circuit, is applied to flyback converter, and described flyback converter comprises: the power switch pipe that first side winding, secondary side winding, auxiliary winding and input are connected with described first side winding Same Name of Ends; Described multiplexing testing circuit comprises:
The bleeder circuit that input is connected with described auxiliary Motor Winding Same Name of Ends; Described bleeder circuit comprises negative tempperature coefficient thermistor;
Timesharing detects the control circuit of auxiliary winding voltage and ambient temperature; The SOVP/OTP pin of described control circuit is connected with described bleeder circuit output, and the OUT pin of described control circuit is connected with the control end of described power switch pipe.
Preferably, described bleeder circuit comprises:
Anodal the first diode as described bleeder circuit input;
The first resistance that one end is connected with described the first diode cathode;
The second resistance that one end is connected with the described first resistance other end; The other end ground connection of described the second resistance;
The described negative tempperature coefficient thermistor that one end is connected with described the first resistance and the second resistance tie point; The other end of described negative tempperature coefficient thermistor is as the output of described bleeder circuit.
Preferably, described control circuit comprises:
One end receives the current source of biasing voltage signal;
The switch that input is connected with the described current source other end;
The first comparator that in-phase input end is connected with described output switching terminal respectively and the second comparator; The tie point of described the first comparator and the second comparator in-phase input end and described output switching terminal is as described control circuit SOVP/OTP pin; The inverting input of described the first comparator receives the first reference signal; The inverting input of described the second comparator receives the second reference signal;
Receive primary side current detection signal and feedback loading detection signal, and the equal sub-control circuit of sequential that is connected with described the first comparator output terminal and the second comparator output terminal respectively of input; The first output of the equal sub-control circuit of described sequential is connected with the control end of described switch; The second output of the equal sub-control circuit of described sequential is as the OUT pin of described control circuit.
Preferably, the equal sub-control circuit of described sequential comprises:
Input is respectively as the first logic controller of the equal sub-control circuit input of described sequential; The first output of described the first logic controller is as the first output of the equal sub-control circuit of described sequential;
Receive primary side current detection signal and feedback loading detection signal, and the second logic controller of being connected with the second output of described the first logic controller of input; The output of described the second logic controller is connected with described the first logic controller;
The voltage and current reference module, oscillator and the driver that are connected with described the second logic controller respectively; The output of described driver is as the second output of the equal sub-control circuit of described sequential.
Preferably, in described control circuit, the equal sub-control circuit of sequential also comprises:
Generate and export the 3rd comparator of described primary side current detection signal; The normal phase input end of described the 3rd comparator receives reference voltage signal; The CS pin that the inverting input of described the 3rd comparator receives described control circuit receives signal and line voltage compensation signal;
Generate and export the 4th comparator of described feedback loading detection signal; The normal phase input end of described the 4th comparator is as the COMP pin of described control circuit; The CS pin that the inverting input of described the 4th comparator receives described control circuit receives signal and harmonic compensation signal.
Preferably, described the first logic controller comprises:
The rest-set flip-flop of input difference received pulse trailing edge signal and sampled clock signal; The output of described rest-set flip-flop is as the first output of described the first logic controller;
Received pulse modulation signal, benchmark are set up the SOVP Logic control module that signal and described sampled clock signal, input are connected with described the first comparator output terminal;
Receive described pulse-modulated signal and benchmark and set up the OTP Logic control module that signal, input are connected with described the second comparator output terminal;
The first NAND gate that input is connected with the output of described SOVP Logic control module and OTP Logic control module respectively, the output of described the first NAND gate is the second output of described the first logic controller.
Preferably, described SOVP Logic control module comprises:
Input receives the not gate of described pulse-modulated signal;
Input receives the output signal of described not gate and the second NAND gate of described sampled clock signal;
The first d type flip flop that CLK pin is connected with described the second NAND gate output; The D pin of described the first d type flip flop is the input of described SOVP Logic control module; The R pin of described the first d type flip flop receives described benchmark and sets up signal;
The first delay circuit that input is connected with the Q pin of described the first d type flip flop.
Preferably, described OTP Logic control module comprises:
CLK pin receives the second d type flip flop of described pulse-modulated signal; The D pin of described the second d type flip flop is the input of described OTP Logic control module; The R pin of described the second d type flip flop receives described benchmark and sets up signal;
The second delay circuit that input is connected with the Q pin of described the second d type flip flop.
A kind of switch power controller, is applied to flyback converter, and described flyback converter comprises: the power switch pipe that first side winding, secondary side winding, auxiliary winding and input are connected with described first side winding Same Name of Ends; Described switch power controller comprises:
Grounding pin;
Provide the VCC power pins of power supply with auxiliary winding coupled and for described switch power controller;
Be coupled, detect the first side winding current detecting pin CS of the electric current flowing through in described first side winding by described power switch pipe and described first side winding;
The feedback signal that detects the output situation being coupled with described secondary side winding detects pin COMP;
Be coupled with the control end of described power switch pipe and control the output pin OUT of conducting and the cut-off of described power switch pipe;
Timesharing detects the SOVP/OTP multiplexing pins of auxiliary winding voltage and ambient temperature;
And as above-mentioned control circuit as described in arbitrary.
A kind of flyback converter, comprising:
Receive the filter unit of AC supply voltage signal;
The rectification unit being connected with described filter unit;
The first electric capacity and the first resistance that one end is connected with described rectification unit output respectively; The other end ground connection of described the first electric capacity;
The first side winding that different name end is connected with described rectification unit output;
The power switch pipe that input is connected with the Same Name of Ends of described first side winding;
The second electric capacity being connected with the described first resistance other end; The other end ground connection of described the second electric capacity;
The first diode that negative pole is connected with described the first resistance and the second electric capacity tie point;
The auxiliary winding that Same Name of Ends is connected with described the first diode cathode; The different name end ground connection of described auxiliary winding;
Above-mentioned arbitrary described multiplexing testing circuit; Described in described multiplexing testing circuit, the VCC pin of control circuit is connected with the negative pole of described the first diode;
The second resistance being connected with the CS pin of control circuit described in described multiplexing testing circuit; Described the second resistance is connected with the output of described power switch pipe with the tie point of described control circuit CS pin, the other end ground connection of described the second resistance;
The optocoupler unit that the first output is connected with the COMP pin of control circuit described in described multiplexing testing circuit;
The second diode that negative pole is connected with described optocoupler unit the second output; The plus earth of described the second diode;
The 3rd resistance that one end is connected with described optocoupler unit input;
The 3rd diode that negative pole is connected with described the 3rd resistance other end;
The secondary side winding that Same Name of Ends is connected with described the 3rd diode cathode; The different name end ground connection of described secondary side winding;
The 4th resistance and the 3rd electric capacity that one end is connected with described the 3rd diode cathode; The equal ground connection of the other end of described the 4th resistance and the 3rd electric capacity.
Can find out from above-mentioned technical scheme, the disclosed multiplexing testing circuit of the utility model, by the auxiliary winding voltage of bleeder circuit collection, and gather ambient temperature information by the negative tempperature coefficient thermistor in described bleeder circuit, again by auxiliary winding voltage and ambient temperature information described in the SOVP/OTP pin acquisition time of control circuit, to realize respectively the detection to both, and the output signal of OUT pin by described control circuit realizes the control for power switch pipe, finally realize respectively overvoltage protection and overheat protector; Due to output voltage and the described auxiliary winding voltage of flyback converter; even if under different line voltage, different loading condition; also can keep stable multiple relation; so the disclosed multiplexing testing circuit of the utility model can effectively improve overvoltage protection effect; and without increasing pin or other components and parts, can not cause the increase of cost.
Brief description of the drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the flyback converter circuit diagram of this prior art;
Fig. 2 is the disclosed flyback converter circuit diagram of the utility model embodiment;
Fig. 3 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Fig. 4 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Fig. 5 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Fig. 6 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Fig. 7 is disclosed the first logic controller circuit diagram of another embodiment of the utility model;
Fig. 8 is the disclosed signal timing diagram of another embodiment of the utility model;
Fig. 9 is disclosed the first logic controller circuit diagram of another embodiment of the utility model;
Figure 10 is the disclosed signal timing diagram of another embodiment of the utility model;
Figure 11 is the disclosed flyback converter circuit diagram of another embodiment of the utility model;
Figure 12 is the disclosed flyback converter circuit diagram of another embodiment of the utility model.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The utility model provides a kind of multiplexing testing circuit, to solve in prior art to increase into the original problem of improving output over-voltage protection effect.
Concrete, as shown in Figure 2, described multiplexing testing circuit, is applied to flyback converter, and described flyback converter comprises: the power switch pipe Q that first side winding 201, secondary side winding 202, auxiliary winding 203 and input are connected with first side winding 201 Same Name of Ends; Described multiplexing testing circuit comprises:
The bleeder circuit 204 that input is connected with auxiliary winding 203 Same Name of Ends; Bleeder circuit 204 comprises negative tempperature coefficient thermistor;
The control circuit 205 that SOVP/OTP pin is connected with bleeder circuit 204 outputs; The OUT pin of control circuit 205 is connected with the control end of power switch pipe Q.
Concrete operation principle is:
Bleeder circuit 204 gathers auxiliary winding voltage, and gather ambient temperature information by the described negative tempperature coefficient thermistor in bleeder circuit 204, again by auxiliary winding voltage and ambient temperature information described in the SOVP/OTP pin acquisition time of control circuit 205, to realize respectively the detection to both, and the output signal of OUT pin by control circuit 205 realizes the control for power switch pipe Q, finally realize respectively overvoltage protection and overheat protector; Due to output voltage and the described auxiliary winding voltage of flyback converter; even if under different line voltage, different loading condition; also can keep stable multiple relation; so the disclosed multiplexing testing circuit of the present embodiment can effectively improve overvoltage protection effect; and without increasing pin or other components and parts, can not cause the increase of cost.
Preferably, as shown in Figure 3, bleeder circuit 204 comprises:
Anodal the first diode D1 as bleeder circuit 204 inputs;
The first resistance R 1 that one end is connected with the first diode D1 negative pole;
The second resistance R 2 that one end is connected with first resistance R 1 other end; The other end ground connection of the second resistance R 2;
The negative tempperature coefficient thermistor RN that one end is connected with the first resistance R 1 and the second resistance R 2 tie points; The other end of negative tempperature coefficient thermistor RN is as the output of bleeder circuit 204.
Preferably, as shown in Figure 4, control circuit 205 comprises:
One end receives the current source 251 of biasing voltage signal Vbias;
The switch S that input is connected with current source 251 other ends;
The first comparator A1 that in-phase input end is connected with switch S output respectively and the second comparator A2; The tie point of the first comparator A1 and the second comparator A2 in-phase input end and switch S output is as the SOVP/OTP pin of control circuit 205; The inverting input of the first comparator A1 receives the first reference signal REF1; The inverting input of the second comparator A2 receives the second reference signal REF2;
Receive primary side current detection signal VCS and feedback loading detection signal FB, and the equal sub-control circuit 252 of sequential that is connected with the first comparator A1 output and the second comparator A2 output respectively of input; The first output of the equal sub-control circuit 252 of sequential is connected with the control end of switch S; The second output of the equal sub-control circuit 252 of sequential is as the OUT pin of control circuit 205.
Concrete operation principle is:
In the time of power switch pipe Q conducting, the equal sub-control circuit 252 control switch S closures of sequential, make current source 251 flow out electric current I OTP, in the negative tempperature coefficient thermistor RN outside control circuit 205 and the second resistance R 2, produce pressure drop.Now auxiliary winding voltage Vaux=0, the voltage on the SOVP/OTP pin of control circuit 205 is:
V
SOVP/OTP=IOTP*(R
N+R2) (1)
In the time that the voltage on the SOVP/OTP of control circuit 205 pin is less than the first reference signal REF1 of the first comparator A1 inverting input reception; the first comparator A1 output protection signal OTP; by the equal sub-control circuit 252 of sequential; the OUT pin output signal power ratio control switching tube Q of control circuit 205 is closed, to realize overheat protector.
In the time that power switch pipe Q closes, the equal sub-control circuit 252 control switch S of sequential disconnect, and make current source 251 not flow out electric current I OTP, in the negative tempperature coefficient thermistor RN outside control circuit 205 and the second resistance R 2, do not produce pressure drop.Now the voltage on the SOVP/OTP pin of control circuit 205 is that auxiliary winding voltage Vaux deducts the pressure drop V on the first diode D1
d1after, the pressure drop of getting in the second resistance R 2:
V
SOVP/OTP=(Vaxu-V
D1)*R2/(R1+R2) (2)
. work as V
sOVP/OTPwhen voltage is greater than the second reference signal REF2 of the second comparator A2 inverting input reception; the second comparator A2 output protection signal SOVP; by the equal sub-control circuit 252 of sequential, the OUT pin output signal power ratio control switching tube Q of control circuit 205 is closed, to realize overvoltage protection.
Preferably, as shown in Figure 5, the equal sub-control circuit 252 of sequential comprises:
Input is respectively as the first logic controller 521 of the equal sub-control circuit input of sequential; The first output of the first logic controller 521 is as the first output of the equal sub-control circuit 252 of sequential;
Receive primary side current detection signal VCS and feedback loading detection signal FB, and the second logic controller 522 of being connected with the second output of the first logic controller 521 of input; The output of the second logic controller 522 is connected with the first logic controller 521;
The voltage being connected with the second logic controller 522 respectively and current reference module 523, oscillator 524 and driver 525; The output of driver 525 is as the second output of the equal sub-control circuit 252 of sequential.
The first output output enable signal Bias_EN of the first logic controller 521 is to the control end of switch S, the second output output Fault signal to the second logic controller 522 of the first logic controller 521, voltage and current reference module 523 output references are set up signal BG to the second logic controller 522, oscillator 524 clock signal CLK to the second logic controllers 522, the second logic controller 522 is exported pulse-modulated signal PWM to driver 525, and driver 525 outputs signal to OUT pin.
Figure 5 shows that a kind of specific implementation form of the equal sub-control circuit 252 of sequential, by the first logic controller 521, the second logic controller 522, voltage and current reference module 523, oscillator 524 and driver 525, realize the time-sharing facility of control circuit 205; In concrete practical application, can also adopt other components and parts or connected mode to realize described time-sharing facility according to its concrete applied environment, and be not specifically limited herein.
Preferably, as shown in Figure 6, control circuit 205 also comprises:
Generate and export the 3rd comparator A3 of primary side current detection signal VCS; The normal phase input end of the 3rd comparator A3 receives reference voltage signal Vref; The CS pin of the inverting input reception control circuit 205 of the 3rd comparator A3 receives signal and line voltage compensation signal Saw Comp;
Generate also the 4th comparator A4 of output load feedback detection signal FB; The normal phase input end of the 4th comparator A4 is as the COMP pin of control circuit 205; The CS pin of the inverting input reception control circuit 205 of the 4th comparator A4 receives signal and harmonic compensation signal Slop Comp.
The signal that the signal that control circuit 205 receives according to COMP pin and CS pin receive decides the duty ratio of OUT pin output signal, so that the output voltage that whole flyback converter can be stable.
Preferably, as shown in Figure 7, the first logic controller 521 comprises:
The rest-set flip-flop 701 of input difference received pulse trailing edge signal Pulse_FE and sampled clock signal Tsample; The output of rest-set flip-flop 701 is as the first output of the first logic controller 521, output enable signal Bias_EN;
Received pulse modulation signal PWM, benchmark are set up the SOVP Logic control module 702 that signal BG and sampled clock signal Tsample, input and described the first comparator output terminal are connected, receive described SOVP signal;
Received pulse modulation signal PWM and benchmark are set up the OTP Logic control module 703 that signal BG, input and described the second comparator output terminal are connected, receive described OTP signal;
The output of the first NAND gate 704, the first NAND gate 704 that input is connected with the output of SOVP Logic control module 702 and OTP Logic control module 703 is respectively the second output of the first logic controller 521, exports described Fault signal.
Concrete operation principle is:
As shown in Figure 8:
In the T0 moment, pulse-modulated signal PWM exports high level, and it is effective that rest-set flip-flop 701 exports the enable signal Bias_EN of control end of switch S to.
In the T1 moment, pulse-modulated signal PWM transfers low level to by high level, and now described enable signal Bias_EN is invalid, and a high flag bit, the appearance of indicating impulse modulation signal PWM trailing edge appear in the trailing edge of pulse simultaneously signal Pulse_FE.
In the T2 moment, pulse-modulated signal PWM continues low level a period of time, starts timing from t1, and during to t2, a high flag bit appears in sampled clock signal Tsample, and now described enable signal Bias_EN transfers high level to by low level, and electric current enables to start.
In the T3 moment, be the circulation in T0 moment, and pulse-modulated signal PWM exports high level, and described enable signal Bias_EN enables effectively.
Described enable signal Bias_EN appeared between T2 moment and T4 moment.
Preferably, as shown in Figure 9, SOVP Logic control module 702 comprises:
The not gate 801 of input received pulse modulation signal PWM;
Input receives the output signal of not gate 801 and the second NAND gate 802 of sampled clock signal Tsample;
The first d type flip flop 803 that CLK pin is connected with described the second NAND gate output; The D pin of the first d type flip flop 803 is the input of SOVP Logic control module 702; The R pin of the first d type flip flop 803 receives benchmark and sets up signal BG;
The first delay circuit 804 that input is connected with the Q pin of the first d type flip flop 803;
OTP Logic control module 703 comprises:
The second d type flip flop 805 of CLK pin received pulse modulation signal PWM; The D pin of the second d type flip flop 805 is the input of OTP Logic control module 703; The R pin of the second d type flip flop 805 receives benchmark and sets up signal BG;
The second delay circuit 806 that input is connected with the Q pin of the second d type flip flop 805.
Concrete operation principle is:
As shown in figure 10:
In the T0 moment, pulse-modulated signal PWM is high level, Vaxu=0, and sampled clock signal Tsample is invalid, SOVP_EN invalidating signal.
In the T1 moment, pulse-modulated signal PWM is that high level transfers low level to, and described Vaxu is high level, and sampled clock signal Tsample is invalid, described SOVP_EN invalidating signal.
In the T2 moment, pulse-modulated signal PWM is low level, and described Vaxu is high level, through stabilization time, there is the flag bit enabling in sampled clock signal Tsample, and described SOVP_EN signal enables effectively, now, by the output signal SOVP of the second comparator A2, control the second logic controller 522.
In the T4 moment, be the circulation in T0 moment, and pulse-modulated signal PWM is high level, Vaxu=0, and sampled clock signal Tsample is invalid, described SOVP_EN invalidating signal.
The utility model another embodiment also provide a kind of switch power controller, be applied to flyback converter, described flyback converter as shown in figure 11, comprising: the power switch pipe Q that first side winding 201, secondary side winding 202, auxiliary winding 203 and input are connected with first side winding 201 Same Name of Ends; Wherein, switch power controller 200 comprises:
Grounding pin;
VCC power pins;
First side winding current detecting pin CS;
Feedback signal detects pin COMP;
Output pin OUT;
SOVP/OTP multiplexing pins;
And control circuit 205 as described in as arbitrary in Fig. 2 to Fig. 6.
Concrete operation principle is:
VCC power pins and auxiliary winding 203 couplings are merged into switch power controller 200 provides power supply; First side winding current detecting pin CS is coupled by power switch pipe Q and first side winding 201, detects the electric current flowing through in first side winding 201; Feedback signal detection pin COMP detects the situation of the output being coupled with secondary side winding 202; The control end coupling of output pin OUT and power switch pipe Q conducting and the cut-off of power ratio control switching tube Q; The timesharing of SOVP/OTP multiplexing pins detects auxiliary winding voltage and ambient temperature; Control circuit 205 coordinates the operation principle of bleeder circuit 204 identical with above-mentioned arbitrary embodiment, repeats no more herein.
The utility model another embodiment also provide a kind of flyback converter, as shown in figure 12, comprising:
Receive the filter unit 111 of AC supply voltage signal;
The rectification unit 112 being connected with filter unit 111;
The first capacitor C 1 that one end is connected with rectification unit 112 outputs respectively and the first resistance R 1; The other end ground connection of the first capacitor C 1;
The first side winding 113 that different name end is connected with rectification unit 112 outputs;
The power switch pipe Q that input is connected with the Same Name of Ends of first side winding 113;
The second capacitor C 2 being connected with first resistance R 1 other end; The other end ground connection of the second capacitor C 2;
The first diode D1 that negative pole is connected with the first resistance R 1 and the second capacitor C 2 tie points;
Same Name of Ends and the anodal auxiliary winding 114 being connected of the first diode D1; The different name end ground connection of auxiliary winding 114;
The arbitrary described multiplexing testing circuit 115 of above-described embodiment; In multiplexing testing circuit 115, the VCC pin of control circuit 150 is connected with the negative pole of the first diode D1;
The second resistance R 2 being connected with the CS pin of control circuit 150 in multiplexing testing circuit 115; The second resistance R 2 is connected with the output of power switch pipe Q with the tie point of control circuit 150CS pin, the other end ground connection of the second resistance R 2;
The optocoupler unit 116 that the first output is connected with the COMP pin of control circuit 150 in multiplexing testing circuit 115;
The second diode D2 that negative pole is connected with optocoupler unit 116 second outputs; The plus earth of the second diode D2;
The 3rd resistance R 3 that one end is connected with optocoupler unit 116 inputs;
The 3rd diode D3 that negative pole is connected with the 3rd resistance R 3 other ends;
Same Name of Ends and the anodal secondary side winding 117 being connected of the 3rd diode D3; The different name end ground connection of secondary side winding 117;
The 4th resistance R 4 and the 3rd capacitor C 3 that one end is connected with the 3rd diode D3 negative pole; The equal ground connection of the other end of the 4th resistance R 4 and the 3rd capacitor C 3.
Concrete operation principle is:
The AC supply voltage signal VAC of the alternating-current voltage source output after filtering voltage after unit 111 and rectification unit 112 is input voltage vin, input voltage vin is coupled to first side winding 113, power switch pipe Q is controlled by the pulse width modulation control signal that the OUT pin of control circuit 150 is exported, the second resistance R 2 is in order to detect the primary side current of the power switch pipe Q that flows through, the primary side current that the feedback signal that control circuit 150 receives according to COMP pin and CS pin receive decides the duty ratio of described pulse width modulation control signal, thereby regulated output voltage Vo.
In control circuit 150 start-up courses, when the voltage that VCC pin receives is less than internal reservoir threshold value, the OUT pin of control circuit 150 is not exported described pulse width modulation control signal, therefore input voltage vin is by the first resistance R 1, charge to the second capacitor C 2, in the time that the voltage of VCC pin reception is greater than described internal reservoir threshold value, control circuit 150 is exported described pulse width modulation control signal, and auxiliary winding 114 powers to after the first diode D1 rectification, the second capacitor C 2 filtering control circuit 150.
The control circuit 150 of multiplexing testing circuit 115 inside and the operation principle of bleeder circuit 151 are same as the previously described embodiments, repeat no more herein.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment, between each embodiment identical similar part mutually referring to.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the utility model.To be apparent for those skilled in the art to the multiple amendment of these embodiment, General Principle as defined herein can, in the situation that not departing from spirit or scope of the present utility model, realize in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a multiplexing testing circuit, is characterized in that, is applied to flyback converter, and described flyback converter comprises: the power switch pipe that first side winding, secondary side winding, auxiliary winding and input are connected with described first side winding Same Name of Ends; Described multiplexing testing circuit comprises:
The bleeder circuit that input is connected with described auxiliary Motor Winding Same Name of Ends; Described bleeder circuit comprises negative tempperature coefficient thermistor;
Timesharing detects the control circuit of auxiliary winding voltage and ambient temperature; The SOVP/OTP pin of described control circuit is connected with described bleeder circuit output, and the OUT pin of described control circuit is connected with the control end of described power switch pipe.
2. multiplexing testing circuit according to claim 1, is characterized in that, described bleeder circuit comprises:
Anodal the first diode as described bleeder circuit input;
The first resistance that one end is connected with described the first diode cathode;
The second resistance that one end is connected with the described first resistance other end; The other end ground connection of described the second resistance;
The described negative tempperature coefficient thermistor that one end is connected with described the first resistance and the second resistance tie point; The other end of described negative tempperature coefficient thermistor is as the output of described bleeder circuit.
3. multiplexing testing circuit according to claim 1, is characterized in that, described control circuit comprises:
One end receives the current source of biasing voltage signal;
The switch that input is connected with the described current source other end;
The first comparator that in-phase input end is connected with described output switching terminal respectively and the second comparator; The tie point of described the first comparator and the second comparator in-phase input end and described output switching terminal is as described control circuit SOVP/OTP pin; The inverting input of described the first comparator receives the first reference signal; The inverting input of described the second comparator receives the second reference signal;
Receive primary side current detection signal and feedback loading detection signal, and the equal sub-control circuit of sequential that is connected with described the first comparator output terminal and the second comparator output terminal respectively of input; The first output of the equal sub-control circuit of described sequential is connected with the control end of described switch; The second output of the equal sub-control circuit of described sequential is as the OUT pin of described control circuit.
4. multiplexing testing circuit according to claim 3, is characterized in that, the equal sub-control circuit of described sequential comprises:
Input is respectively as the first logic controller of the equal sub-control circuit input of described sequential; The first output of described the first logic controller is as the first output of the equal sub-control circuit of described sequential;
Receive primary side current detection signal and feedback loading detection signal, and the second logic controller of being connected with the second output of described the first logic controller of input; The output of described the second logic controller is connected with described the first logic controller;
The voltage and current reference module, oscillator and the driver that are connected with described the second logic controller respectively; The output of described driver is as the second output of the equal sub-control circuit of described sequential.
5. multiplexing testing circuit according to claim 3, is characterized in that, in described control circuit, the equal sub-control circuit of sequential also comprises:
Generate and export the 3rd comparator of described primary side current detection signal; The normal phase input end of described the 3rd comparator receives reference voltage signal; The CS pin that the inverting input of described the 3rd comparator receives described control circuit receives signal and line voltage compensation signal;
Generate and export the 4th comparator of described feedback loading detection signal; The normal phase input end of described the 4th comparator is as the COMP pin of described control circuit; The CS pin that the inverting input of described the 4th comparator receives described control circuit receives signal and harmonic compensation signal.
6. multiplexing testing circuit according to claim 4, is characterized in that, described the first logic controller comprises:
The rest-set flip-flop of input difference received pulse trailing edge signal and sampled clock signal; The output of described rest-set flip-flop is as the first output of described the first logic controller;
Received pulse modulation signal, benchmark are set up the SOVP Logic control module that signal and described sampled clock signal, input are connected with described the first comparator output terminal;
Receive described pulse-modulated signal and benchmark and set up the OTP Logic control module that signal, input are connected with described the second comparator output terminal;
The first NAND gate that input is connected with the output of described SOVP Logic control module and OTP Logic control module respectively, the output of described the first NAND gate is the second output of described the first logic controller.
7. multiplexing testing circuit according to claim 6, is characterized in that, described SOVP Logic control module comprises:
Input receives the not gate of described pulse-modulated signal;
Input receives the output signal of described not gate and the second NAND gate of described sampled clock signal;
The first d type flip flop that CLK pin is connected with described the second NAND gate output; The D pin of described the first d type flip flop is the input of described SOVP Logic control module; The R pin of described the first d type flip flop receives described benchmark and sets up signal;
The first delay circuit that input is connected with the Q pin of described the first d type flip flop.
8. multiplexing testing circuit according to claim 7, is characterized in that, described OTP Logic control module comprises:
CLK pin receives the second d type flip flop of described pulse-modulated signal; The D pin of described the second d type flip flop is the input of described OTP Logic control module; The R pin of described the second d type flip flop receives described benchmark and sets up signal;
The second delay circuit that input is connected with the Q pin of described the second d type flip flop.
9. a switch power controller, is applied to flyback converter, and described flyback converter comprises: the power switch pipe that first side winding, secondary side winding, auxiliary winding and input are connected with described first side winding Same Name of Ends; It is characterized in that, described switch power controller comprises:
Grounding pin;
Provide the VCC power pins of power supply with auxiliary winding coupled and for described switch power controller;
Be coupled, detect the first side winding current detecting pin CS of the electric current flowing through in described first side winding by described power switch pipe and described first side winding;
The feedback signal that detects the output situation being coupled with described secondary side winding detects pin COMP;
Be coupled with the control end of described power switch pipe and control the output pin OUT of conducting and the cut-off of described power switch pipe;
Timesharing detects the SOVP/OTP multiplexing pins of auxiliary winding voltage and ambient temperature;
And control circuit as described in as arbitrary in claim 1 to 8.
10. a flyback converter, is characterized in that, comprising:
Receive the filter unit of AC supply voltage signal;
The rectification unit being connected with described filter unit;
The first electric capacity and the first resistance that one end is connected with described rectification unit output respectively; The other end ground connection of described the first electric capacity;
The first side winding that different name end is connected with described rectification unit output;
The power switch pipe that input is connected with the Same Name of Ends of described first side winding;
The second electric capacity being connected with the described first resistance other end; The other end ground connection of described the second electric capacity;
The first diode that negative pole is connected with described the first resistance and the second electric capacity tie point;
The auxiliary winding that Same Name of Ends is connected with described the first diode cathode; The different name end ground connection of described auxiliary winding;
The arbitrary described multiplexing testing circuit of claim 1 to 8; Described in described multiplexing testing circuit, the VCC pin of control circuit is connected with the negative pole of described the first diode;
The second resistance being connected with the CS pin of control circuit described in described multiplexing testing circuit; Described the second resistance is connected with the output of described power switch pipe with the tie point of described control circuit CS pin, the other end ground connection of described the second resistance;
The optocoupler unit that the first output is connected with the COMP pin of control circuit described in described multiplexing testing circuit;
The second diode that negative pole is connected with described optocoupler unit the second output; The plus earth of described the second diode;
The 3rd resistance that one end is connected with described optocoupler unit input;
The 3rd diode that negative pole is connected with described the 3rd resistance other end;
The secondary side winding that Same Name of Ends is connected with described the 3rd diode cathode; The different name end ground connection of described secondary side winding;
The 4th resistance and the 3rd electric capacity that one end is connected with described the 3rd diode cathode; The equal ground connection of the other end of described the 4th resistance and the 3rd electric capacity.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420160762.3U CN203883690U (en) | 2014-04-03 | 2014-04-03 | Multiplexing detection circuit, switching power supply controller and fly-back converter |
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| CN201420160762.3U CN203883690U (en) | 2014-04-03 | 2014-04-03 | Multiplexing detection circuit, switching power supply controller and fly-back converter |
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| CN107493007B (en) * | 2017-08-21 | 2023-09-08 | 矽力杰半导体技术(杭州)有限公司 | Signal multiplexing electronic circuit, signal multiplexing method and switching regulator using same |
| CN107592108A (en) * | 2017-09-29 | 2018-01-16 | 深圳南云微电子有限公司 | A kind of controller IC |
| CN107592108B (en) * | 2017-09-29 | 2024-05-14 | 深圳南云微电子有限公司 | Controller IC |
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