CN103825469B - For control circuit and the isolated converter of isolated converter - Google Patents
For control circuit and the isolated converter of isolated converter Download PDFInfo
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- CN103825469B CN103825469B CN201410079336.1A CN201410079336A CN103825469B CN 103825469 B CN103825469 B CN 103825469B CN 201410079336 A CN201410079336 A CN 201410079336A CN 103825469 B CN103825469 B CN 103825469B
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Abstract
The present invention relates to control circuit and isolated converter for isolated converter, described control circuit comprises for electrical input, grid link, source electrode link, source drive transistor, auxiliary switch, clamp diode and control signal generative circuit. Source drive transistor is connected between source electrode link and earth point; Auxiliary switch is connected to grid link and supplies between electrical input; Clamp diode is connected to between electrical input and source electrode link; Control signal generative circuit is used for generating the first control signal and the second control signal; The first control signal control source drive transistor is interval shutoff of the very first time, and the second control signal control auxiliary switch turn-offs at the second time interval, and very first time interval and the second time interval are positioned at the time interval of main power transistor conducting; It is interval or identical with very first time interval that the second time interval is greater than the very first time. The present invention can solve the problem of the isolated converter electricity shortage of source drive type.
Description
Technical field
The present invention relates to Power Electronic Technique, be specifically related to control circuit and isolated conversion for isolated converterDevice.
Background technology
Isolated converter is widely used in various off-line electric power systems. Isolated converter generally includes power stageCircuit and control circuit. In existing isolated converter, control circuit is conventionally by power supply capacitances to supply power, and power supply electric capacity needsAssist winding that energy is provided.
Thereby the isolated converter of source drive type is suggested to break away from the dependence for auxiliary winding. Fig. 1 is with inverse-excitation typeConverter is the circuit diagram that has exemplified existing isolated converter. As shown in Figure 1, the power of isolated converter 10Level circuit 11 comprises main power transistor QM, its control circuit 12 comprises control signal generative circuit Ctrl1 and source drive crystalline substanceBody pipe QS, by controlling source drive transistor QSON/OFF, can change main power transistor QMThe voltage of source electrode, entersAnd change main power transistor QMGate source voltage, thus make the power transistor Q of winnerMWith source drive transistor QSSynchronous conducting/Turn-off.
Isolated converter shown in Fig. 1 can be realized the power supply to control circuit without auxiliary winding, is control circuitThe supply voltage of 12 power supplies is at main power transistor QMConduction period, by main power transistor QMDrain-source electric capacity (be also crystalThe parasitic capacitance of pipe drain-source end) produce electric current to power supply capacitor CSCharging produces, and still, existing circuit structure is easyThe situation that occurs electricity shortage, affects control circuit and normally works.
Summary of the invention
In view of this, the present invention has overcome the defect for the control circuit electricity shortage of isolated converter.
In first aspect, a kind of control circuit is proposed, for isolated converter, described control circuit comprises power supply inputEnd, grid link, source electrode link, source drive transistor, auxiliary switch, clamp diode and control signal generate electricityRoad;
Described power supply electric capacity of powering for being connected to described control circuit for electrical input; Described grid link is used forBe connected with the grid of the main power transistor of described isolated converter; Described source electrode link is used for and described main power crystalThe source electrode of pipe connects;
Described source drive transistor is connected between described source electrode link and earth point;
Described auxiliary switch is connected to described grid link and described between electrical input;
Described clamp diode is connected to described between electrical input and described source electrode link;
Described control signal generative circuit is used for generating the first control signal and the second control signal; Described first controls letterNumber control described source drive transistor interval shutoff of the very first time, auxiliary switch exists described in described the second control signal controlThe second time interval turn-offs, and described very first time interval and described the second time interval are positioned at pulse-width signal and indicate main powerIn the time interval of transistor turns; Described the second time interval be greater than described very first time interval or with district of the described very first timeBetween identical.
In second aspect, provide a kind of isolated converter to comprise power stage circuit, the power supply with main power transistorElectric capacity and control circuit as above;
The grid of described main power transistor is connected with the grid link of described control circuit, described main power transistorSource electrode be connected with the source electrode link of described control circuit, described power supply electric capacity is connected to described for electrical input and earth pointBetween.
The present invention arranges auxiliary switch by the grid at main power transistor and control circuit between electrical input, andControl auxiliary switch and source drive transistor and turn-off between the winding current rising stage of former limit, make to flow through the electric current of former limit windingTo power supply capacitor charging, avoid the appearance of the too low situation of supply voltage by main power transistor, ensured control circuitNormal work.
Brief description of the drawings
By the description to the embodiment of the present invention referring to accompanying drawing, above-mentioned and other object of the present invention, feature andAdvantage will be more clear, in the accompanying drawings:
Fig. 1 is the circuit diagram of the isolated converter of source drive type in prior art;
Fig. 2 is the circuit diagram of the isolated converter of first embodiment of the invention;
Fig. 3 is the circuit diagram of the isolated converter of second embodiment of the invention;
Fig. 4 is a preferred circuit schematic diagram of delay pulse circuit in second embodiment of the invention;
Fig. 5 is the signal waveform schematic diagram of the isolated converter of second embodiment of the invention;
Fig. 6 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of third embodiment of the invention;
Fig. 7 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of fourth embodiment of the invention;
Fig. 8 is the signal waveform schematic diagram of the isolated converter of fourth embodiment of the invention;
Fig. 9 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of fifth embodiment of the invention;
Figure 10 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of sixth embodiment of the invention.
Detailed description of the invention
Based on preferred embodiment, present invention is described below, but the present invention is not restricted to these embodiment.In below details of the present invention being described, detailed some specific detail sections of having described. For a person skilled in the artDo not have the description of these detail sections can understand the present invention completely yet. For fear of obscuring essence of the present invention, known sideMethod, process, flow process, element and circuit do not describe in detail.
In addition, it should be understood by one skilled in the art that the accompanying drawing providing at this is all for illustrative purposes, andAccompanying drawing is not necessarily drawn in proportion.
, should be appreciated that in the following description, " circuit " refers to and passes through electric by least one element or electronic circuit meanwhileThe galvanic circle that connection or electromagnetism connect and compose. When claiming element or circuit " to be connected to " another element or claiming element/circuit " to connect" between two nodes time, it can be directly couple or be connected to another element or can have intermediary element, element itBetween connection can be physically, in logic or its combination. On the contrary, when claiming that element " is directly coupled to " or " directly connectsReceive " when another element, mean that both do not exist intermediary element.
Unless context explicitly calls for, otherwise " comprising ", " comprising " etc. in whole description and claims is similarThe implication that word should be interpreted as comprising instead of exclusive or exhaustive implication; That is to say, be containing of " including but not limited to "Justice.
In description of the invention, it will be appreciated that, term " first ", " second " etc. are only for describing object, and notCan be interpreted as instruction or hint relative importance. In addition, in description of the invention, except as otherwise noted, the implication of " multiple "Two or more.
In the present invention, be useful on and control the control signal of transistor or switch or for generating the letter of control signalNumber including two states, is also off state and conducting state, when control signal is during in off state, and the crystal of its controlPipe or switch are turned off, and when control signal is during in conducting state, transistor or the switch of its control are switched on.
The present invention can be applied to any isolated converter, in the following detailed description, only converts with inverse-excitation typeDevice (flybackconverter) is explained specific works principle of the present invention for example.
Fig. 2 is the circuit diagram of the isolated converter of first embodiment of the invention. As shown in Figure 2, isolated conversionDevice 20 comprises power stage circuit 21, the power supply capacitor C with main power transistorSWith control circuit 22.
Particularly, power stage circuit 21 comprises transformer T, main power transistor QMWith secondary current rectifying and wave filtering circuit. TransformationDevice T comprises the former limit winding L 1 and the secondary winding L 2 that intercouple. Secondary current rectifying and wave filtering circuit is connected with secondary winding L 2.
Control circuit 22 comprises for electrical input cc, grid link g, source electrode link s, source drive transistor QS、Auxiliary switch QC, clamp diode D2 and control signal generative circuit Ctrl2.
Main power transistor QMGrid be connected with the grid link g of control circuit 32, main power transistor QMSource electrodeBe connected power supply capacitor C with the source electrode link s of control circuit 32SBe connected to between electrical input cc and earth point gnd.
In control circuit 22, be used for being connected to for electrical input cc the power supply capacitor C that control circuit 22 is poweredS; GridLink g is used for the main power transistor Q with isolated converter 20MGrid connect; Source electrode link s is used for and main powerTransistor QMSource electrode connect.
Source drive transistor QSBe connected between source electrode link s and earth point gnd.
Auxiliary switch QCBe connected to grid link g and supply between electrical input cc.
Clamp diode D2 is connected to between electrical input cc and source electrode link s.
Control signal generative circuit Ctrl2 is used for generating the first control signal VQsWith the second control signal VQc, and defeated respectivelyGo out to source drive transistor QSWith auxiliary switch QCControl end. The first control signal VQsControl source drive transistor QS?The very first time, interval T1 turn-offed, the second control signal VQcControl auxiliary switch QCTurn-off the very first time at the second time interval T2Interval T1 and the second time interval T2 are positioned at pulse-width signal PWM and indicate main power transistor QMIn the time interval of conducting,And the second time interval T2 is greater than interval T1 of the very first time or identical with interval T1 of the very first time.
The circuit working principle of the present embodiment is as follows, and control signal generative circuit Ctrl2 can be according to feedback parameters (exampleAs, output voltage, primary current etc.) determine and indicate main power transistor QMThe pulse-width signal V of turn-on and turn-off statePWM(PWM, PulseWidthModulation), and generate the first control signal V based on this signalQsWith the second control signal VQc，At pulse-width signal VPWMWhile switching to conducting state by off state, the first control signal VQsControl source drive transistorQSSwitch to conducting by shutoff, meanwhile, the second control signal VQcControl auxiliary switch QCIn conducting state, now, main powerTransistor QMThe grid voltage input terminal voltage Vcc that equals to power, due to source drive transistor QSConducting, main power transistorQMSource voltage be 0. Therefore, main power transistor QMGate source voltage equal Vcc, thereby make the power transistor Q of winnerMQuiltDrive conducting, now electric current flows through former limit winding L 1, and rises gradually, and transformer T carries out energy storage.
At pulse-width signal VPWMIndicate main power transistor QMIn keeping during conducting, for the power supply of electrical inputVoltage vcc continuous decrease, if can not be compensated, supply voltage Vcc may be too low, and then cause control circuit 22 to be powered notFoot and cisco unity malfunction. Thus, control circuit 22 is at pulse-width signal VPWMIndicate main power transistor QMMaintenance conductingDuring this time, control source drive transistor QSWith auxiliary switch QCTurn-off a period of time simultaneously. During this period, because source electrode drivesMoving transistor QSTurn-off main power transistor QMSource voltage by lifting gradually until the input terminal voltage Vcc that equals to power makeObtain clamp diode D2 conducting, by main power transistor QMSource voltage be clamped at Vcc. Due to auxiliary switch Q nowCAlsoIn off state, main power transistor QMGrid source electric capacity there is no discharge channel, main power transistor QMGrid and source electrode itBetween voltage difference remain unchanged, make the power transistor Q of winnerMKeep conducting. The inductive current I of former limit windingpBy clamp two utmost pointsPipe D2 is to power supply capacitor CSCharging, compensation supply voltage Vcc.
Supply voltage Vcc is being compensated and met after predetermined condition, source drive transistor QSControlled and recovered conducting,Make the power transistor Q of winnerMSource voltage pulled down to 0, clamp diode D2 turn-off, the inductive current I of former limit windingpLogicalCross source drive transistor QSFlow to earth point, stop power supply capacitor CSCharging.
At pulse-width signal VPWMWhen instruction is turn-offed, source drive transistor QSTurn-off, and auxiliary switch Q nowCPlaceIn conducting state. The power transistor Q of Zhe Huishi winnerMGate source voltage become fast 0, and then cause main power transistor QMCloseDisconnected. Therefore, in order to keep main power transistor QMMaintain conducting state, auxiliary switch QCTurn-off time interval (also second o'clockBetween interval) need to be greater than source drive transistor QSTurn-off time interval (being also very first time interval) or at least with source electrodeDriving transistors QSTurn-off time interval (being also very first time interval) identical.
One of ordinary skill in the art will readily recognize that as long as the second time interval and very first time interval meet above-mentioned relation, nothingDiscuss the length in charging interval, all can to a certain degree alleviate the risk of control circuit electricity shortage.
Thus, the present embodiment is auxiliary for arranging between electrical input by the grid at main power transistor and control circuitSwitch, and control auxiliary switch and source drive transistor turn-offs between the winding current rising stage of former limit, make to flow through former limit aroundThe electric current of group to power supply capacitor charging, has been avoided the appearance of the too low situation of supply voltage by main power transistor, has ensured controlThe normal work of circuit processed.
Fig. 3 is the circuit diagram of the isolated converter of second embodiment of the invention. As shown in Figure 3, the present embodimentThe power stage circuit 31 of isolated converter 30 is identical with the first embodiment, does not repeat them here.
Control circuit 32 comprises for electrical input cc, grid link g, source electrode link s, source drive transistor QS、Auxiliary switch QC, clamp diode D2 and control signal generative circuit Ctrl3.
Main power transistor QMGrid be connected with the grid link g of control circuit 32, main power transistor QMSource electrodeBe connected power supply capacitor C with the source electrode link of control circuit 32SBe connected to between electrical input cc and earth point gnd.
In a preferred embodiment, isolated converter 30 can also comprise that being used to control circuit 32 to start powersStarting resistance RinAnd absorbing circuit.
In control circuit 32, be used for being connected to for electrical input cc the power supply capacitor C that control circuit 32 is poweredS; GridLink g is used for the main power transistor Q with isolated converterMGrid connect; Source electrode link s is used for and main power crystalline substanceBody pipe QMSource electrode connect.
Source drive transistor QSBe connected between source electrode link s and earth point gnd.
Auxiliary switch QCBe connected to grid link g and supply between electrical input cc.
Clamp diode D2 is connected to between electrical input cc and source electrode link s.
In the present embodiment, control signal generative circuit Ctrl3 comprises pulse-width signal generative circuit Ctrl31 and controlSignal acquisition circuit Ctrl32 processed.
Pulse-width signal generative circuit Ctrl31 is used for generating the main power transistor Q of instructionMThe time of turn-on and turn-offInterval pulse-width signal. It can be based on disclosing in well known to those skilled in the art and other prior art meansRealize, also, for example, determine the main power transistor Q of instruction according to feedback parameters (, output voltage, primary current etc.)MConducting andThe pulse-width signal V of the time interval turn-offingPWM。
Control signal acquisition cuicuit Ctrl32 is according to pulse-width signal VPWMDescribed in generating with power supply input terminal voltage VccThe first control signal VQsWith the second control signal VQc。
The first control signal VQsAfter conducting switching instant, postpone first time delay d1 switch to off state, supplyingElectrical input voltage switches to conducting state while being greater than first threshold voltage.
The second control signal VQcAfter conducting switching instant, postpone second time delay d2 switch to off state, supplyingElectrical input voltage switches to conducting state while being greater than first threshold voltage.
In the present embodiment, conducting switching instant is pulse-modulated signal VPWMSwitch to conducting state by off stateMoment.
In the present embodiment, the first control signal VQsInterval T1 of the corresponding very first time and the second control signal VQcCorrespondingThe second time interval T2 difference. Both can have different initial times and the identical finish time.
As shown in Figure 3, control signal acquisition cuicuit Ctrl32 comprises the first delay pulse circuit DP1, the second delay pulseCircuit DP2, the first rest-set flip-flop RS1, the second rest-set flip-flop RS2, overvoltage comparator CMP1 and logic circuit OUT1.
The first delay pulse circuit DP1 input pulse-width signal VPWM, its output is connected to the first rest-set flip-flop RS1Reset terminal, for exporting the first reset pulse, with respect to conducting switching instant, when the first reset pulse is delayed the first delayBetween d1.
The second delay pulse circuit DP2 input pulse-width signal VPWM, its output is connected to the second rest-set flip-flop RS2Reset terminal, for exporting the second reset pulse, with respect to conducting switching instant, when the second reset pulse is delayed the second delayBetween d2.
Wherein, first time delay d1 be greater than second time delay d2.
Preferably, as shown in Figure 4, delay pulse circuit can adopt signal delay circuit DL and pulse generative circuit OSBe composed in series. Signal delay circuit DL postpones predetermined time output to its input signal, and pulse generative circuit OS is according to itThe rising edge of input signal triggers output single pulse signal.
The in-phase input end input power supply input terminal voltage Vcc of overvoltage comparator CMP1, inverting input is inputted the first thresholdThreshold voltage Vth1, first threshold voltage Vth1Define in main power transistor conduction period for power supply capacitor CSChargeUpper voltage limit. The output while of overvoltage comparator CMP1 and the set end of the first rest-set flip-flop RS1 and the second rest-set flip-flop RS2Connect, rise to and be greater than first threshold voltage V at power supply input terminal voltage Vccth1Time export set pulse.
In Fig. 3, logic circuit OUT1 is logical AND gate, and its input is inputted respectively the output of the first rest-set flip-flop RS1Signal and pulse-width signal VPWM, output the first control signal VQs. Certainly, one of ordinary skill in the art will readily recognize that logic circuitOUT1 can make amendment adaptively according to the implication of each signal low and high level representative is different, as long as ensure the of outputOne control signal VQsAt output signal and the pulse-width signal V of the first rest-set flip-flop RS1PWMWhile being conducting state in leadingLogical state, at output signal or the pulse-width signal V of the first rest-set flip-flop RS1PWMDuring for off state in off stateCan.
The second rest-set flip-flop RS2 exports the second control signal V according to set pulse and the reset pulse of inputQc。
Fig. 5 is the signal waveform schematic diagram of the isolated converter of second embodiment of the invention. Below in conjunction with Fig. 5, this is describedThe operation principle of the isolated converter of embodiment. In the present embodiment, taking high level as conducting state, low level is for turn-offing shapeState is that example describes. Certainly, one of ordinary skill in the art will readily recognize that the consideration for other side, also can be by low levelBe set to conducting state, high level is set to off state. Can also different fingers be set for different switches or transistorShow level, for example, for pulse-width signal VPWM, high level is indicated conducting and low level instruction shutoff, simultaneously for the first controlSignal V processedQs, high level is indicated conducting and low level instruction shutoff. In order to be adapted to, the variation of level definition makes circuitChange be only those skilled in the art can make be equal to replacement.
As shown in Figure 5, in the t0 moment, also at pulse-width signal VPWMWhile switching to conducting state by off state, arteries and veinsWide modulation signal is VPWMHigh level, now, the first rest-set flip-flop RS1 and the second rest-set flip-flop RS2 are all in SM set mode, allOutput high level, therefore, the first control signal VQsWith the second control signal VQcBe high level. Now, main power transistor QMGrid voltage equal supply voltage Vcc, due to source drive transistor QSConducting, main power transistor QMSource voltage be0. Therefore, main power transistor QMGate source voltage equal Vcc, thereby make the power transistor Q of winnerMDriven conducting, now electricityStream flows through former limit winding L 1, and rises gradually, and transformer T carries out energy storage.
In the t1 moment, it (is also pulse-width signal V apart from the t0 momentPWMRising edge) time while being the second delayBetween d2, the second delay pulse circuit DP2 exports reset pulse at this moment, and second of the second rest-set flip-flop RS2 output is controlledSignal VQcSwitch to low level by high level. Due to first time delay d1 be greater than second time delay d2, therefore, in the time of t1Carve the first control signal VQsStill be high level.
In the t0 moment to the t2 moment, power supply input terminal voltage Vcc continuous decrease.
In the t2 moment, it (is also pulse-width signal V apart from the t0 momentPWMRising edge) time while being the first delayBetween d1, the first delay pulse circuit DP1 exports reset pulse at this moment, makes the output signal of the first rest-set flip-flop RS1 by heightLevel switches to low level. Therefore, the first control signal V of logic circuit OUT1 outputQsSwitch to low level by high level.
In the t2 moment to the t3 moment, the first control signal VQsWith the second control signal VQcAll remain low level, make sourceUtmost point driving transistors QSWith auxiliary switch QCKeep turn-offing. Due to source drive transistor QSTurn-off main power transistor QMSourcePole tension by lifting gradually until the input terminal voltage Vcc that equals to power makes clamp diode D2 conducting, by main power crystalPipe QMSource voltage be clamped at Vcc. Due to auxiliary switch Q nowCAlso in off state, main power transistor QMGrid sourceElectric capacity does not have discharge channel, main power transistor QMGrid and source electrode between voltage difference remain unchanged, make winner's power crystalline substanceBody pipe QMKeep conducting. During this period, the inductive current I of former limit windingpBy clamp diode D2 to power supply capacitor CSFillElectricity, compensation supply voltage Vcc. During this period, power supply input terminal voltage Vcc continues to rise.
In the t3 moment, power supply input terminal voltage Vcc rises to predetermined first threshold voltage Vth1, now, overvoltage comparatorCMP1 exports high level, and the first rest-set flip-flop RS1 and the second rest-set flip-flop RS2 are set, and all exports high level. Therefore,The second control signal VQcFor high level. Meanwhile, due in the t3 moment, pulse-width signal VPWMFor high level, therefore, the first controlSignal V processedQsAlso be high level. Therefore, in this moment, source drive transistor QSWith auxiliary switch QCSwitched to by shutoff simultaneouslyConducting. Make the power transistor Q of winnerMSource voltage pulled down to 0, clamp diode D2 turn-off, the inductance electricity of former limit windingStream IpBy source drive transistor QSFlow to earth point, stop power supply capacitor CSCharging. Owing to stopping power supply capacitor CSFillElectricity, power supply input terminal voltage Vcc is from first threshold voltage Vth1Start continuous decrease, make overvoltage comparator CMP1 export low electricityFlat.
In the t3 moment, to the t4 moment, power supply input terminal voltage Vcc is from first threshold voltage Vth1Start continuous decrease. Former limitThe inductive current I of windingpStill linear increasing.
In the t4 moment, pulse-width signal VPWMSwitch to low level by high level, make the of logic circuit OUT1 outputOne control signal VQsBecome low level. Thus, source drive transistor QSTurn-off. Now the second control signal VQcStill keep highLevel, makes auxiliary switch QcKeep conducting. Due to source drive transistor QSTurn-off main power transistor QMSource voltageBe elevated, make clamp diode D2 conducting, thereby make the power transistor Q of winnerMGate source voltage decline, and then make winner's meritRate transistor QMTurn-off.
In the t4 moment to the t5 moment, due to main power transistor QMTurn-off the inductive current I of former limit windingpLinearity reduces,The inductive current I of secondary windingsLinear increase, the leakage inductance of former limit winding and main power transistor QMParasitic capacitance resonance, therebyIn the time approaching t5 moment, main power transistor QMDrain voltage VdWith source voltage VsWaveform vibrate.
Preferably, in the time that isolated converter 30 comprises absorbing circuit, at main power transistor QMAfter being turned off, its drain electrodeVoltage VdBe lifted very soon, and be absorbed circuit clamping. Absorbing circuit comprises absorption resistance R, Absorption Capacitance C and absorbing circuit pincersPosition diode D3. Work as VdWhile rising fast, absorbing circuit clamp diode D3 conducting, the inductive current I of former limit windingpTo absorptionCapacitor C charging, then the voltage at Absorption Capacitance C two ends is absorbed resistance R consumption, to prevent main power transistor QMWhen shutoffDrain-source voltage is too high and breakdown.
In the t5 moment, former limit winding L 1 and 2 changes of current of secondary winding L complete. The inductive current I of secondary windingsReach maximumValue. After the t5 moment, the inductive current I of secondary windingsLinearity reduces, and is the load energy supply of isolated converter output terminal.
Thus, the present embodiment by main power transistor conduction period to power supply capacitor charging, can avoid power supplyThe appearance of brownout situation, has ensured the normal work of control circuit. In the control signal generative circuit of the present embodiment, auxiliarySwitch turn-offs before source drive transistor turn-offs, and can ensure that the transistorized shutoff of source drive can not cause main power crystalPipe mistake is turn-offed, and has good reliability. Meanwhile, the present embodiment adopts overvoltage comparator output signal, controls source electrode simultaneously and drivesMoving transistor and auxiliary switch conducting, component number is less, can reduce circuit scale.
Fig. 6 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of third embodiment of the invention.The other parts of the isolated converter of the present embodiment and the second embodiment are similar, do not repeat them here. The control of the present embodimentSignal generating circuit Ctrl6 comprises pulse-width signal generative circuit Ctrl61 and control signal acquisition cuicuit Ctrl62.
Pulse-width signal generative circuit Ctrl61 is used for generating the main power transistor Q of instructionMThe time of turn-on and turn-offInterval pulse-width signal VPWM。
Control signal acquisition cuicuit Ctrl62 is according to pulse-width signal VPWMVcc generates first with power supply input terminal voltageControl signal VQsWith the second control signal VQc。
Different from the second embodiment, in the present embodiment, the first control signal VQsInterval T1 of the corresponding very first time and theTwo control signal VQcThe second corresponding time interval T2 is identical. Both have identical initial time and the identical finish time.
As shown in Figure 6, control signal acquisition cuicuit Ctrl62 comprises delay pulse circuit DP3, rest-set flip-flop RS3, overvoltageComparator C MP2 and logic circuit OUT2.
Delay pulse circuit DP3 input pulse-width signal VPWM, its output is connected to the reset terminal of rest-set flip-flop RS3,Be used for exporting reset pulse, with respect to conducting switching instant, reset pulse be delayed first time delay d1. At the present embodimentIn, first time delay d1 can arrange identically with the second embodiment. Conducting switching instant is pulse-modulated signal VPWMByOff state switches to the moment of conducting state.
Overvoltage comparator CMP2 is connected to the set end of rest-set flip-flop RS3, and at power supply input terminal voltage, Vcc is greater than the first thresholdThreshold voltage Vth1Time export set pulse.
Rest-set flip-flop RS3 exports the second control signal VQc。
Logic circuit OUT2 is according to the output signal of rest-set flip-flop and pulse-width signal VPWMExport the first control signalVQs, make the first control signal VQsAt the output signal V of rest-set flip-flop RS3QcWith pulse-width signal VPWMBe conducting stateTime in conducting state, at output signal or the pulse-width signal V of rest-set flip-flopPWMDuring for off state in off state.
In Fig. 6, logic circuit OUT2 is logical AND gate, and its input is inputted respectively the output signal of rest-set flip-flop RS3With pulse-width signal VPWM, output the first control signal VQs. Certainly, one of ordinary skill in the art will readily recognize that logic circuit OUT2Can make adaptability revision according to the implication difference of each signal low and high level representative.
The signal waveform difference of the signal waveform of the present embodiment and the second embodiment is in the present embodiment, adjusts in pulsewidthSignal V processedPWMIndicate main power transistor QMConduction period, the first control signal VQsWith the second control signal VQcControl source electrode drivesMoving transistor QSWith auxiliary switch QCTurn-off simultaneously, and rise to first threshold voltage V at power supply input terminal voltage Vccth1Same afterwardsTime conducting.
By above setting, the control signal generative circuit number of elements of the present embodiment is less, can further reduce electricityRoad scale.
Fig. 7 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of fourth embodiment of the invention.The other parts of the isolated converter of the present embodiment and the second embodiment are similar, do not repeat them here. The control of the present embodimentSignal generating circuit Ctrl7 comprises pulse-width signal generative circuit Ctrl71 and control signal acquisition cuicuit Ctrl72.
Pulse-width signal generative circuit Ctrl71 is used for generating the main power transistor Q of instructionMThe time of turn-on and turn-offInterval pulse-width signal VPWM。
Control signal acquisition cuicuit Ctrl72 is according to pulse-width signal VPWMVcc generates first with power supply input terminal voltageControl signal VQsWith the second control signal VQc。
In the present embodiment, the first control signal VQsInterval T1 of the corresponding very first time and the second control signal VQcCorrespondingThe second time interval T2 difference. Both can have different initial times and the identical finish time.
Different from the second embodiment, the control signal acquisition cuicuit Ctrl72 of the present embodiment has different circuit knotsStructure. As shown in Figure 7, control signal acquisition cuicuit Ctrl72 comprise the first under-voltage comparator CMP3, the second under-voltage comparator CMP4,Pulse generative circuit OS1, the first logic circuit LG1, the second logic circuit LG2, overvoltage comparator CMP5, the first rest-set flip-flopRS4, the second rest-set flip-flop RS5 and the 3rd logic circuit OUT3.
The first under-voltage comparator CMP3 input power supply input terminal voltage Vcc and Second Threshold voltage Vth2, supplying electrical inputVoltage vcc is less than Second Threshold voltage Vth2Time export the first under-voltage pulse.
The second under-voltage comparator CMP4 input power supply input terminal voltage Vcc and the 3rd threshold voltage Vth3, supplying electrical inputVoltage vcc is less than the 3rd threshold voltage Vth3Time export the second under-voltage signal. Second Threshold voltage Vth2Be less than the 3rd threshold voltageVth3。
Pulse generative circuit OS1 inputs the second under-voltage signal and exports the second under-voltage pulse.
The first logic circuit LG1 inputs the first under-voltage pulse and pulse-width signal VPWM, and be connected to the first rest-set flip-flopThe reset terminal of RS4, at pulse-width signal VPWMWhile exporting the first under-voltage pulse for conducting state and the first under-voltage comparator, defeatedGo out the first reset pulse.
The second logic circuit LG2 inputs the second under-voltage pulse and pulse-width signal VPWM, and be connected to the second rest-set flip-flopThe reset terminal of RS5, at pulse-width signal VPWMWhile exporting the second under-voltage signal for conducting state and the second under-voltage comparator, defeatedGo out the second reset pulse.
Overvoltage comparator CMP5 is connected to the set end of the first rest-set flip-flop RS4 and the second rest-set flip-flop RS5, defeated in power supplyEnter terminal voltage Vcc and be greater than first threshold voltage Vth1Time export set pulse.
The 3rd logic circuit OUT3 is according to the output signal of the first rest-set flip-flop RS4 and pulse-width signal VPWMOutput theOne control signal VQs, the first control signal VQsAt output signal and the pulse-width signal V of the first rest-set flip-flop RS4PWMBeWhen conducting state in conducting state, at output signal or the pulse-width signal V of the first rest-set flip-flop RS4PWMFor off stateTime in off state.
The second rest-set flip-flop RS5 is used for exporting the second control signal VQc。
In Fig. 7, the first logic circuit LG1, the second logic circuit LG2 and the 3rd logic circuit OUT3 are logical ANDDoor.
Certainly, one of ordinary skill in the art will readily recognize that above-mentioned each logic circuit can be according to each signal low and high level institute's generationThe implication difference of table is made amendment adaptively, as long as ensure to realize the logic function of its required realization.
Fig. 8 is the signal waveform schematic diagram of the isolated converter of fourth embodiment of the invention. Below in conjunction with Fig. 8, this is describedThe operation principle of the isolated converter of embodiment. In the present embodiment, using high level as instruction conducting, low level instruction is closedBreak and describe for example. Certainly, one of ordinary skill in the art will readily recognize that the consideration for other side, also can be by low levelBe set to conducting state, high level is set to off state.
In the t0 moment to the t2 ' moment, due to source drive transistor QSConducting, main power transistor QMSource voltage be0. Clamp diode D2 is in off state, power supply input terminal voltage Vcc continuous decrease.
At source drive transistor QSWhen shutoff, if auxiliary switch QCIn conducting state, Hui Shi winner power transistorQMGate source voltage become fast 0, and then cause main power transistor QMTurn-off. Therefore, in order to keep main power transistor QMDimensionHold conducting state, auxiliary switch QCTurn-off time interval (also the second time interval) need to be greater than source drive transistor QSTurn-off time interval (being also very first time interval) or at least with source drive transistor QSTurn-off time interval identical.Accordingly, need to make the 3rd threshold voltage Vth3Be greater than Second Threshold voltage Vth2。
In the t1 ' moment, power supply input terminal voltage Vcc drops to the 3rd threshold voltage Vth3, the second under-voltage comparator CMP4 is defeatedGo out high level. Due to pulse-width signal V nowPWMFor high level, therefore the second logic circuit LG2 output high level, makes theTwo rest-set flip-flop RS5 reset. Thus, the second control signal V of the second rest-set flip-flop RS5 outputQcFor low level, auxiliary switch QCTurn-off.
In the t1 ' moment, to the t2 ' moment, power supply input terminal voltage Vcc continues to decline.
In the t2 ' moment, power supply input terminal voltage Vcc drops to Second Threshold voltage Vth2, the first under-voltage comparator CMP3 is defeatedGo out high level. Due to pulse-width signal V nowPWMFor high level, therefore the first logic circuit LG1 output high level, makes theOne rest-set flip-flop RS4 resets. Thus, the first rest-set flip-flop RS4 output low level, and then make the first control signal VQsFor low electricityFlat, source drive transistor QSTurn-off. Now, main power transistor QMSource voltage by lifting gradually until equal to power defeatedThe supply voltage Vcc that enters end, makes clamp diode D2 conducting, by main power transistor QMSource voltage be clamped at Vcc.The inductive current I of former limit windingpStart power supply capacitor CSCharging.
Hence one can see that, Second Threshold voltage Vth2In fact having limited power supply input terminal voltage Vcc leads at main power transistorLower limit during logical.
In the t2 ' moment, to the t3 moment, power supply input terminal voltage Vcc continues to rise.
In the t3 moment, power supply input terminal voltage Vcc rises to predetermined first threshold voltage Vth1. With the second embodiment classSeemingly, overvoltage comparator CMP5 exports set pulse, finally makes the first control signal VQsWith the second control signal VQcBe high electricityFlat, now charging process finishes.
Thus, the present embodiment by main power transistor conduction period to power supply capacitor charging, can avoid power supply electricityPress the appearance of too low situation, ensured the normal work of control circuit. The control signal generative circuit of the present embodiment is based on threshold valueVoltage is controlled the zero hour to power supply capacitor charging, thereby accurately controls charging process.
Fig. 9 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of fifth embodiment of the invention.The other parts of the isolated converter of the present embodiment and the 4th embodiment are similar, do not repeat them here. The control of the present embodimentSignal generating circuit Ctrl9 comprises pulse-width signal generative circuit Ctrl91 and control signal acquisition cuicuit Ctrl92.
Pulse-width signal generative circuit Ctrl91 is used for generating the main power transistor Q of instructionMThe time of turn-on and turn-offInterval pulse-width signal VPWM。
Control signal acquisition cuicuit Ctrl92 is according to pulse-width signal VPWMVcc generates first with power supply input terminal voltageControl signal VQsWith the second control signal VQc。
Different from the 4th embodiment, in the present embodiment, the first control signal VQsInterval T1 of the corresponding very first time and theTwo control signal VQcThe second corresponding time interval T2 is identical. Both have identical initial time and the identical finish time.
As shown in Figure 9, control signal acquisition cuicuit Ctrl92 comprises under-voltage comparator CMP6, the first logic circuit LG3, mistakePress comparator CMP7, rest-set flip-flop RS6, the second logic circuit OUT4.
Under-voltage comparator CMP6 is less than Second Threshold voltage V at power supply input terminal voltage Vccth2Time, export under-voltage pulse.
The first logic circuit LG3 input undervoltage pulse and pulse-width signal VPWM, at pulse-width signal VPWMInstruction is mainPower transistor QMWhen conducting and under-voltage comparator CMP6 export under-voltage pulse, reset to the reset terminal output of rest-set flip-flop RS6Pulse.
Overvoltage comparator CMP7 is connected to the set end of rest-set flip-flop RS6, and at power supply input terminal voltage, Vcc is greater than the first thresholdThreshold voltage Vth1Time, output set pulse.
Rest-set flip-flop RS6 exports the second control signal VQc。
Output signal and the pulse-width signal V of the second logic circuit OUT4 input rest-set flip-flop RS6PWM, and export firstControl signal VQs, make the first control signal VQsAt output signal and the pulse-width signal V of rest-set flip-flop RS6PWMBe and leadWhen logical in conducting state, at output signal or the pulse-width signal V of rest-set flip-flopPWMFor turn-off time in off state.
Similar with the 4th embodiment, the first logic circuit LG3 and the second logic circuit OUT4 are logical AND gate. WhenSo, one of ordinary skill in the art will readily recognize that above-mentioned each logic circuit can be according to the implication of each signal low and high level representative notWith making amendment adaptively, as long as ensure to realize the logic function of its required realization.
The signal waveform difference of the signal waveform of the present embodiment and the second embodiment is, at pulse-width signalVPWMIndicate main power transistor QMConduction period, the first control signal VQsWith the second control signal VQcControl source drive crystalPipe QSWith auxiliary switch QCTurn-off simultaneously, and rise to first threshold voltage V at power supply input terminal voltage Vccth1Rear while conducting.
By above setting, the control signal generative circuit of the present embodiment in accurately controlling charging process, elementNegligible amounts, can further reduce circuit scale.
The above second to the 5th embodiment all makes the first control signal and very first time district corresponding to the second control signalBetween and the second time interval there is the identical finish time. But, it will be understood by those skilled in the art that it is only for simplificationThe consideration of control signal generative circuit structure, but not realize the unique selection of the object of the invention. For the consideration of other side, alsoCan make very first time interval and the second time interval there is the different finish times by for example increasing delay circuit.
Figure 10 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of sixth embodiment of the invention.The other parts of the isolated converter of the present embodiment and the second embodiment are similar, do not repeat them here. The control of the present embodimentSignal generating circuit Ctrl10 comprises pulse-width signal generative circuit Ctrl101 and control signal acquisition cuicuit Ctrl102.
Pulse-width signal generative circuit Ctrl101 is used for generating the main power transistor Q of instructionMThe time of turn-on and turn-offInterval pulse-width signal VPWM, to realize accurate constant current control.
Control signal acquisition cuicuit Ctrl102 is according to pulse-width signal VPWMDescribed in generating with power supply input terminal voltage VccThe first control signal VQsWith the second control signal VQc。
In the present embodiment, pulse-width signal generative circuit Ctrl101 comprises former limit peak point current sampling hold circuitPEAK, controlled integrating circuit INTE, integral control circuit INTEC and pulsewidth modulation acquisition cuicuit PWM.
Former limit peak point current sampling hold circuit PEAK is connected to controlled integrating circuit INTE, to controlled integrating circuit INTEExport former limit peak point current sampled signal, this signal is the voltage signal that characterizes former limit peak point current.
According to the control of integral control circuit INTEC, controlled integrating circuit INTE output voltage compensation signal Vc, described electricityPress compensating signal VcAccording to described former limit peak point current sampled signal and reference voltage VrefDifference integration and obtain.
Pulsewidth modulation acquisition cuicuit PWM is used for according to described voltage compensation signal VcOutput pulse width modulation signal. Pulsewidth is adjustedAcquisition cuicuit PWM processed can use existing all kinds of circuit structure to realize.
Wherein, integral control circuit INTEC is in former limit winding inductance electric current IpBe decreased at 1 o'clock (in Fig. 5 by peak value linearityThe t5 moment) control controlled integrating circuit INTE and start to carry out integration, in secondary winding inductance electric current IsBe decreased to by peak value linearity1 o'clock (t6 moment in Fig. 5) controlled controlled integrating circuit INTE and stops integration.
Preferably, this enforcement, using the following moment as the moment that starts integration, also, meets power supply input terminal voltage VccWith main power transistor source voltage VsDifference be less than the 4th voltage threshold Vth4, pulse-width signal V simultaneouslyPWMFor turn-offing shapeThe moment of state.
More preferably, integral control circuit INTEC comprises that zero passage comparison circuit A1, pulse generative circuit OS2, zero passage patrolCollect circuit LG4, integration control rest-set flip-flop RS7 and secondary inductance current over-zero testing circuit PZ.
Zero passage comparison circuit A1 specifically comprises comparator C MP8 and threshold voltage source, and the voltage of threshold voltage source is the 4th electricityPress threshold value Vth4. The high-pressure side of threshold voltage source is connected to the in-phase input end of comparator C MP8, and low-pressure end is connected to source electrode and connectsEnd. The reverse input end input power supply input terminal voltage Vcc of comparator C MP8. The output of comparator C MP8 is as crossing zero balancingThe output of circuit A1, it is connected to pulse generative circuit OS2. Zero passage comparison circuit A1 power supply input terminal voltage Vcc withMain power transistor source voltage VsDifference be less than the 4th voltage threshold Vth4Time export zero cross signal.
Pulse generative circuit OS2 inputs zero cross signal, and to zero passage logic circuit LG4 output zero-crossing pulse signal.
Zero passage logic circuit LG4 inputs described zero-crossing pulse signal and described pulse-width signal VPWM, and to integration controlThe set end output set pulse of rest-set flip-flop RS7.
Secondary inductance current over-zero testing circuit PZ, in the time of secondary winding inductance electric current positive going zeror crossing, touches to integration control RSThe reset terminal output reset pulse of hair device RS7.
Integration control rest-set flip-flop RS7 exports integral control signal.
Meanwhile, controlled integrating circuit INTE can comprise the first switch S 1, second switch S2, filter circuit RC and integration electricityRoad INT.
The first switch S 1 is connected to the defeated of the output of former limit peak point current sampling hold circuit PEAK and filter circuit RCEnter between end. Second switch S2 is connected between the input and earth point of filter circuit RC. The first switch S 1 is in integration controlConducting when signal is high level is turn-offed in the time that integral control signal is low level. Second switch S2 integral control signal is high electricityTurn-off at ordinary times conducting in the time that integral control signal is low level.
Filter circuit RC comprises filter resistance RfWith filter capacitor Cf. Integrating circuit INT comprises trsanscondutance amplifier GM and connectionAmplify the building-out capacitor C between output and earth point in mutual conductancec. The inverting input of trsanscondutance amplifier GM and filter circuit RCOutput connect, its in-phase input end input reference voltage Vref。
One of ordinary skill in the art will readily recognize that controlled integrating circuit INTE can also use other those skilled in the art ripeIn that know or prior art, disclosed circuit structure is realized.
Known according to the circuit topology of anti exciting converter, output current meets following formula, that is:
Wherein, IoFor output current, tsBe the switch periods of main power transistor, NpFor former limit umber of turn, NsFor secondaryUmber of turn, tdisFor the discharge time (or being called the degaussing time) of secondary winding, Ipk1For the inductive current peak of former limit winding.
In order to obtain constant output current Io, at the switch periods t of main power transistorsOne timing, can be by controllingCircuit makes the inductive current peak I of former limit windingpk1T discharge time with secondary windingdisProduct constant. Also, profitWith the inductive current peak I of former limit windingpk1T discharge time with secondary windingdisProduct as control parameter generate pulsewidthModulation signal VPWM。
In the prior art, conventionally use the turn-off time t of main power transistordis' while being used as the electric discharge of secondary windingBetween. But, as shown in Figure 5, the turn-off time t of main power transistordis' time (in Fig. 5 of comprising the former secondary winding change of currentThe t4 moment is to the t5 moment) and discharge time (the t5 moment in Fig. 5 is to the t7 moment) of secondary winding. Hence one can see that, tdis' alsoBe not the actual discharge time of secondary winding, thereby the control mode inaccuracy of prior art, can be to isolated converter constant currentThe accuracy of controlling forms harmful effect.
The present embodiment is by accurately controlling the time interval of integration, also, and based on accurate discharge time of tdisControlSystem, to improve the constant-current control accuracy of isolated converter.
Known with reference to figure 5, in the t4 moment, to the t5 moment, former limit winding L 1 and secondary winding L 2 are carried out the change of current, former limit windingInductive current IpLinearity reduces, the inductive current I of secondary windingsLinear increase. The leakage inductance of former limit winding and main power transistorQMParasitic capacitance resonance, thereby in the time approaching t5 moment, main power transistor QMSource voltage VSWaveform vibrate.Due to the existence of clamp diode D2, source voltage VSWaveform shielded by clamp diode D2. Meanwhile, due to feeder earThe fall of voltage vcc is with respect to VSOscillating waveform amplitude is negligible, therefore, feeder ear voltage vcc can be doneFor standard of comparison judges source voltage VSOscillation amplitude. Make feeder ear voltage vcc and source voltage V in this oscillation amplitudeSDifference is less than predefined the 4th voltage threshold Vth4Time, can think and detect that the former secondary change of current completes, and with this moment workFor t discharge timedisInitial time.
In the t6 moment, the inductive current I of secondary windingsBe reduced at 1 o'clock by peak value, the source voltage V of main power transistorSReduce, now, think the inductive current zero crossing of secondary winding, thereby obtain the finish time of discharge time suddenly.
The present embodiment, by accurately controlling the time interval of integration, has improved the constant-current control accuracy of isolated converter.
The pulse-width signal generative circuit that it will be understood by those skilled in the art that the present embodiment can be applied to above-mentionedOne to the 5th embodiment, to improve the constant-current control accuracy of isolated converter.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for those skilled in the art, the present invention can have various changes and variation. All any amendments of doing within spirit of the present invention and principle, be equal toReplacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. for a control circuit for isolated converter, described control circuit comprises for electrical input, grid link, sourceUtmost point link, source drive transistor, auxiliary switch, clamp diode and control signal generative circuit;
Described power supply electric capacity of powering for being connected to described control circuit for electrical input; Described grid link is used for and instituteThe grid of stating the main power transistor of isolated converter connects; Described source electrode link is for described main power transistorSource electrode connects;
Described source drive transistor is connected between described source electrode link and earth point;
Described auxiliary switch is connected to described grid link and described between electrical input;
Described clamp diode is connected to described between electrical input and described source electrode link;
Described control signal generative circuit is used for generating the first control signal and the second control signal; Described the first control signal controlMake described source drive transistor interval shutoff of the very first time, auxiliary switch is second described in described the second control signal controlTime interval turn-offs, and described very first time interval and described the second time interval are positioned at pulse-width signal and indicate main power crystalIn the time interval of pipe conducting; Described the second time interval be greater than described very first time interval or with interval phase of the described very first timeWith.
2. the control circuit for isolated converter according to claim 1, is characterized in that, described control signal is rawBecome circuit to comprise pulse-width signal generative circuit and control signal acquisition cuicuit;
Described pulse-width signal generative circuit is used for generating described pulse-width signal, and described pulse-width signal is used to indicateThe shutoff of described main power transistor and conducting;
Described control signal acquisition cuicuit is used for according to described in described pulse-width signal and the generation of described power supply input terminal voltageThe first control signal and the second control signal.
3. the control circuit for isolated converter according to claim 2, is characterized in that, described control signal obtainsSense circuit comprises the first delay pulse circuit, the second delay pulse circuit, the first rest-set flip-flop, the second rest-set flip-flop, crosses pressure ratioCompared with device and logic circuit;
Described the first delay pulse circuit is used for exporting the first reset pulse to the reset terminal of described the first rest-set flip-flop, with respect toConducting switching instant, described the first reset pulse was delayed for the first time delay;
Described the second delay pulse circuit is used for exporting the second reset pulse to the reset terminal of described the second rest-set flip-flop, with respect toDescribed conducting switching instant, described the second reset pulse was delayed for the second time delay;
Described conducting switching instant is described pulse-modulated signal is switched to conducting state moment by off state; Described firstBe greater than described the second time delay time delay;
Described overvoltage comparator is connected to the set end of described the first rest-set flip-flop and the second rest-set flip-flop, in described power supply inputWhen being greater than first threshold voltage, terminal voltage exports set pulse;
Described logic circuit is exported described the first control signal, adjusts in output signal and the described pulsewidth of described the first rest-set flip-flopWhen signal processed is conducting state, described the first control signal is in conducting state; At the output letter of described the first rest-set flip-flopNumber or described pulse-width signal while being off state, described the first control signal is in off state;
Described the second rest-set flip-flop is exported described the second control signal.
4. the control circuit for isolated converter according to claim 2, is characterized in that, described control signal obtainsSense circuit comprises delay pulse circuit, rest-set flip-flop, overvoltage comparator and logic circuit;
Described delay pulse circuit is for the reset terminal output reset pulse to described rest-set flip-flop, described reset pulse with respect toConducting switching instant postponed for the first time delay;
Described conducting switching instant is described pulse-modulated signal is switched to conducting state moment by off state;
Described overvoltage comparator is connected to the set end of described rest-set flip-flop, is greater than first threshold at described power supply input terminal voltageWhen voltage, export set pulse;
Described rest-set flip-flop is exported described the second control signal;
Described logic circuit is exported described the first control signal, at output signal and the described pulsewidth modulation letter of described rest-set flip-flopWhile number being conducting state, described the first control signal is in conducting state; The output signal of described rest-set flip-flop or described inWhen pulse-width signal is off state, described the first control signal is in off state.
5. the control circuit for isolated converter according to claim 2, is characterized in that, described control signal obtainsSense circuit comprises the first under-voltage comparator, the second under-voltage comparator, pulse generative circuit, the first logic circuit, the second logicCircuit, overvoltage comparator, the first rest-set flip-flop, the second rest-set flip-flop and the 3rd logic circuit;
Described the first under-voltage comparator is exported the first under-voltage pulse in the time that described power supply input terminal voltage is less than Second Threshold voltage;
Described the second under-voltage comparator is exported the second under-voltage signal in the time that described power supply input terminal voltage is less than the 3rd threshold voltage;Described Second Threshold voltage is less than described the 3rd threshold voltage;
Described pulse generative circuit is exported the second under-voltage pulse according to described the second under-voltage signal;
Described the first logic circuit is connected to the reset terminal of the first rest-set flip-flop, receive described the first under-voltage pulse and described inWhen pulse-width signal is conducting state, output the first reset pulse;
Described the second logic circuit is connected to the reset terminal of the second rest-set flip-flop, receive described the second under-voltage pulse and described inWhen pulse-width signal is conducting state, output the second reset pulse;
Described overvoltage comparator is connected to the set end of described the first rest-set flip-flop and the second rest-set flip-flop, in described power supply inputWhen being greater than first threshold voltage, terminal voltage exports set pulse;
Described the 3rd logic circuit is exported described the first control signal, at output signal and the described arteries and veins of described the first rest-set flip-flopWhen wide modulation signal is conducting state, described the first control signal is in conducting state; Defeated at described the first rest-set flip-flopWhen going out signal or described pulse-width signal and being off state, described the first control signal is in off state;
Described the second rest-set flip-flop is exported described the second control signal.
6. the control circuit for isolated converter according to claim 2, is characterized in that, described control signal obtainsSense circuit comprises under-voltage comparator, the first logic circuit, overvoltage comparator, rest-set flip-flop, the second logic circuit;
Described under-voltage comparator is exported under-voltage pulse in the time that described power supply input terminal voltage is less than Second Threshold voltage;
Described the first logic circuit is connected to the reset terminal of described rest-set flip-flop, is receiving described under-voltage pulse and described pulsewidthWhen modulation signal is conducting state, output reset pulse;
Described overvoltage comparator is connected to the set end of described rest-set flip-flop, is greater than first threshold at described power supply input terminal voltageWhen voltage, output set pulse;
Described rest-set flip-flop is exported described the second control signal;
Described the second logic circuit is exported described the first control signal, at output signal and the pulsewidth modulation letter of described rest-set flip-flopWhile number being conducting state, described the first control signal is in conducting state; In output signal or the pulsewidth of described rest-set flip-flopWhen modulation signal is off state, described the first control signal is in off state.
7. the control circuit for isolated converter according to claim 2, is characterized in that, described pulsewidth modulation letterNumber generative circuit comprises that former limit peak point current sampling hold circuit, controlled integrating circuit, integral control circuit and pulsewidth modulation obtainSense circuit;
Described former limit peak point current sampling hold circuit is connected to described controlled integrating circuit, exports former limit peak point current sampling letterNumber;
According to the control of described integral control circuit, described controlled integrating circuit output voltage compensation signal, described voltage compensationSignal obtains according to the difference integration of described former limit peak point current sampled signal and reference voltage;
Described pulsewidth modulation acquisition cuicuit is exported described pulse-width signal according to described voltage compensation signal;
Wherein, described integral control circuit is decreased at former limit winding inductance electric current at 1 o'clock by peak value linearity and controls described controlled amassingParallel circuit starts to carry out integration, is decreased at 1 o'clock controls described controlled integrating circuit at secondary winding inductance electric current by peak value linearityStop integration.
8. the control circuit for isolated converter according to claim 7, is characterized in that, former limit winding electric electrificationIt is that the difference of described power supply input terminal voltage and main power transistor source voltage is little that stream is decreased to moment of zero by peak value linearityThe moment that is off state in the 4th voltage threshold and described pulse-width signal.
9. the control circuit for isolated converter according to claim 8, is characterized in that, described integration control electricityRoad comprises zero passage comparison circuit, zero passage pulse generative circuit, zero passage logic circuit, integration control rest-set flip-flop and secondary inductanceCurrent over-zero testing circuit;
Described zero passage comparison circuit is connected to described zero passage pulse generative circuit, described power supply input terminal voltage and described masterWhen being less than described the 4th voltage threshold, the difference of power transistor source voltage exports zero cross signal;
Described zero passage pulse generative circuit receives described zero cross signal and believes to described zero passage logic circuit output zero-crossing pulseNumber;
Described zero passage logic circuit is connected with the set end of described integration control rest-set flip-flop, according to described zero-crossing pulse signal andDescribed pulse-width signal output set pulse;
Described secondary inductance current over-zero testing circuit is decreased at secondary winding inductance electric current at 1 o'clock by peak value linearity, to describedThe reset terminal output reset pulse of integration control rest-set flip-flop;
Described integration control rest-set flip-flop output integral control signal.
10. an isolated converter, comprises power stage circuit, the power supply electric capacity and as claim with main power transistorThe control circuit for isolated converter described in 1-9 any one;
The grid of described main power transistor is connected with the grid link of described control circuit, the source of described main power transistorThe utmost point is connected with the source electrode link of described control circuit, described power supply electric capacity be connected to described for electrical input and earth point itBetween.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104038031B (en) * | 2014-07-01 | 2016-05-25 | 矽力杰半导体技术(杭州)有限公司 | A kind of generating circuit of service voltage and Switching Power Supply |
| CN104319983B (en) * | 2014-09-29 | 2017-09-29 | 矽力杰半导体技术(杭州)有限公司 | A kind of source driving method, drive circuit and Switching Power Supply being used in Switching Power Supply |
| CN104410252B (en) * | 2014-12-11 | 2017-09-01 | 矽力杰半导体技术(杭州)有限公司 | Source electrode drive circuit and its control method |
| CN104993682A (en) * | 2015-07-02 | 2015-10-21 | 电子科技大学 | Flyback converter leakage inductor absorption and feedback circuit |
| CN105553259B (en) * | 2016-01-28 | 2018-11-13 | 杰华特微电子（杭州）有限公司 | self-powered control circuit, control method and switching circuit |
| JP6597948B2 (en) | 2017-08-29 | 2019-10-30 | 富士電機株式会社 | Detection device, control device and inverter device |
| CN108880296B (en) * | 2018-06-12 | 2021-01-05 | 昂宝电子（上海）有限公司 | Power supply conversion system |
| CN110429701A (en) * | 2019-09-11 | 2019-11-08 | 芯好半导体(成都)有限公司 | A kind of linear energy recovery circuit, recovery method and electric device |
| CN113541444B (en) * | 2020-04-15 | 2023-03-24 | 成都中启易联科技有限公司 | Current recovery circuit, switch converter and integrated circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010028990A (en) * | 2008-07-22 | 2010-02-04 | Fuji Electric Holdings Co Ltd | Switching power supply |
| CN202334314U (en) * | 2011-11-25 | 2012-07-11 | 成都芯源系统有限公司 | Switching power supply for LED driving and control circuit thereof |
| CN102882359A (en) * | 2012-10-25 | 2013-01-16 | 矽力杰半导体技术(杭州)有限公司 | Bias voltage generation circuit and switching power supply using same |
| CN102969889A (en) * | 2012-11-05 | 2013-03-13 | 矽力杰半导体技术(杭州)有限公司 | Self-powered source driving circuit and switching power supply applying same |
| CN103490648A (en) * | 2013-10-10 | 2014-01-01 | 成都芯源系统有限公司 | Isolated switch converter and control method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0610422D0 (en) * | 2006-05-26 | 2006-07-05 | Cambridge Semiconductor Ltd | Forward power converters |
| US8811037B2 (en) * | 2011-09-05 | 2014-08-19 | Texas Instruments Incorporated | Adaptive driver delay compensation |
-
2014
- 2014-03-06 CN CN201410079336.1A patent/CN103825469B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010028990A (en) * | 2008-07-22 | 2010-02-04 | Fuji Electric Holdings Co Ltd | Switching power supply |
| CN202334314U (en) * | 2011-11-25 | 2012-07-11 | 成都芯源系统有限公司 | Switching power supply for LED driving and control circuit thereof |
| CN102882359A (en) * | 2012-10-25 | 2013-01-16 | 矽力杰半导体技术(杭州)有限公司 | Bias voltage generation circuit and switching power supply using same |
| CN102969889A (en) * | 2012-11-05 | 2013-03-13 | 矽力杰半导体技术(杭州)有限公司 | Self-powered source driving circuit and switching power supply applying same |
| CN103490648A (en) * | 2013-10-10 | 2014-01-01 | 成都芯源系统有限公司 | Isolated switch converter and control method thereof |
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