CN103825469A - Control circuit for isolated type convertor and isolated type convertor - Google Patents
Control circuit for isolated type convertor and isolated type convertor Download PDFInfo
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- CN103825469A CN103825469A CN201410079336.1A CN201410079336A CN103825469A CN 103825469 A CN103825469 A CN 103825469A CN 201410079336 A CN201410079336 A CN 201410079336A CN 103825469 A CN103825469 A CN 103825469A
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Abstract
The invention relates to a control circuit for an isolated type convertor and the isolated type convertor. The control circuit comprises a power supply input end, a grid connecting end, a source connecting end, a source driving transistor, an auxiliary switch, a clamping diode and a control signal generation circuit, wherein the source driving transistor is connected between the source connecting end and an earthing point; the auxiliary switch is connected between the grid connecting end and the power supply input end; the clamping diode is connected between the power supply input end of the source connecting end; the control signal generation circuit is used for generating a first control signal and a second control signal; the first control signal is used for controlling the source driving transistor to be powered off at a first time interval; the second control signal is used for controlling the auxiliary switch to be powered off at a second time interval; the first time interval and the second time interval are positioned within a time interval that a main power transistor is powered on; the second time interval is greater than the first time interval or is identical to the first time interval. By adopting the control circuit, the problem that the source driving type isolated type converter is insufficient in power supply can be solved.
Description
Technical field
The present invention relates to power electronic technology, be specifically related to control circuit and isolated converter for isolated converter.
Background technology
Isolated converter is widely used in various off-line electric power systems.Isolated converter generally includes power stage circuit and control circuit.In existing isolated converter, control circuit is conventionally by power supply capacitances to supply power, and power supply electric capacity need to assist winding that energy is provided.
Thereby the isolated converter of source drive type is suggested to break away from the dependence for auxiliary winding.Fig. 1 is take inverse excitation type converter as having exemplified the circuit diagram of existing isolated converter.As shown in Figure 1, the power stage circuit 11 of isolated converter 10 comprises main power transistor Q
m, its control circuit 12 comprises control signal generative circuit Ctrl1 and source drive transistor Q
s, by controlling source drive transistor Q
soN/OFF, can change main power transistor Q
mthe voltage of source electrode, and then change main power transistor Q
mgate source voltage, thus make the power transistor Q of winner
mwith source drive transistor Q
ssynchronous ON/OFF.
Isolated converter shown in Fig. 1 can be realized the power supply to control circuit without auxiliary winding, and the supply power voltage of powering for control circuit 12 is at main power transistor Q
mconduction period, by main power transistor Q
mdrain-source electric capacity (being also the parasitic capacitance of transistor drain-source end) produce electric current to power supply capacitor C
scharging produces, and still, the situation of electricity shortage easily appears in existing circuit structure, affects control circuit and normally works.
Summary of the invention
In view of this, the present invention has overcome the defect for the control circuit electricity shortage of isolated converter.
In first aspect, a kind of control circuit is proposed, for isolated converter, described control circuit comprises for electrical input, grid link, source electrode link, source drive transistor, auxiliary switch, clamping diode and control signal generative circuit;
Described power supply electric capacity of powering for being connected to described control circuit for electrical input; Described grid link is for being connected with the grid of the main power transistor of described isolated converter; Described source electrode link is for being connected with the source electrode of described main power transistor;
Described source drive transistor is connected between described source electrode link and earth point;
Described auxiliary switch is connected to described grid link and described between electrical input;
Described clamping diode is connected to described between electrical input and described source electrode link;
Described control signal generative circuit is used for generating the first control signal and the second control signal; Described in described the first control signal control, source drive transistor is interval shutoff of the very first time, described in described the second control signal control, auxiliary switch turn-offs at the second time interval, and interval and described the second time interval of described very first time is positioned at pulse-width signal indicates the time interval of main power transistor conducting; It is interval or identical with described very first time interval that described the second time interval is greater than the described very first time.
In second aspect, provide a kind of isolated converter to comprise and there is the power stage circuit of main power transistor, power electric capacity and control circuit as above;
The grid of described main power transistor is connected with the grid link of described control circuit, and the source electrode of described main power transistor is connected with the source electrode link of described control circuit, and described power supply electric capacity is connected to described between electrical input and earth point.
The present invention arranges auxiliary switch by the grid at main power transistor and control circuit between electrical input, and control auxiliary switch and source drive transistor turn-offs between the winding current rising stage of former limit, make the electric current that flows through former limit winding pass through main power transistor to power supply capacitor charging, avoid the appearance of the too low situation of supply power voltage, guaranteed the normal work of control circuit.
Accompanying drawing explanation
By the description to the embodiment of the present invention referring to accompanying drawing, above-mentioned and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:
Fig. 1 is the circuit diagram of the isolated converter of source drive type in prior art;
Fig. 2 is the circuit diagram of the isolated converter of first embodiment of the invention;
Fig. 3 is the circuit diagram of the isolated converter of second embodiment of the invention;
Fig. 4 is a preferred circuit schematic diagram of delay pulse circuit in second embodiment of the invention;
Fig. 5 is the signal waveform schematic diagram of the isolated converter of second embodiment of the invention;
Fig. 6 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of third embodiment of the invention;
Fig. 7 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of fourth embodiment of the invention;
Fig. 8 is the signal waveform schematic diagram of the isolated converter of fourth embodiment of the invention;
Fig. 9 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of fifth embodiment of the invention;
Figure 10 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of sixth embodiment of the invention.
Embodiment
Based on preferred embodiment, present invention is described below, but the present invention is not restricted to these embodiment.In below details of the present invention being described, detailed some specific detail sections of having described.Do not have for a person skilled in the art the description of these detail sections can understand the present invention completely yet.For fear of obscuring essence of the present invention, known method, process, flow process, element and circuit do not describe in detail.
In addition, it should be understood by one skilled in the art that the accompanying drawing providing at this is all for illustrative purposes, and accompanying drawing not necessarily in proportion draw.
, should be appreciated that in the following description, " circuit " refers to the galvanic circle being connected and composed by electrical connection or electromagnetism by least one element or electronic circuit meanwhile.In the time claiming that element or circuit " are connected to " another element or claim that element/circuit " is connected to " between two nodes, it can be directly couple or be connected to another element or can have intermediary element, and the connection between element can be physically, in logic or its combination.On the contrary, when claiming element " to be directly coupled to " or when " being directly connected to " another element, meaning that both do not exist intermediary element.
Unless context explicitly calls for, otherwise the implication that " comprising ", " comprising " etc. in whole specification and claims, similar word should be interpreted as comprising rather than exclusive or exhaustive implication; That is to say, be the implication of " including but not limited to ".
In description of the invention, it will be appreciated that, term " first ", " second " etc. are only for describing object, and can not be interpreted as indication or hint relative importance.In addition,, in description of the invention, except as otherwise noted, the implication of " multiple " is two or more.
In the present invention, be useful on and control the control signal of transistor or switch or include two states for generating the signal of control signal, also be off state and conducting state, when control signal is during in off state, transistor or the switch of its control are turned off, and when control signal is during in conducting state, transistor or the switch of its control are switched on.
The present invention can be applied to any isolated converter, in the following detailed description, only explains specific works principle of the present invention as an example of inverse excitation type converter (flyback converter) example.
Fig. 2 is the circuit diagram of the isolated converter of first embodiment of the invention.As shown in Figure 2, isolated converter 20 comprises power stage circuit 21, the power supply capacitor C with main power transistor
swith control circuit 22.
Particularly, power stage circuit 21 comprises transformer T, main power transistor Q
mwith secondary current rectifying and wave filtering circuit.Transformer T comprises the former limit winding L 1 and the secondary winding L 2 that intercouple.Secondary current rectifying and wave filtering circuit is connected with secondary winding L 2.
Main power transistor Q
mgrid be connected with the grid link g of control circuit 32, main power transistor Q
msource electrode be connected with the source electrode link s of control circuit 32, power supply capacitor C
sbe connected to between electrical input cc and earth point gnd.
In control circuit 22, be used for being connected to for electrical input cc the power supply capacitor C that control circuit 22 is powered
s; Grid link g is used for the main power transistor Q with isolated converter 20
mgrid connect; Source electrode link s is used for and main power transistor Q
msource electrode connect.
Source drive transistor Q
sbe connected between source electrode link s and earth point gnd.
Auxiliary switch Q
cbe connected to grid link g and supply between electrical input cc.
Clamping diode D2 is connected to between electrical input cc and source electrode link s.
Control signal generative circuit Ctrl2 is used for generating the first control signal V
qswith the second control signal V
qc, and output to respectively source drive transistor Q
swith auxiliary switch Q
ccontrol end.The first control signal V
qscontrol source drive transistor Q
sin the very first time, interval T1 turn-offs, the second control signal V
qccontrol auxiliary switch Q
cturn-off at the second time interval T2, interval T1 of the very first time and the second time interval T2 are positioned at pulse-width signal PWM and indicate main power transistor Q
min the time interval of conducting, and the second time interval T2 is greater than interval T1 of the very first time or identical with interval T1 of the very first time.
The circuit working principle of the present embodiment is as follows, and control signal generative circuit Ctrl2 can for example, determine the main power transistor Q of indication according to feedback parameters (, output voltage, primary current etc.)
mthe pulse-width signal V of turn-on and turn-off state
pWM(PWM, Pulse Width Modulation), and generate the first control signal V based on this signal
qswith the second control signal V
qc, at pulse-width signal V
pWMwhile switching to conducting state by off state, the first control signal V
qscontrol source drive transistor Q
sswitch to conducting by shutoff, meanwhile, the second control signal V
qccontrol auxiliary switch Q
cin conducting state, now, main power transistor Q
mthe grid voltage input terminal voltage Vcc that equals to power, due to source drive transistor Q
sconducting, main power transistor Q
msource voltage be 0.Therefore, main power transistor Q
mgate source voltage equal Vcc, thereby make the power transistor Q of winner
mdriven conducting, now electric current flows through former limit winding L 1, and rises gradually, and transformer T carries out energy storage.
At pulse-width signal V
pWMindicate main power transistor Q
min keeping during conducting, for the supply power voltage Vcc continuous decrease of electrical input, if can not be compensated, supply power voltage Vcc may be too low, and then cause control circuit 22 electricity shortages and cisco unity malfunction.Thus, control circuit 22 is at pulse-width signal V
pWMindicate main power transistor Q
min keeping during conducting, control source drive transistor Q
swith auxiliary switch Q
cturn-off a period of time simultaneously.During this period, due to source drive transistor Q
sturn-off main power transistor Q
msource voltage by lifting gradually until the input terminal voltage Vcc that equals to power makes clamping diode D2 conducting, by main power transistor Q
msource voltage be clamped at Vcc.Due to auxiliary switch Q now
calso in off state, main power transistor Q
mgrid source electric capacity there is no discharge channel, main power transistor Q
mgrid and source electrode between voltage difference remain unchanged, make the power transistor Q of winner
mkeep conducting.The inductive current I of former limit winding
pby clamping diode D2 to power supply capacitor C
scharging, compensation supply power voltage Vcc.
Supply power voltage Vcc is being compensated and met after predetermined condition, source drive transistor Q
scontrolled and recovered conducting, made the power transistor Q of winner
msource voltage pulled down to 0, clamping diode D2 turn-off, the inductive current I of former limit winding
pby source drive transistor Q
sflow to earth point, stop power supply capacitor C
scharging.
At pulse-width signal V
pWMwhen indication is turn-offed, source drive transistor Q
sturn-off, and auxiliary switch Q now
cin conducting state.The power transistor Q of Zhe Huishi winner
mgate source voltage become fast 0, and then cause main power transistor Q
mturn-off.Therefore, in order to keep main power transistor Q
mmaintain conducting state, auxiliary switch Q
cturn-off time interval (also the second time interval) need to be greater than source drive transistor Q
sturn-off time interval (being also very first time interval) or at least with source drive transistor Q
sturn-off time interval (being also very first time interval) identical.
One of ordinary skill in the art will readily recognize that as long as the second time interval and very first time interval meet above-mentioned relation the no matter length in charging interval all can to a certain degree be alleviated the risk of control circuit electricity shortage.
Thus, the present embodiment arranges auxiliary switch by the grid at main power transistor and control circuit between electrical input, and control auxiliary switch and source drive transistor turn-offs between the winding current rising stage of former limit, make the electric current that flows through former limit winding pass through main power transistor to power supply capacitor charging, avoid the appearance of the too low situation of supply power voltage, guaranteed the normal work of control circuit.
Fig. 3 is the circuit diagram of the isolated converter of second embodiment of the invention.As shown in Figure 3, the power stage circuit 31 of the isolated converter 30 of the present embodiment is identical with the first embodiment, does not repeat them here.
Control circuit 32 comprises for electrical input cc, grid link g, source electrode link s, source drive transistor Q
s, auxiliary switch Q
c, clamping diode D2 and control signal generative circuit Ctrl3.
Main power transistor Q
mgrid be connected with the grid link g of control circuit 32, main power transistor Q
msource electrode be connected with the source electrode link of control circuit 32, power supply capacitor C
sbe connected to between electrical input cc and earth point gnd.
In a preferred implementation, isolated converter 30 can also comprise the starting resistance R that is used to control circuit 32 to start power supply
inand absorbing circuit.
In control circuit 32, be used for being connected to for electrical input cc the power supply capacitor C that control circuit 32 is powered
s; Grid link g is used for the main power transistor Q with isolated converter
mgrid connect; Source electrode link s is used for and main power transistor Q
msource electrode connect.
Source drive transistor Q
sbe connected between source electrode link s and earth point gnd.
Auxiliary switch Q
cbe connected to grid link g and supply between electrical input cc.
Clamping diode D2 is connected to between electrical input cc and source electrode link s.
In the present embodiment, control signal generative circuit Ctrl3 comprises pulse-width signal generative circuit Ctrl31 and control signal acquisition cuicuit Ctrl32.
Pulse-width signal generative circuit Ctrl31 is used for generating the main power transistor Q of indication
mthe pulse-width signal of the time interval of turn-on and turn-off.It can be realized based on the means that disclose in well known to those skilled in the art and other prior art, also, for example, determines the main power transistor Q of indication according to feedback parameters (, output voltage, primary current etc.)
mthe pulse-width signal V of the time interval of turn-on and turn-off
pWM.
Control signal acquisition cuicuit Ctrl32 is according to pulse-width signal V
pWMvcc generates described the first control signal V with power supply input terminal voltage
qswith the second control signal V
qc.
The first control signal V
qsafter conducting switching instant, postpone first time of delay d1 switch to off state, in the time that power supply input terminal voltage is greater than first threshold voltage, switch to conducting state.
The second control signal V
qcafter conducting switching instant, postpone second time of delay d2 switch to off state, in the time that power supply input terminal voltage is greater than first threshold voltage, switch to conducting state.
In the present embodiment, conducting switching instant is pulse-modulated signal V
pWMswitched to the moment of conducting state by off state.
In the present embodiment, the first control signal V
qsinterval T1 of the corresponding very first time and the second control signal V
qcthe second corresponding time interval T2 difference.Both can have different initial times and the identical finish time.
As shown in Figure 3, control signal acquisition cuicuit Ctrl32 comprises the first delay pulse circuit DP1, the second delay pulse circuit DP2, the first rest-set flip-flop RS1, the second rest-set flip-flop RS2, overvoltage comparator CMP1 and logical circuit OUT1.
The first delay pulse circuit DP1 input pulse-width signal V
pWM, its output is connected to the reset terminal of the first rest-set flip-flop RS1, for exporting the first reset pulse, with respect to conducting switching instant, the first reset pulse be delayed first time of delay d1.
The second delay pulse circuit DP2 input pulse-width signal V
pWM, its output is connected to the reset terminal of the second rest-set flip-flop RS2, for exporting the second reset pulse, with respect to conducting switching instant, the second reset pulse be delayed second time of delay d2.
Wherein, first time of delay d1 be greater than second time of delay d2.
Preferably, as shown in Figure 4, delay pulse circuit can adopt signal delay circuit DL and pulse generative circuit OS to be composed in series.Signal delay circuit DL postpones predetermined time output to its input signal, and pulse generative circuit OS triggers output single pulse signal according to the rising edge of its input signal.
The in-phase input end input power supply input terminal voltage Vcc of overvoltage comparator CMP1, inverting input input first threshold voltage V
th1, first threshold voltage V
th1define in main power transistor conduction period for power supply capacitor C
sthe upper voltage limit of charging.The output of overvoltage comparator CMP1 is connected with the set end of the first rest-set flip-flop RS1 and the second rest-set flip-flop RS2 simultaneously, rises to and is greater than first threshold voltage V at power supply input terminal voltage Vcc
th1time export set pulse.
In Fig. 3, logical circuit OUT1 is logical AND gate, and its input is inputted respectively output signal and the pulse-width signal V of the first rest-set flip-flop RS1
pWM, output the first control signal V
qs.Certainly, one of ordinary skill in the art will readily recognize that logical circuit OUT1 can revise according to different the making adaptively of the implication of each signal low and high level representative, as long as guarantee the first control signal V of output
qsat output signal and the pulse-width signal V of the first rest-set flip-flop RS1
pWMwhile being conducting state in conducting state, at output signal or the pulse-width signal V of the first rest-set flip-flop RS1
pWMduring for off state in off state.
The second rest-set flip-flop RS2 exports the second control signal V according to set pulse and the reset pulse of input
qc.
Fig. 5 is the signal waveform schematic diagram of the isolated converter of second embodiment of the invention.The operation principle of the isolated converter of the present embodiment is described below in conjunction with Fig. 5.In the present embodiment, take high level as conducting state, low level is that off state is that example describes.Certainly, one of ordinary skill in the art will readily recognize that the consideration for other side, also can low level be set to conducting state, high level is set to off state.Can also different indication level be set for different switches or transistor, for example, for pulse-width signal V
pWM, high level is indicated conducting and low level indication shutoff, simultaneously for the first control signal V
qs, high level is indicated conducting and low level indication shutoff.For be adapted to change that the variation of level definition makes circuit be only those skilled in the art can make be equal to replacement.
As shown in Figure 5, in the t0 moment, also at pulse-width signal V
pWMwhile switching to conducting state by off state, pulse-width signal is V
pWMhigh level, now, the first rest-set flip-flop RS1 and the second rest-set flip-flop RS2, all in SM set mode, all export high level, therefore, the first control signal V
qswith the second control signal V
qcbe high level.Now, main power transistor Q
mgrid voltage equal supply power voltage Vcc, due to source drive transistor Q
sconducting, main power transistor Q
msource voltage be 0.Therefore, main power transistor Q
mgate source voltage equal Vcc, thereby make the power transistor Q of winner
mdriven conducting, now electric current flows through former limit winding L 1, and rises gradually, and transformer T carries out energy storage.
In the t1 moment, it (is also pulse-width signal V apart from the t0 moment
pWMrising edge) time be second time of delay d2, the second delay pulse circuit DP2 exports reset pulse at this moment, makes the second control signal V of the second rest-set flip-flop RS2 output
qcswitch to low level by high level.Due to first time of delay d1 be greater than second time of delay d2, therefore, in the t1 moment, the first control signal V
qsstill be high level.
In the t0 moment to the t2 moment, power supply input terminal voltage Vcc continuous decrease.
In the t2 moment, it (is also pulse-width signal V apart from the t0 moment
pWMrising edge) time be first time of delay d1, the first delay pulse circuit DP1 exports reset pulse at this moment, makes the output signal of the first rest-set flip-flop RS1 switch to low level by high level.Therefore, the first control signal V of logical circuit OUT1 output
qsswitch to low level by high level.
In the t2 moment to the t3 moment, the first control signal V
qswith the second control signal V
qcall remain low level, make source drive transistor Q
swith auxiliary switch Q
ckeep turn-offing.Due to source drive transistor Q
sturn-off main power transistor Q
msource voltage by lifting gradually until the input terminal voltage Vcc that equals to power makes clamping diode D2 conducting, by main power transistor Q
msource voltage be clamped at Vcc.Due to auxiliary switch Q now
calso in off state, main power transistor Q
mgrid source electric capacity there is no discharge channel, main power transistor Q
mgrid and source electrode between voltage difference remain unchanged, make the power transistor Q of winner
mkeep conducting.During this period, the inductive current I of former limit winding
pby clamping diode D2 to power supply capacitor C
scharging, compensation supply power voltage Vcc.During this period, power supply input terminal voltage Vcc continues to rise.
In the t3 moment, power supply input terminal voltage Vcc rises to predetermined first threshold voltage V
th1, now, overvoltage comparator CMP1 exports high level, and the first rest-set flip-flop RS1 and the second rest-set flip-flop RS2 are set, and all exports high level.Therefore, the second control signal V
qcfor high level.Meanwhile, due in the t3 moment, pulse-width signal V
pWMfor high level, therefore, the first control signal V
qsalso be high level.Therefore, in this moment, source drive transistor Q
swith auxiliary switch Q
cswitch to conducting by shutoff simultaneously.Make the power transistor Q of winner
msource voltage pulled down to 0, clamping diode D2 turn-off, the inductive current I of former limit winding
pby source drive transistor Q
sflow to earth point, stop power supply capacitor C
scharging.Owing to stopping power supply capacitor C
scharging, power supply input terminal voltage Vcc is from first threshold voltage V
th1start continuous decrease, make overvoltage comparator CMP1 output low level.
In the t3 moment, to the t4 moment, power supply input terminal voltage Vcc is from first threshold voltage V
th1start continuous decrease.The inductive current I of former limit winding
pstill linear increasing.
In the t4 moment, pulse-width signal V
pWMswitch to low level by high level, make the first control signal V of logical circuit OUT1 output
qsbecome low level.Thus, source drive transistor Q
sturn-off.Now the second control signal V
qcstill keep high level, make auxiliary switch Q
ckeep conducting.Due to source drive transistor Q
sturn-off main power transistor Q
msource voltage be elevated, make clamping diode D2 conducting, thereby make the power transistor Q of winner
mgate source voltage decline, and then make the power transistor Q of winner
mturn-off.
In the t4 moment to the t5 moment, due to main power transistor Q
mturn-off the inductive current I of former limit winding
plinearity reduces, the inductive current I of secondary winding
slinear increase, the leakage inductance of former limit winding and main power transistor Q
mparasitic capacitance resonance, thereby in the time approaching t5 moment, main power transistor Q
mdrain voltage V
dwith source voltage V
swaveform vibrate.
Preferably, in the time that isolated converter 30 comprises absorbing circuit, at main power transistor Q
mafter being turned off, its drain voltage V
dbe lifted very soon, and be absorbed circuit clamping.Absorbing circuit comprises absorption resistance R, Absorption Capacitance C and absorbing circuit clamping diode D3.Work as V
dwhile rising fast, absorbing circuit clamping diode D3 conducting, the inductive current I of former limit winding
pto Absorption Capacitance C charging, then the voltage at Absorption Capacitance C two ends is absorbed resistance R consumption, to prevent main power transistor Q
mdrain-source voltage when shutoff is too high and breakdown.
In the t5 moment, former limit winding L 1 and 2 changes of current of secondary winding L complete.The inductive current I of secondary winding
sreach maximum.After the t5 moment, the inductive current I of secondary winding
slinearity reduces, and is the load energy supply of isolated converter output terminal.
Thus, the present embodiment by main power transistor conduction period to power supply capacitor charging, can avoid the appearance of the too low situation of supply power voltage, guaranteed the normal work of control circuit.In the control signal generative circuit of the present embodiment, auxiliary switch turn-offs before source drive transistor turn-offs, and can guarantee that the transistorized shutoff of source drive can not cause main power transistor mistake to be turn-offed, and has good reliability.Meanwhile, the present embodiment adopts overvoltage comparator output signal, controls source drive transistor and auxiliary switch conducting simultaneously, and component number is less, can reduce circuit scale.
Fig. 6 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of third embodiment of the invention.The other parts of the isolated converter of the present embodiment and the second embodiment are similar, do not repeat them here.The control signal generative circuit Ctrl6 of the present embodiment comprises pulse-width signal generative circuit Ctrl61 and control signal acquisition cuicuit Ctrl62.
Pulse-width signal generative circuit Ctrl61 is used for generating the main power transistor Q of indication
mthe pulse-width signal V of the time interval of turn-on and turn-off
pWM.
Control signal acquisition cuicuit Ctrl62 is according to pulse-width signal V
pWMvcc generates the first control signal V with power supply input terminal voltage
qswith the second control signal V
qc.
Different from the second embodiment, in the present embodiment, the first control signal V
qsinterval T1 of the corresponding very first time and the second control signal V
qcthe second corresponding time interval T2 is identical.Both have identical initial time and the identical finish time.
As shown in Figure 6, control signal acquisition cuicuit Ctrl62 comprises delay pulse circuit DP3, rest-set flip-flop RS3, overvoltage comparator CMP2 and logical circuit OUT2.
Delay pulse circuit DP3 input pulse-width signal V
pWM, its output is connected to the reset terminal of rest-set flip-flop RS3, for exporting reset pulse, with respect to conducting switching instant, reset pulse be delayed first time of delay d1.In the present embodiment, first time of delay d1 can arrange identically with the second embodiment.Conducting switching instant is pulse-modulated signal V
pWMswitched to the moment of conducting state by off state.
Overvoltage comparator CMP2 is connected to the set end of rest-set flip-flop RS3, and at power supply input terminal voltage, Vcc is greater than first threshold voltage V
th1time export set pulse.
Rest-set flip-flop RS3 exports the second control signal V
qc.
Logical circuit OUT2 is according to the output signal of rest-set flip-flop and pulse-width signal V
pWMexport the first control signal V
qs, make the first control signal V
qsat the output signal V of rest-set flip-flop RS3
qcwith pulse-width signal V
pWMwhile being conducting state in conducting state, at output signal or the pulse-width signal V of rest-set flip-flop
pWMduring for off state in off state.
In Fig. 6, logical circuit OUT2 is logical AND gate, and its input is inputted respectively output signal and the pulse-width signal V of rest-set flip-flop RS3
pWM, output the first control signal V
qs.Certainly, one of ordinary skill in the art will readily recognize that logical circuit OUT2 can make adaptability revision according to the implication difference of each signal low and high level representative.
The signal waveform difference of the signal waveform of the present embodiment and the second embodiment is in the present embodiment, at pulse-width signal V
pWMindicate main power transistor Q
mconduction period, the first control signal V
qswith the second control signal V
qccontrol source drive transistor Q
swith auxiliary switch Q
cturn-off simultaneously, and rise to first threshold voltage V at power supply input terminal voltage Vcc
th1rear while conducting.
By above setting, the control signal generative circuit number of elements of the present embodiment is less, can further reduce circuit scale.
Fig. 7 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of fourth embodiment of the invention.The other parts of the isolated converter of the present embodiment and the second embodiment are similar, do not repeat them here.The control signal generative circuit Ctrl7 of the present embodiment comprises pulse-width signal generative circuit Ctrl71 and control signal acquisition cuicuit Ctrl72.
Pulse-width signal generative circuit Ctrl71 is used for generating the main power transistor Q of indication
mthe pulse-width signal V of the time interval of turn-on and turn-off
pWM.
Control signal acquisition cuicuit Ctrl72 is according to pulse-width signal V
pWMvcc generates the first control signal V with power supply input terminal voltage
qswith the second control signal V
qc.
In the present embodiment, the first control signal V
qsinterval T1 of the corresponding very first time and the second control signal V
qcthe second corresponding time interval T2 difference.Both can have different initial times and the identical finish time.
Different from the second embodiment, the control signal acquisition cuicuit Ctrl72 of the present embodiment has different circuit structures.As shown in Figure 7, control signal acquisition cuicuit Ctrl72 comprises the first under-voltage comparator CMP3, the second under-voltage comparator CMP4, pulse generative circuit OS1, the first logical circuit LG1, the second logical circuit LG2, overvoltage comparator CMP5, the first rest-set flip-flop RS4, the second rest-set flip-flop RS5 and the 3rd logical circuit OUT3.
The first under-voltage comparator CMP3 input power supply input terminal voltage Vcc and Second Threshold voltage V
th2, at power supply input terminal voltage, Vcc is less than Second Threshold voltage V
th2time export the first under-voltage pulse.
The second under-voltage comparator CMP4 input power supply input terminal voltage Vcc and the 3rd threshold voltage V
th3, at power supply input terminal voltage, Vcc is less than the 3rd threshold voltage V
th3time export the second under-voltage signal.Second Threshold voltage V
th2be less than the 3rd threshold voltage V
th3.
Pulse generative circuit OS1 inputs the second under-voltage signal and exports the second under-voltage pulse.
The first logical circuit LG1 inputs the first under-voltage pulse and pulse-width signal V
pWM, and be connected to the reset terminal of the first rest-set flip-flop RS4, at pulse-width signal V
pWMwhile exporting the first under-voltage pulse for conducting state and the first under-voltage comparator, output the first reset pulse.
The second logical circuit LG2 inputs the second under-voltage pulse and pulse-width signal V
pWM, and be connected to the reset terminal of the second rest-set flip-flop RS5, at pulse-width signal V
pWMwhile exporting the second under-voltage signal for conducting state and the second under-voltage comparator, output the second reset pulse.
Overvoltage comparator CMP5 is connected to the set end of the first rest-set flip-flop RS4 and the second rest-set flip-flop RS5, and at power supply input terminal voltage, Vcc is greater than first threshold voltage V
th1time export set pulse.
The 3rd logical circuit OUT3 is according to the output signal of the first rest-set flip-flop RS4 and pulse-width signal V
pWMexport the first control signal V
qs, the first control signal V
qsat output signal and the pulse-width signal V of the first rest-set flip-flop RS4
pWMwhile being conducting state in conducting state, at output signal or the pulse-width signal V of the first rest-set flip-flop RS4
pWMduring for off state in off state.
The second rest-set flip-flop RS5 is used for exporting the second control signal V
qc.
In Fig. 7, the first logical circuit LG1, the second logical circuit LG2 and the 3rd logical circuit OUT3 are logical AND gate.
Certainly, one of ordinary skill in the art will readily recognize that above-mentioned each logical circuit can make adaptively and to revise according to the implication difference of each signal low and high level representative, as long as guarantee to realize the logic function of its required realization.
Fig. 8 is the signal waveform schematic diagram of the isolated converter of fourth embodiment of the invention.The operation principle of the isolated converter of the present embodiment is described below in conjunction with Fig. 8.In the present embodiment, using high level as indication conducting, low level indication is turn-offed and is described for example.Certainly, one of ordinary skill in the art will readily recognize that the consideration for other side, also can low level be set to conducting state, high level is set to off state.
In the t0 moment to the t2 ' moment, due to source drive transistor Q
sconducting, main power transistor Q
msource voltage be 0.Clamping diode D2 is in off state, power supply input terminal voltage Vcc continuous decrease.
At source drive transistor Q
swhen shutoff, if auxiliary switch Q
cin conducting state, the power transistor Q of Hui Shi winner
mgate source voltage become fast 0, and then cause main power transistor Q
mturn-off.Therefore, in order to keep main power transistor Q
mmaintain conducting state, auxiliary switch Q
cturn-off time interval (also the second time interval) need to be greater than source drive transistor Q
sturn-off time interval (being also very first time interval) or at least with source drive transistor Q
sturn-off time interval identical.Accordingly, need to make the 3rd threshold voltage V
th3be greater than Second Threshold voltage V
th2.
In the t1 ' moment, power supply input terminal voltage Vcc drops to the 3rd threshold voltage V
th3, the second under-voltage comparator CMP4 output high level.Due to pulse-width signal V now
pWMfor high level, therefore the second logical circuit LG2 output high level, resets the second rest-set flip-flop RS5.Thus, the second control signal V of the second rest-set flip-flop RS5 output
qcfor low level, auxiliary switch Q
cturn-off.
In the t1 ' moment, to the t2 ' moment, power supply input terminal voltage Vcc continues to decline.
In the t2 ' moment, power supply input terminal voltage Vcc drops to Second Threshold voltage V
th2, the first under-voltage comparator CMP3 output high level.Due to pulse-width signal V now
pWMfor high level, therefore the first logical circuit LG1 output high level, resets the first rest-set flip-flop RS4.Thus, the first rest-set flip-flop RS4 output low level, and then make the first control signal V
qsfor low level, source drive transistor Q
sturn-off.Now, main power transistor Q
msource voltage by lifting gradually until equal the supply power voltage Vcc for electrical input, make clamping diode D2 conducting, by main power transistor Q
msource voltage be clamped at Vcc.The inductive current I of former limit winding
pstart power supply capacitor C
scharging.
Hence one can see that, Second Threshold voltage V
th2in fact limited the lower limit of input terminal voltage Vcc in main power transistor conduction period of powering.
In the t2 ' moment, to the t3 moment, power supply input terminal voltage Vcc continues to rise.
In the t3 moment, power supply input terminal voltage Vcc rises to predetermined first threshold voltage V
th1.Similar with the second embodiment, overvoltage comparator CMP5 exports set pulse, finally makes the first control signal V
qswith the second control signal V
qcbe high level, now charging process finishes.
Thus, the present embodiment by main power transistor conduction period to power supply capacitor charging, can avoid the appearance of the too low situation of supply power voltage, guaranteed the normal work of control circuit.The control signal generative circuit of the present embodiment is controlled the zero hour to power supply capacitor charging based on threshold voltage, thereby accurately controls charging process.
Fig. 9 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of fifth embodiment of the invention.The other parts of the isolated converter of the present embodiment and the 4th embodiment are similar, do not repeat them here.The control signal generative circuit Ctrl9 of the present embodiment comprises pulse-width signal generative circuit Ctrl91 and control signal acquisition cuicuit Ctrl92.
Pulse-width signal generative circuit Ctrl91 is used for generating the main power transistor Q of indication
mthe pulse-width signal V of the time interval of turn-on and turn-off
pWM.
Control signal acquisition cuicuit Ctrl92 is according to pulse-width signal V
pWMvcc generates the first control signal V with power supply input terminal voltage
qswith the second control signal V
qc.
Different from the 4th embodiment, in the present embodiment, the first control signal V
qsinterval T1 of the corresponding very first time and the second control signal V
qcthe second corresponding time interval T2 is identical.Both have identical initial time and the identical finish time.
As shown in Figure 9, control signal acquisition cuicuit Ctrl92 comprises under-voltage comparator CMP6, the first logical circuit LG3, overvoltage comparator CMP7, rest-set flip-flop RS6, the second logical circuit OUT4.
Under-voltage comparator CMP6 is less than Second Threshold voltage V at power supply input terminal voltage Vcc
th2time, export under-voltage pulse.
The first logical circuit LG3 input undervoltage pulse and pulse-width signal V
pWM, at pulse-width signal V
pWMindicate main power transistor Q
mwhen conducting and under-voltage comparator CMP6 export under-voltage pulse, to the reset terminal output reset pulse of rest-set flip-flop RS6.
Overvoltage comparator CMP7 is connected to the set end of rest-set flip-flop RS6, and at power supply input terminal voltage, Vcc is greater than first threshold voltage V
th1time, output set pulse.
Rest-set flip-flop RS6 exports the second control signal V
qc.
Output signal and the pulse-width signal V of the second logical circuit OUT4 input rest-set flip-flop RS6
pWM, and export the first control signal V
qs, make the first control signal V
qsat output signal and the pulse-width signal V of rest-set flip-flop RS6
pWMwhile being conducting in conducting state, at output signal or the pulse-width signal V of rest-set flip-flop
pWMfor turn-off time in off state.
Similar with the 4th embodiment, the first logical circuit LG3 and the second logical circuit OUT4 are logical AND gate.Certainly, one of ordinary skill in the art will readily recognize that above-mentioned each logical circuit can make adaptively and to revise according to the implication difference of each signal low and high level representative, as long as guarantee to realize the logic function of its required realization.
The signal waveform difference of the signal waveform of the present embodiment and the second embodiment is, at pulse-width signal V
pWMindicate main power transistor Q
mconduction period, the first control signal V
qswith the second control signal V
qccontrol source drive transistor Q
swith auxiliary switch Q
cturn-off simultaneously, and rise to first threshold voltage V at power supply input terminal voltage Vcc
th1rear while conducting.
By above setting, the control signal generative circuit of the present embodiment is in accurately controlling charging process, and number of elements is less, can further reduce circuit scale.
The above second to the 5th embodiment all makes the first control signal and corresponding very first time interval and the second time interval of the second control signal have the identical finish time.But, it will be understood by those skilled in the art that it is only for the consideration of simplifying control signal generative circuit structure, but not realize the unique selection of the object of the invention.For the consideration of other side, also can make very first time interval and the second time interval there is the different finish times by for example increasing delay circuit.
Figure 10 is the schematic diagram of the control signal generative circuit that adopts of the isolated converter of sixth embodiment of the invention.The other parts of the isolated converter of the present embodiment and the second embodiment are similar, do not repeat them here.The control signal generative circuit Ctrl10 of the present embodiment comprises pulse-width signal generative circuit Ctrl101 and control signal acquisition cuicuit Ctrl102.
Pulse-width signal generative circuit Ctrl101 is used for generating the main power transistor Q of indication
mthe pulse-width signal V of the time interval of turn-on and turn-off
pWM, to realize accurate constant current control.
Control signal acquisition cuicuit Ctrl102 is according to pulse-width signal V
pWMvcc generates described the first control signal V with power supply input terminal voltage
qswith the second control signal V
qc.
In the present embodiment, pulse-width signal generative circuit Ctrl101 comprises former limit peak current sampling hold circuit PEAK, controlled integrating circuit INTE, integral control circuit INTEC and pulse-width modulation acquisition cuicuit PWM.
Former limit peak current sampling hold circuit PEAK is connected to controlled integrating circuit INTE, exports former limit peak current sampled signal to controlled integrating circuit INTE, and this signal is the voltage signal that characterizes former limit peak current.
According to the control of integral control circuit INTEC, controlled integrating circuit INTE output voltage compensation signal V
c, described voltage compensation signal V
caccording to described former limit peak current sampled signal and reference voltage V
refdifference integration and obtain.
Pulse-width modulation acquisition cuicuit PWM is used for according to described voltage compensation signal V
coutput pulse width modulation signal.Pulse-width modulation acquisition cuicuit PWM can use existing all kinds of circuit structure to realize.
Wherein, integral control circuit INTEC is in former limit winding inductance electric current I
p(t5 moment in Fig. 5) controlled controlled integrating circuit INTE and starts to carry out integration to be decreased at 1 o'clock by peak value linearity, in secondary winding inductance electric current I
s(t6 moment in Fig. 5) controlled controlled integrating circuit INTE and stops integration being decreased at 1 o'clock by peak value linearity.
Preferably, this enforcement, using the following moment as the moment that starts integration, also, meets power supply input terminal voltage Vcc and main power transistor source voltage V
sdifference be less than the 4th voltage threshold V
th4, pulse-width signal V simultaneously
pWMfor the moment of off state.
More preferably, integral control circuit INTEC comprises zero passage comparison circuit A1, pulse generative circuit OS2, zero passage logical circuit LG4, integral control rest-set flip-flop RS7 and secondary inductance current over-zero testing circuit PZ.
Zero passage comparison circuit A1 specifically comprises comparator C MP8 and threshold voltage source, and the voltage of threshold voltage source is the 4th voltage threshold V
th4.The high-pressure side of threshold voltage source is connected to the in-phase input end of comparator C MP8, and low-pressure end is connected to source electrode link.The reverse input end input power supply input terminal voltage Vcc of comparator C MP8.The output of comparator C MP8 is as the output of zero passage comparison circuit A1, and it is connected to pulse generative circuit OS2.Zero passage comparison circuit A1 is at power supply input terminal voltage Vcc and main power transistor source voltage V
sdifference be less than the 4th voltage threshold V
th4time export zero cross signal.
Pulse generative circuit OS2 inputs zero cross signal, and to zero passage logical circuit LG4 output zero-crossing pulse signal.
Zero passage logical circuit LG4 inputs described zero-crossing pulse signal and described pulse-width signal V
pWM, and export set pulse to the set end of integral control rest-set flip-flop RS7.
Secondary inductance current over-zero testing circuit PZ is in the time of secondary winding inductance electric current positive going zeror crossing, to the reset terminal output reset pulse of integral control rest-set flip-flop RS7.
Integral control rest-set flip-flop RS7 exports integral control signal.
Meanwhile, controlled integrating circuit INTE can comprise the first switch S 1, second switch S2, filter circuit RC and integrating circuit INT.
The first switch S 1 is connected between the output and the input of filter circuit RC of former limit peak current sampling hold circuit PEAK.Second switch S2 is connected between the input and earth point of filter circuit RC.First switch S 1 conducting in the time that integral control signal is high level is turn-offed in the time that integral control signal is low level.Second switch S2 turn-offs when integral control signal is high level, conducting in the time that integral control signal is low level.
Filter circuit RC comprises filter resistance R
fwith filter capacitor C
f.Integrating circuit INT comprises trsanscondutance amplifier GM and is connected to the building-out capacitor C between mutual conductance amplification output and earth point
c.The inverting input of trsanscondutance amplifier GM is connected with the output of filter circuit RC, its in-phase input end input reference voltage V
ref.
One of ordinary skill in the art will readily recognize that controlled integrating circuit INTE can also use disclosed circuit structure in other well known to those skilled in the art or prior art to realize.
Known according to the circuit topology of anti exciting converter, output current meets following formula, that is:
Wherein, I
ofor output current, t
sbe the switch periods of main power transistor, N
pfor former limit umber of turn, N
sfor secondary umber of turn, t
disfor the discharge time (or being called the degaussing time) of secondary winding, I
pk1for the inductive current peak of former limit winding.
In order to obtain constant output current I
o, at the switch periods t of main power transistor
sone regularly, can make by control circuit the inductive current peak I of former limit winding
pk1t discharge time with secondary winding
disproduct constant.Also, utilize the inductive current peak I of former limit winding
pk1t discharge time with secondary winding
disproduct generate pulse-width signal V as controlling parameter
pWM.
In the prior art, conventionally use the turn-off time t of main power transistor
dis' be used as discharge time of secondary winding.But, as shown in Figure 5, the turn-off time t of main power transistor
dis' comprise the time (the t4 moment in Fig. 5 is to the t5 moment) of the former secondary winding change of current and the discharge time (the t5 moment in Fig. 5 is to the t7 moment) of secondary winding.Hence one can see that, t
dis' be not the actual discharge time of secondary winding, thereby the control mode inaccuracy of prior art, can form harmful effect to the accuracy of isolated converter constant current control.
The present embodiment is by accurately controlling the time interval of integration, also, and based on accurate discharge time of t
discontrol, to improve the constant-current control accuracy of isolated converter.
Known with reference to figure 5, in the t4 moment, to the t5 moment, former limit winding L 1 and secondary winding L 2 are carried out the change of current, the inductive current I of former limit winding
plinearity reduces, the inductive current I of secondary winding
slinear increase.The leakage inductance of former limit winding and main power transistor Q
mparasitic capacitance resonance, thereby in the time approaching t5 moment, main power transistor Q
msource voltage V
swaveform vibrate.Due to the existence of clamping diode D2, source voltage V
swaveform shielded by clamping diode D2.Meanwhile, because the fall of feeder ear voltage vcc is with respect to V
soscillating waveform amplitude is negligible, therefore, can by feeder ear voltage vcc as a comparison standard judge source voltage V
soscillation amplitude.Make feeder ear voltage vcc and source voltage V in this oscillation amplitude
sdifference is less than predefined the 4th voltage threshold V
th4time, can think and detect that the former secondary change of current completes, and using this moment as t discharge time
disinitial time.
In the t6 moment, the inductive current I of secondary winding
sbe reduced at 1 o'clock by peak value, the source voltage V of main power transistor
sreduce, now, think the inductive current zero crossing of secondary winding, thereby obtain the finish time of discharge time suddenly.
The present embodiment, by accurately controlling the time interval of integration, has improved the constant-current control accuracy of isolated converter.
The pulse-width signal generative circuit that it will be understood by those skilled in the art that the present embodiment can be applied to the above-mentioned first to the 5th embodiment, to improve the constant-current control accuracy of isolated converter.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various changes and variation.All any modifications of doing, be equal to replacement, improvement etc., within protection scope of the present invention all should be included within spirit of the present invention and principle.
Claims (10)
1. a control circuit, for isolated converter, described control circuit comprises for electrical input, grid link, source electrode link, source drive transistor, auxiliary switch, clamping diode and control signal generative circuit;
Described power supply electric capacity of powering for being connected to described control circuit for electrical input; Described grid link is for being connected with the grid of the main power transistor of described isolated converter; Described source electrode link is for being connected with the source electrode of described main power transistor;
Described source drive transistor is connected between described source electrode link and earth point;
Described auxiliary switch is connected to described grid link and described between electrical input;
Described clamping diode is connected to described between electrical input and described source electrode link;
Described control signal generative circuit is used for generating the first control signal and the second control signal; Described in described the first control signal control, source drive transistor is interval shutoff of the very first time, described in described the second control signal control, auxiliary switch turn-offs at the second time interval, and interval and described the second time interval of described very first time is positioned at pulse-width signal indicates the time interval of main power transistor conducting; It is interval or identical with described very first time interval that described the second time interval is greater than the described very first time.
2. control circuit according to claim 1, is characterized in that, described control signal generative circuit comprises pulse-width signal generative circuit and control signal acquisition cuicuit;
Described pulse-width signal generative circuit is used for generating described pulse-width signal, and described pulse-width signal is used to indicate shutoff and the conducting of described main power transistor;
Described control signal acquisition cuicuit is for generating described the first control signal and the second control signal according to described pulse-width signal and described power supply input terminal voltage.
3. control circuit according to claim 2, is characterized in that, described control signal acquisition cuicuit comprises the first delay pulse circuit, the second delay pulse circuit, the first rest-set flip-flop, the second rest-set flip-flop, overvoltage comparator and logical circuit;
Described the first delay pulse circuit is for exporting the first reset pulse to the reset terminal of described the first rest-set flip-flop, and with respect to conducting switching instant, described the first reset pulse was delayed for the first time of delay;
Described the second delay pulse circuit is for exporting the second reset pulse to the reset terminal of described the second rest-set flip-flop, and with respect to described conducting switching instant, described the second reset pulse was delayed for the second time of delay;
Described conducting switching instant is described pulse-modulated signal is switched to conducting state moment by off state; Be greater than described the second time of delay described the first time of delay;
Described overvoltage comparator is connected to the set end of described the first rest-set flip-flop and the second rest-set flip-flop, exports set pulse in the time that described power supply input terminal voltage is greater than first threshold voltage;
Described logical circuit is exported described the first control signal, and in the time that the output signal of described the first rest-set flip-flop and described pulse-width signal are conducting state, described the first control signal is in conducting state; In the time that the output signal of described the first rest-set flip-flop or described pulse-width signal are off state, described the first control signal is in off state;
Described the second rest-set flip-flop is exported described the second control signal.
4. control circuit according to claim 2, is characterized in that, described control signal acquisition cuicuit comprises delay pulse circuit, rest-set flip-flop, overvoltage comparator and logical circuit;
Described delay pulse circuit is for the reset terminal output reset pulse to described rest-set flip-flop, and described reset pulse postponed for the first time of delay with respect to conducting switching instant;
Described conducting switching instant is described pulse-modulated signal is switched to conducting state moment by off state;
Described overvoltage comparator is connected to the set end of described rest-set flip-flop, exports set pulse in the time that described power supply input terminal voltage is greater than first threshold voltage;
Described rest-set flip-flop is exported described the second control signal;
Described logical circuit is exported described the first control signal, and in the time that the output signal of described rest-set flip-flop and described pulse-width signal are conducting state, described the first control signal is in conducting state; In the time that the output signal of described rest-set flip-flop or described pulse-width signal are off state, described the first control signal is in off state.
5. control circuit according to claim 2, it is characterized in that, described control signal acquisition cuicuit comprises the first under-voltage comparator, the second under-voltage comparator, pulse generative circuit, the first logical circuit, the second logical circuit, overvoltage comparator, the first rest-set flip-flop, the second rest-set flip-flop and the 3rd logical circuit;
Described the first under-voltage comparator is exported the first under-voltage pulse in the time that described power supply input terminal voltage is less than Second Threshold voltage;
Described the second under-voltage comparator is exported the second under-voltage signal in the time that described power supply input terminal voltage is less than the 3rd threshold voltage; Described Second Threshold voltage is less than described the 3rd threshold voltage;
Described pulse generative circuit is exported the second under-voltage pulse according to described the second under-voltage signal;
Described the first logical circuit is connected to the reset terminal of the first rest-set flip-flop, in the time receiving described the first under-voltage pulse and described pulse-width signal and be conducting state, and output the first reset pulse;
Described the second logical circuit is connected to the reset terminal of the second rest-set flip-flop, in the time receiving described the second under-voltage pulse and described pulse-width signal and be conducting state, and output the second reset pulse;
Described overvoltage comparator is connected to the set end of described the first rest-set flip-flop and the second rest-set flip-flop, exports set pulse in the time that described power supply input terminal voltage is greater than first threshold voltage;
Described the 3rd logical circuit is exported described the first control signal, and in the time that the output signal of described the first rest-set flip-flop and described pulse-width signal are conducting state, described the first control signal is in conducting state; In the time that the output signal of described the first rest-set flip-flop or described pulse-width signal are off state, described the first control signal is in off state;
Described the second rest-set flip-flop is exported described the second control signal.
6. control circuit according to claim 2, is characterized in that, described control signal acquisition cuicuit comprises under-voltage comparator, the first logical circuit, overvoltage comparator, rest-set flip-flop, the second logical circuit;
Described under-voltage comparator is exported under-voltage pulse in the time that described power supply input terminal voltage is less than Second Threshold voltage;
Described the first logical circuit is connected to the reset terminal of described rest-set flip-flop, in the time receiving described under-voltage pulse and described pulse-width signal and be conducting state, and output reset pulse;
Described overvoltage comparator is connected to the set end of described rest-set flip-flop, in the time that described power supply input terminal voltage is greater than first threshold voltage, and output set pulse;
Described rest-set flip-flop is exported described the second control signal;
Described the second logical circuit is exported described the first control signal, and in the time that the output signal of described rest-set flip-flop and pulse-width signal are conducting state, described the first control signal is in conducting state; In the time that the output signal of described rest-set flip-flop or pulse-width signal are off state, described the first control signal is in off state.
7. control circuit according to claim 2, is characterized in that, described pulse-width signal generative circuit comprises former limit peak current sampling hold circuit, controlled integrating circuit, integral control circuit and pulse-width modulation acquisition cuicuit;
Described former limit peak current sampling hold circuit is connected to described controlled integrating circuit, exports former limit peak current sampled signal;
According to the control of described integral control circuit, described controlled integrating circuit output voltage compensation signal, described voltage compensation signal obtains according to the difference integration of described former limit peak current sampled signal and reference voltage;
Described pulse-width modulation acquisition cuicuit is exported described pulse-width signal according to described voltage compensation signal;
Wherein, described integral control circuit is decreased at 1 o'clock and is controlled described controlled integrating circuit by peak value linearity at former limit winding inductance electric current and starts to carry out integration, is decreased at 1 o'clock and is controlled described controlled integrating circuit to stop integration at secondary winding inductance electric current by peak value linearity.
8. control circuit according to claim 7, it is characterized in that, it is that the difference of described power supply input terminal voltage and main power transistor source voltage is less than the moment that the 4th voltage threshold and described pulse-width signal are off state that former limit winding inductance electric current is decreased to moment of zero by peak value linearity.
9. control circuit according to claim 8, is characterized in that, described integral control circuit comprises zero passage comparison circuit, zero passage pulse generative circuit, zero passage logical circuit, integral control rest-set flip-flop and secondary inductance current over-zero testing circuit;
Described zero passage comparison circuit is connected to described zero passage pulse generative circuit, exports zero cross signal in the time that the difference of described power supply input terminal voltage and described main power transistor source voltage is less than described the 4th voltage threshold;
Described zero passage pulse generative circuit receives described zero cross signal and exports zero-crossing pulse signal to described zero passage logical circuit;
Described zero passage logical circuit is connected with the set end of described integral control rest-set flip-flop, according to described zero-crossing pulse signal and described pulse-width signal output set pulse;
Described secondary inductance current over-zero testing circuit is decreased at secondary winding inductance electric current at 1 o'clock by peak value linearity, to the reset terminal output reset pulse of described integral control rest-set flip-flop;
Described integral control rest-set flip-flop output integral control signal.
10. an isolated converter, comprises power stage circuit, power supply electric capacity and the control circuit as described in claim 1-9 any one with main power transistor;
The grid of described main power transistor is connected with the grid link of described control circuit, and the source electrode of described main power transistor is connected with the source electrode link of described control circuit, and described power supply electric capacity is connected to described between electrical input and earth point.
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