CN206442302U - A kind of synchronous rectification control chip - Google Patents
A kind of synchronous rectification control chip Download PDFInfo
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- CN206442302U CN206442302U CN201621157303.5U CN201621157303U CN206442302U CN 206442302 U CN206442302 U CN 206442302U CN 201621157303 U CN201621157303 U CN 201621157303U CN 206442302 U CN206442302 U CN 206442302U
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Abstract
The utility model discloses a kind of synchronous rectification control chip, including：Turn on initializing circuit, voltage detecting circuit, pattern decision circuit, fault secure circuit, advanced breaking circuit, ON time initialization circuit, selection circuit, control circuit, triggers circuit and drive circuit；The conducting initializing circuit, voltage detecting circuit, pattern decision circuit connection Input voltage terminal；The conducting initializing circuit connects the voltage detecting circuit.The utility model is solved in the prior art can not be while can realize the problem accurately turned off under DCM/CCM both of which；Peripheral applications circuit can be simplified simultaneously, reduce application device.
Description
Technical field
The utility model is related to synchronous rectification field, more particularly to a kind of synchronous rectification control chip.
Background technology
Synchronous rectification be the special power MOSFET for using on state resistance extremely low to replace commutation diode to reduce rectification
One technology of loss.Since primary side switch pipe cut-off time, the conducting of secondary-side switch pipe, secondary inductance starts electric discharge, in pair
At the end of side inductive discharge closes on, secondary-side switch pipe will be turned off, and particularly after the completion of secondary inductance electric discharge, secondary-side switch pipe must
It must turn off, otherwise secondary output capacitance can be caused inversely to discharge, there is aircraft bombing risk.
Solving the method for secondary-side switch pipe shut-off at present has following several：
1. utilize voltagesecond product conservation：First the voltage at sampling primary side switch pipe turn-on instant secondary inductance two ends is with holding time
Product (secondary inductance both end voltage be converted into current signal and and time integral, become the voltage on secondary electric capacity), then
Re-sampling output voltage and it is converted into electric current when primary side switch pipe ends flyback electric capacity C2 is charged, compares two voltages and come real
The time point of existing secondary-side switch pipe shut-off.The advantage of the method greatly can also even if the change of primary side ON time under discontinuous mode
Accurately determine when to turn off secondary-side switch pipe；It has the disadvantage easily to be disturbed by input voltage fluctuation, and needs detection primary side electricity
Feel both end voltage.
2nd, the directly anti-phase terminal voltage Vd of sampling secondary inductance：Secondary-side switch pipe is turned off when Vd is more than 0V, is led during less than 0V
Logical secondary-side switch pipe, the advantage of the method is that detection mode is simple, unrelated with the change of primary side sampled voltage under discontinuous mode；Shortcoming
It is that can not support continuous mode, is easily caused secondary inductance and inversely discharges, and requires the speed of driving shut-off secondary-side switch pipe
It is fast.
3rd, other：The synchronous rectification done for primary side structure, is controlled in linear zone after the conducting of secondary-side switch pipe, makes secondary electricity
The Vgs of secondary-side switch pipe increases when stream reduces and Vds is constant, and such primary side sampled voltage is stablized relatively, is conducive to system stable
Property, the advantage of the method is that former secondary structural system is stable；Have the disadvantage the work of secondary-side switch pipe in linear zone, loss is relative can be big
A bit.
It is therefore proposed that a kind of loss is small, while compatible continuous mode and the synchronous commutating control circuit of discontinuous mode are urgently
To be solved the problem of.
Utility model content
The problem of being existed based on prior art, the utility model proposes a kind of synchronous rectification control chip, including：
Conducting initializing circuit, voltage detecting circuit, pattern decision circuit, fault secure circuit, advanced breaking circuit, lead
Logical time setting circuit, selection circuit, control circuit, triggers circuit and drive circuit；
The conducting initializing circuit, voltage detecting circuit, pattern decision circuit connection Input voltage terminal；
The conducting initializing circuit connects the voltage detecting circuit；
The voltage detecting circuit connects the fault secure circuit, advanced breaking circuit, control circuit, triggers circuit；
The pattern decision circuit, fault secure circuit connect the input of the selection circuit；
The selection circuit, the voltage detecting circuit, the advanced breaking circuit, the ON time initialization circuit connect
Connect the input of the control circuit；
The output end of the control circuit connects the triggers circuit；
The output end of the triggers circuit connects the drive circuit.
Preferably, the conducting initializing circuit is used for：When judging input voltage for effective input voltage, output allows to lead
Messenger；
The voltage detecting circuit is used for：Detect numerical value, cycle time and the effective input voltage of input voltage
First duration；When the permission Continuity signal is effective, output control Continuity signal gives the triggers circuit；By described
One duration was exported to the fault secure circuit；The cycle time is exported to the advanced breaking circuit；According to having
Input voltage and the comparative result of the first setting value are imitated, output voltage comparison signal gives the control circuit；
The pattern decision circuit is used to judge external circuit mode of operation, and the mode of operation includes：Continuous mode and/or
Discontinuous mode；
The fault secure circuit continued according to first duration in a upper cycle with described the first of this cycle
Time, export error protection signal；
The selection circuit judges whether the error protection signal is effective according to the mode of operation；
The advanced breaking circuit according to the cycle time in this cycle and the cycle time in a upper cycle,
Export advanced cut-off signals；
The triggers circuit exports Continuity signal according to the output signal of the voltage detecting circuit and the control circuit
Or cut-off signals；
The ON time initialization circuit is used for the maximum retention time for controlling the Continuity signal, is reached in ON time
Output overtime signal gives the control circuit during maximum；The control circuit is according to the selection circuit, the voltage detecting
Circuit, the advanced breaking circuit, the output of the ON time initialization circuit, output control cut-off signals are to the triggering electricity
Road；
The drive circuit is according to the Continuity signal and the cut-off signals, output drive signal.
Preferably, the magnitude of voltage of input voltage and first threshold are compared by the conducting initializing circuit, while right
The duration of the magnitude of voltage carries out timing and is compared the duration and Second Threshold, when the magnitude of voltage is big
It is effective input voltage when the first threshold and/or the duration are more than the Second Threshold, exporting allows conducting
Signal is to the voltage detecting circuit.
Preferably, the first threshold includes the first high voltage threshold and the first low voltage threshold, first high voltage
Threshold value is inputted corresponding to high voltage, and first low voltage threshold is inputted corresponding to low-voltage.
Preferably, the voltage detecting circuit is used to detect input voltage, when the permission Continuity signal is effective, in institute
State effective input voltage trailing edge or be delayed a period of time after trailing edge, output control Continuity signal is to the triggering electricity
Road；The triggers circuit is according to the control Continuity signal output Continuity signal；The drive circuit is according to the Continuity signal
Output driving Continuity signal.
Preferably, the pattern decision circuit is sentenced according to the number of oscillation of input voltage between two adjacent effective input voltages
Disconnected mode of operation is continuous mode or discontinuous mode.
Preferably, when the number of oscillation is more than or equal to 2, external circuit is operated in discontinuous mode, otherwise, external circuit work
In continuous mode.
Preferably, the fault secure circuit is with a certain numerical value of first duration less than or equal to a upper cycle
For the first benchmark, according to first duration in this cycle and the comparative result of first benchmark, error protection is exported
Signal.
Preferably, the selection circuit judges the error protection signal according to the output signal of the pattern decision circuit
Effectively whether, when mode of operation is continuous mode, the error protection signal is shielded, when mode of operation is discontinuous mode
The error protection signal is effective.
Preferably, the initial time of ON time initialization circuit sampling Continuity signal and timing is started, when conducting letter
When number duration exceedes setting time, output overtime signal gives the control circuit
The utility model is by way of Cycle by Cycle analogy, and the drain terminal voltage vd that detection inductance is connected with SR_MOSFET can
IC accurately control can be discharged the time point completed when being operated in DCM/CCM patterns, effective to judge shut-off point, realization is carried
Preceding turn-off function, both realizes high efficiency, can prevent SR_MOSFET from causing the possibility of aircraft bombing because of reverse electric discharge again；Solve existing
Have can not be while can realize the problem accurately turned off in technology under DCM/CCM both of which；Periphery can be simplified simultaneously should
With circuit, reduce application device.
Brief description of the drawings
Fig. 1 is a kind of structural representation of synchronous rectification chip of the present utility model；
Fig. 2 is a kind of structural representation of the synchronous rectification chip of embodiment of the present utility model；
Fig. 3 is synchronous rectification chip discontinuous mode working waveform figure of the present utility model；
Fig. 4 is synchronous rectification chip continuous mode working waveform figure of the present utility model；
The oscillogram that Fig. 5 is turned off in advance when being discontinuous mode of the present utility model；
Fig. 6 is the oscillogram of discontinuous mode error protection of the present utility model；
Advanced shut-off oscillogram when Fig. 7 is both of which of the present utility model；
Fig. 8 is the structural representation of synchronous commutating control circuit figure of the present utility model；
Fig. 9 is the method for rectifying schematic flow sheet of circuit of synchronous rectification of the present utility model；
Figure 10 is the synchronous commutating control circuit oscillogram under discontinuous mode of the present utility model；
Figure 11 is the synchronous commutating control circuit oscillogram under continuous mode of the present utility model.
Embodiment
Fig. 1 show synchronous rectification chip structure schematic diagram of the present utility model, and the synchronous rectification chip includes：Conducting
Initializing circuit 10, voltage detecting circuit 20, pattern decision circuit 30, fault secure circuit 40, advanced breaking circuit 50, selection
Circuit 60, time setting circuit 70, control circuit 80, triggers circuit 90, drive circuit 100.The conducting initializing circuit 10,
Voltage detecting circuit 20, pattern decision circuit 30 are respectively connecting to voltage input end；The conducting initializing circuit 10 connection institute
State voltage detecting circuit 20, the voltage detecting circuit 20 connect respectively the fault secure circuit 40, advanced breaking circuit 50,
Control circuit 80, triggers circuit 90；The pattern decision circuit 30, fault secure circuit 40 connect the defeated of the selection circuit 60
Enter end；The selection circuit 60, the voltage detecting circuit 20, the advanced breaking circuit 50, ON time setting electricity
Road 70 connects the input of the control circuit 80；The selection circuit 60 is electric with pattern decision circuit 30, error protection respectively
Road 40, control circuit 80 are connected；The control circuit 80 respectively with time setting circuit 70, voltage detecting circuit 20, advanced close
Deenergizing 50, selection circuit 60, triggers circuit 90 are connected；The time setting circuit 70 is electric with triggers circuit 90, driving respectively
Road 100 is connected.The pattern decision circuit 30, fault secure circuit 40 connect the input of the selection circuit 60, the choosing
The input that circuit 60, the advanced breaking circuit 50, the time setting circuit 70 connect the control circuit 80 is selected, it is described
The output end of circuit 80 is controlled to connect the triggers circuit 90, the output end of the triggers circuit 90 connects the drive circuit
100。
1st, when the conducting initializing circuit 10 is used to judge input voltage for effective input voltage, output allows conducting to believe
Number A1.Input voltage VS is compared by the conducting initializing circuit 10 with first threshold, when input voltage is more than the first threshold
When value and/or duration exceed Second Threshold, then this input voltage is effective input voltage, and conducting initializing circuit 10 is exported
Allow Continuity signal A1 to voltage detecting circuit 20.
The first threshold is for voltage, Second Threshold is default for the time,.
When high voltage input is inputted with low-voltage, first threshold is different, thus sets two comparators to input
Voltage is compared.Specifically, the first threshold includes the first high voltage threshold and/or the first low voltage threshold, right respectively
High voltage input is answered to input two kinds of different conditions with low-voltage.First high voltage threshold is inputted corresponding to high voltage, described
First low voltage threshold is inputted corresponding to low-voltage.
2nd, the voltage detecting circuit 20 is used for numerical value, cycle time and the effective input voltage for detecting input voltage
The first duration；When the permission Continuity signal A1 is effective, output control Continuity signal A2 gives the triggers circuit 90；
The voltage detecting circuit 20 exports first duration to the fault secure circuit 40；The cycle time is defeated
Go out to the advanced breaking circuit 50；According to effective input voltage and the ratio of the first setting value (the first setting value is less than or equal to zero)
Relatively result, output voltage comparing signals A 3 is to the control circuit 80.
When the permission Continuity signal A1 is effective, it is delayed in effective input voltage trailing edge or after trailing edge
For a period of time, output control Continuity signal A2 gives the triggers circuit 90；The triggers circuit 90 is according to the control conducting letter
Number A2 output Continuity signal；The drive circuit is according to the Continuity signal output driving Continuity signal.
Input voltage VS is compared by the voltage detecting circuit 20 with the first setting value, output voltage comparing signals A 3
To control circuit 80；First setting value is less than or equal to no-voltage.First setting value is default for voltage
's.
The record of voltage detecting circuit 20 input voltage is more than duration during first threshold, and during by described continuing
Between waveform at export to fault secure circuit 40.
The voltage detecting circuit 20 records input voltage from effective input voltage rising edge to another subsequent rising
The time on edge, using time period as a cycle, and the cycle time waveform AT is exported to advanced breaking circuit 50.
3rd, the pattern decision circuit 30 is used to judge that external circuit mode of operation is continuous mode or discontinuous mode.
Specifically, the pattern decision circuit 30 is used for the vibration according to input voltage between two adjacent effective input voltages
Number of times judges that external circuit mode of operation is continuous mode or discontinuous mode.The record of pattern decision circuit 30 two is adjacent effectively defeated
Enter the number of times of input voltage rising edge between voltage, when the number of times is more than or equal to 2, judge that mode of operation is discontinuous mode,
Otherwise it is continuous mode；And output mode signal ccmH is to selection circuit 60.Continuous mode or discontinuous mode refer to where chip
External circuit mode of operation.
4th, the fault secure circuit 40 is according to described the first of first duration in a upper cycle and this cycle
Duration, output error protection signal ftpL.
The fault secure circuit 40 is using a certain numerical value of first duration less than or equal to a upper cycle as
One benchmark, according to first duration in this cycle and the comparative result of first benchmark, exports error protection signal
ftpL。
Fault secure circuit 40, the first duration waveform at of the effective input voltage exported with voltage detecting circuit 20
For foundation, the first duration of effective input voltage when recording a upper cycle, and had during with less than or equal to the upper cycle
The a certain numerical value for imitating first duration of input voltage is the first benchmark.First when this cycle effective input voltage holds
The continuous time is less than the first benchmark, and both differences are when being more than or equal to the second setting value, and output error protection signal ftpL is to selecting
Select circuit 60.First duration is the duration of effective input voltage.
5th, the advanced breaking circuit 50 is using a certain numerical value of the cycle time less than or equal to a upper cycle as second
Benchmark, according to the cycle time in this cycle and the cycle time in a upper cycle, exported advanced cut-off signals.
The advanced breaking circuit using a certain numerical value of the cycle time less than or equal to a upper cycle as the second benchmark,
According to the cycle time in this cycle and the cycle time in a upper cycle, advanced cut-off signals were exported.
Advanced breaking circuit 50, the periodic waveform AT using the output of voltage detecting circuit 20 is foundation, a cycle on record
Cycle time, and using a certain numerical value of the cycle time less than or equal to the upper a cycle as the second benchmark, when this cycle
Cycle time when being more than the second benchmark, export advanced cut-off signals A5.The cycle time in a upper cycle inputs from effective
Voltage starts, until effective input voltage drops to less than zero and terminated when being more than zero again.
6th, the selection circuit 60 is used to judge whether the error protection signal is effective according to the mode of operation.
The selection circuit 60 is according to the mode of operation, by the error protection signal output in discontinuous mode to described
Circuit is controlled, by the error protection signal shielding in continuous mode.
The selection circuit 60 judges the error protection signal according to the output signal of the pattern decision circuit 30
Whether ftpL is effective, and when mode of operation is continuous mode, the error protection signal is shielded, when mode of operation is interrupted mould
The error protection signal is effective during formula.The selection circuit output selection signal A4.
7th, the ON time initialization circuit 70 is used for the maximum retention time for controlling the Continuity signal, in ON time
Output overtime signal A6 is to the control circuit 80 when reaching maximum.
The initial time of the sampling of ON time initialization circuit 70 Continuity signal simultaneously starts timing, when Continuity signal continues
When time exceedes setting time, output overtime signal A6 is to the control circuit 80.
The ON time initialization circuit 70, in the rising edge of trigger signal, the start recording triggered time, when closed between
During more than three setting values, the output overtime signal A6 of ON time initialization circuit 80 gives control circuit 80.3rd setting value
It is default.
The rising edge of trigger signal can also be in the chips relevant position sampling, be not only triggers circuit output
End.
8th, the control circuit 80 is according to the selection circuit 60, the voltage detecting circuit 20, the advanced shut-off electricity
Road 50, the output of the ON time initialization circuit 70, output control cut-off signals give the triggers circuit 90.
The voltage detecting circuit 20, the advanced breaking circuit 50, the selection circuit 60, ON time setting
When the output signal of at least one circuit is effective in circuit 70, the output control cut-off signals of control circuit 80 give the triggering
Circuit 90；The triggers circuit 90 is according to the control cut-off signals output cut-off signals.
9th, the triggers circuit 90 is according to the output signal of the voltage detecting circuit 20 and the control circuit 80, output
Continuity signal or cut-off signals.
Triggers circuit 90 is when the control Continuity signal A2 that voltage detecting circuit 20 is exported is effective, and triggers circuit 90 is effective
Delay a period of time output Continuity signal after the trailing edge or trailing edge of input voltage；The control shut-off exported in control circuit 80
When signal is effective, the output cut-off signals of triggers circuit 90.
10th, the drive circuit 100 is used for according to the Continuity signal or the cut-off signals, output drive signal.
The method of work to above-mentioned synchronous rectification chip elaborates below.
Input voltage is detected, allows to lead when input voltage is more than first threshold and/or the duration exceedes Second Threshold
Logical, the input voltage is effective input voltage, when input voltage is less than zero after effective input voltage, that is, described
The trailing edge of effective input voltage, or be delayed a period of time after the trailing edge, the triggers circuit output Continuity signal of chip；
When input voltage is by rising above zero less than zero, that is, input voltage is when being more than or equal to the first setting value, the triggering of chip
Circuit 90 exports cut-off signals.
The cycle time in a record upper cycle, using a certain numerical value of the cycle time less than or equal to a upper cycle as the second base
It is accurate；The cycle time is since effective input voltage, until effective input voltage drops to less than zero and again more than zero
When terminate.
A record upper cycle is more than first threshold in input voltage and/or the duration exceedes effective input of Second Threshold
First duration of voltage, using a certain numerical value less than or equal to first duration as the first benchmark.
The number of times of input voltage rising edge between effective input voltage of the upper cycle and this cycle effective input voltage was recorded,
The mode of operation of external circuit is judged with the value of the number of times, is discontinuous mode DCM when the value of the number of times is more than or equal to 2, it is no
It is then continuous mode CCM.
When the first duration of effective input voltage in this cycle being more than or equal to the first benchmark, according to voltagesecond product conservation
Rule, cycle time in this cycle can be more than the second benchmark, then this cycle effective input voltage trailing edge or trailing edge
Afterwards delay a period of time, Continuity signal is exported, when the cycle time in this cycle being more than or equal to the second benchmark, the triggering electricity of chip
Road 90 exports cut-off signals, realizes advanced shut-off.
When the first duration of effective input voltage in this cycle being less than the first benchmark, and both differences are less than the
Two setting values, while when external circuit is operated in discontinuous mode, then after the trailing edge of effective input voltage in this cycle, output is led
Messenger, when the cycle time in this cycle being more than or equal to the second benchmark, the output cut-off signals of triggers circuit 90 of chip are realized
Advanced shut-off.
It is less than the first benchmark when the duration of effective input voltage in this cycle, and both differences are more than or equal to second
Setting value, while when external circuit is operated in discontinuous mode, then after the trailing edge of effective input voltage in this cycle, chip is touched
Power Generation Road 90 exports cut-off signals, realizes advanced shut-off.
It is less than the first benchmark when the duration of effective input voltage in this cycle, while external circuit is operated in continuous mode
When, then after the trailing edge of effective input voltage in this cycle, the output Continuity signal of triggers circuit 90；At the cycle in this cycle
Between when being more than or equal to the second benchmark, the output cut-off signals of triggers circuit 90 of chip realize advanced shut-off.
When chip triggers circuit 90 export the Continuity signal duration be more than or equal to three setting values when, chip touch
Power Generation Road 90 exports cut-off signals.
The foundation judged in next cycle, chip using first benchmark in this cycle, the second benchmark as shut-off, according to similar
Method of work, the output Continuity signal and cut-off signals of triggers circuit 90, while recording first benchmark in a cycle, the second base
Prepare to use.
Fig. 2 is a kind of structural representation of the synchronous rectification chip of embodiment of the present utility model, wherein selection circuit 60
It is that, by being realized with door, control circuit 80 is realized that triggers circuit 90 is realized by d type flip flop by nor gate.
Fig. 3 is synchronous rectification chip discontinuous mode working waveform figure of the present utility model.As shown in figure 3, voltage detecting is electric
The detection input voltage of road 20 is more than zero and minus change.High level is exported when input voltage is more than zero, works as input voltage
Low level is exported during less than zero, voltage comparison signal waveform is as shown in A3 in figure, between two neighboring effective input voltage, when
When the pulse number of voltage comparison signal is more than or equal to 2, the output mode of pattern decision circuit 30 judges signal ccmH for high level,
It is discontinuous mode DCM to represent external circuit mode of operation, and this high level continues to that effective input voltage terminates rear and is delayed next time
For a period of time, when the pulse number of voltage comparison signal is less than 2, the output mode of pattern decision circuit 30 judges that signal ccmH is
Low level, it is continuous mode CCM to represent external circuit mode of operation, and mode of operation signal waveform is as shown in ccmH waveforms in figure；Or
Person, the detection input voltage of voltage detecting circuit 20 is compared with some numerical value less than zero or more than zero, draws voltage
Comparison signal.
Input voltage Vs is compared by conducting initializing circuit 10 with first threshold, when input voltage Vs is more than the first threshold
When value and/or duration are more than Second Threshold, the input voltage is effective input voltage, and the conducting output of initializing circuit 10 is permitted
Perhaps Continuity signal is to voltage detecting circuit 20, it is allowed to which Continuity signal waveform is as shown in A1 in figure.
Voltage detecting circuit 20 is when allowing Continuity signal effective, in the trailing edge output control Continuity signal of input voltage
To triggers circuit 90, control Continuity signal waveform is as shown in waveform A2 in figure；The output control when input voltage is more than zero again
Cut-off signals, triggers circuit 90 is according to control Continuity signal and control cut-off signals output on or off signal, and its waveform is such as
In figure shown in Gate.
Or, voltage detecting circuit 20 is when allowing Continuity signal effective, trailing edge of the triggers circuit 90 in input voltage
Be delayed for a period of time output control Continuity signal again afterwards, but input voltage is more than necessary output control cut-off signals when zero.
In the present embodiment, the first setting value is zero；In this application, the first setting value is some less than or equal to zero
Numerical value.
Fig. 4 is synchronous rectification chip continuous mode working waveform figure of the present utility model；As shown in figure 4, voltage detecting is electric
The detection input voltage of road 20 is more than zero and minus change, exports high level when input voltage is more than zero, works as input voltage
Low level is exported during less than zero, voltage comparison signal is as shown in waveform A3 in figure.
Between two adjacent effective input voltages, when the pulse number of voltage comparison signal is less than 2, pattern decision circuit
30 output low levels, it is continuous mode to represent external circuit mode of operation, and mode decision waveform is as shown in ccmH waveforms in figure.
Input voltage Vs is compared by conducting initializing circuit 10 with first threshold, when input voltage Vs is more than the first threshold
When value and/or duration are more than Second Threshold, the input voltage is effective input voltage, and the conducting output of initializing circuit 10 is permitted
Perhaps Continuity signal is to voltage detecting circuit 20, it is allowed to which Continuity signal waveform is as shown in A1 in figure.
Voltage detecting circuit 20 is in the trailing edge of effective input voltage, that is, when allowing Continuity signal effective, output control is led
Messenger controls the oscillogram of Continuity signal as shown in waveform A2 in figure to triggers circuit 90.
Triggers circuit 90 effective input voltage trailing edge output drive signal, input voltage be more than zero when, also
It is that, when voltage comparison signal is effective, the control output control cut-off signals of circuit 80 are to triggers circuit 90, and triggers circuit 90 is exported
Cut-off signals, the output waveform of triggers circuit 90 is as shown in waveform Gate in figure.Or, triggers circuit 90 is in effective input voltage
Delay a period of time output drive signal again after trailing edge, but input voltage must export cut-off signals when being more than zero.
The oscillogram that Fig. 5 is turned off in advance when being discontinuous mode of the present utility model；As shown in figure 5, T1 was a upper cycle
Cycle time, t11 is the first duration of a upper cycle effective input voltage, and t12 is that upper periodical input voltage is less than zero
The second duration.
T2 is the cycle time in this cycle, and t21 is the first duration of this cycle effective input voltage, and t22 is this week
Phase input voltage minus second duration.
The waveform of first duration is as shown at waveforms in figure, and the waveform of cycle time is as shown in AT waveforms in figure；Mould
The output of formula decision circuitry is as shown in ccmH waveforms in figure.
It is the first benchmark to take the numerical value t3 less than upper cycle duration t11, is taken less than upper cycle time T1
Numerical value t1 be the second benchmark, it is fixed according to voltagesecond product conservation when the first duration t21 in this cycle is more than or equal to numerical value t3
Rule, T2 is more than T1, is limited with the second benchmark t1, when the cycle time in this cycle being equal to the second benchmark t1, advanced breaking circuit
The 50 advanced cut-off signals of output, control circuit 80 is according to the advanced cut-off signals output control cut-off signals to triggers circuit
90, advanced cut-off signals waveform is as shown in A5 in figure, the output cut-off signals of triggers circuit 90, Gate waveforms institute in its waveform such as figure
Show, Gate waveforms are delayed just effective for a period of time after the trailing edge of effective input voltage in this example.
T21 is more than t11 in the present embodiment, and error protection is without output, as shown in ftpL waveforms in Fig. 5.
Fig. 6 is the oscillogram of discontinuous mode error protection of the present utility model.In Fig. 6, pattern decision circuit judges dispatch from foreign news agency
The mode of operation on road is discontinuous mode, and exports the mode of operation signal as shown in ccmH waveforms in figure；
From unlike Fig. 5, the first duration t21 of effective input voltage in this cycle was less than the effective of a upper cycle
First duration t11 of input voltage, t3 is less than the first duration t11 of effective input voltage in cycle number
Value, is taken as first benchmark in this cycle, and t21 is more than or equal to the second setting value, error protection with the difference less than the first benchmark t3
Circuit 40 exports error protection signal, and error protection signal waveform is as shown in ftpL waveforms in figure；
In mode of operation signal and simultaneously effective error protection signal, i.e., external circuit is operated in discontinuous mode state and sheet
First duration of effective input voltage in cycle is much smaller than the first duration of effective input voltage in a upper cycle, choosing
Select circuit 60 and export selection signal A4 to circuit 80 is controlled, control circuit 80 is given according to the control signal output control cut-off signals
Triggers circuit 90, triggers circuit 90 exports cut-off signals, then chip does not export Continuity signal in this cycle, is held off.
Advanced shut-off oscillogram when Fig. 7 is both of which of the present utility model.As shown in fig. 7, T1 is the period 1
Cycle time, T2 is the cycle time of second round, and T3 is the cycle time of period 3；T1 is the cycle time of period 1
The second benchmark, t2 is the second benchmark of the cycle time of second round, and t3 first holds for period 1 effective input voltage
The first benchmark of continuous time, t4 is the first benchmark of the first duration of second round effective input voltage；In the period 1
Between two adjacent effective input voltages of second round, there is vibration in input voltage, there is the voltage comparison signal more than 2 times
Pulse, pattern decision circuit judges that external circuit is operated in discontinuous mode, exports high level signal according to this umber of pulse；Second
Between cycle effective input voltage adjacent with the period 3 two, input voltage is less than zero, voltage comparison signal no pulse, mould
Formula decision circuitry judges that external circuit is operated in continuous mode, exports low level signal；CcmH in mode decision signal waveform such as figure
It is shown.
First duration t21 of second round effective input voltage is more than the first benchmark of period 1, in second week
It is delayed after the trailing edge of phase effective input voltage a period of time, the output Continuity signal of triggers circuit 90, in the cycle of second round
When time T2 is equal to the second benchmark t1 of period 1, advanced decision circuitry 50 exports advanced cut-off signals and gives control circuit 80,
Control the output control cut-off signals of circuit 80 to triggers circuit 90, the output cut-off signals of triggers circuit 90 realize advanced shut-off.
First duration t31 of effective input voltage of period 3 is much smaller than the first benchmark t4 of second round,
That is the first duration t31 and the first benchmark t4 of second round of effective input voltage of period 3 difference are more than
Equal to the second setting value, fault secure circuit 40 exports ftpL waveforms in error protection signal, error protection signal waveform such as figure
It is shown；
Because the mode of operation of period 3 external circuit is continuous mode, and the working frequency of external circuit is solid during connection mode
Fixed, i.e. cycle time T3 is equal with T2, therefore selection circuit 60 masks this error protection signal, and triggering pattern 90 is the 3rd
Gate ripples in delay a period of time output Continuity signal, Continuity signal waveform such as figure after the trailing edge of effective input voltage in cycle
Shown in shape, when the cycle time T3 of period 3 is equal to the second benchmark t2 of second round, the advanced output of decision circuitry 50 is super
Preceding cut-off signals give control circuit 80, and the control output control cut-off signals of circuit 80 are to triggers circuit 90, and triggers circuit 90 is exported
Cut-off signals, realize advanced shut-off.
Fig. 8 show a kind of structural representation of synchronous commutating control circuit of the present utility model.The synchronous rectification control
Circuit processed includes primary circuit, secondary circuit.
The primary circuit includes primary inductor L p, primary side switch pipe PR, primary side sampling resistor Rcs；The primary side inductance
Lp in-phase end connection primary side switch pipe PR one end, the one of primary side switch pipe PR other end connection primary side sampling resistor Rcs
End, the ground terminal of primary side sampling resistor Rcs another termination primary circuit, primary side switch pipe PR control termination primary-side-control
Signal.
The secondary circuit includes secondary inductance L1, secondary-side switch pipe SR, the first sampling resistor of secondary R1, secondary second and adopted
Sample resistance R2, secondary electric capacity C2, secondary load resistance R3, synchronous rectification control chip IC1；The synchronous rectification control chip
IC1 is foregoing synchronous rectification control chip.
Secondary inductance L1 in-phase end connection synchronous rectification control chip IC1 power end, secondary electric capacity C2 positive pole, institute
State secondary load resistance R3 one end；Secondary inductance L1 end of oppisite phase connection secondary switching tube SR one end, secondary first are sampled
Resistance R1 one end；The first sampling resistor of secondary R1 other end connection synchronous rectification control chip IC1 input, secondary the
Two sampling resistor R2 one end, secondary electric capacity C2 negative pole, the secondary load resistance R3 other end, secondary-side switch pipe SR it is another
End, synchronous rectification control chip IC1 ground terminal are connected to the ground terminal of secondary circuit, and secondary-side switch pipe SR control end connection is synchronous
, there is parasitic diode D1 between secondary-side switch pipe SR one end and the other end in the output end of rectification control chip.
The primary inductor L p, secondary inductance L1 are the primary inductor L p of same transformer, secondary inductance L1 respectively.
Synchronous rectification control chip IC1 detects the voltage Vd of secondary inductance L1 end of oppisite phase, as the voltage Vd of the end of oppisite phase
Partial pressure Vs be more than first threshold and/or be continued above time of Second Threshold, this voltage is effective voltage, then judges now former
Side switching tube PR is turned on, and the secondary inductance L1 and primary inductor L p produces electromagnetic induction, and secondary-side switch pipe is off state.
When primary side switch pipe shut-off, when the voltage of the end of oppisite phase drops to less than zero by the effective voltage, institute
The conducting of secondary-side switch pipe is stated, the secondary inductance electric discharge, the secondary electric capacity charging closes on completion in secondary inductance electric discharge
When, the secondary-side switch pipe shut-off prevents the secondary electric capacity from passing through the secondary-side switch tube discharge.
The voltage that the synchronous rectification control chip detects end of oppisite phase described in this cycle is dropped to by the effective voltage
During less than zero, i.e., it is delayed after the trailing edge or trailing edge of effective voltage a period of time, output drive signal drives the secondary
Switching tube is turned on.
The voltage that the synchronous rectification control chip detects the end of oppisite phase begun to decline by the effective voltage
When one trailing edge is to first subsequent rising edge, output cut-off signals turn off the secondary-side switch pipe.
The synchronous rectification control chip detects the mode of operation of the secondary inductance, to be opened in adjacent secondary described twice
The rising edge quantity that the voltage of the secondary inductance end of oppisite phase is begun to ramp up by zero volt or so in the pipe turn-off time of pass is as judgement
Foundation, when the quantity of the rising edge is more than or equal to 2, judges that the secondary inductance is operated in discontinuous mode；Otherwise, institute is judged
State secondary inductance and be operated in continuous mode.
The synchronous rectification control chip detects and records the first ON time of primary side switch pipe described in a cycle, and
Some numerical value using first ON time less than or equal to the upper cycle is the first benchmark；With the primary side switch
The ON time of pipe first is cycle time with the second ON time of secondary-side switch pipe sum, and with less than or equal to a upper cycle
The cycle time some numerical value be the second benchmark, by first ON time in this cycle and first benchmark
It is compared, according to comparative result, controls the shut-off moment of the secondary-side switch pipe.
The first ON time that the synchronous rectification control chip detects the primary side switch pipe in this cycle is more than institute
The first benchmark is stated, then after the primary side switch pipe shut-off in this cycle, the secondary-side switch pipe conducting is controlled, in this cycle
When the cycle time is equal to second benchmark, the secondary-side switch pipe shut-off is controlled.
The first ON time that the synchronous rectification control chip detects the primary side switch pipe in this cycle is less than institute
The first benchmark is stated, and both differences are less than the second setting value, meanwhile, detect synchronous commutating control circuit and be operated in interrupted mould
During formula, then after the primary side switch pipe shut-off in this cycle, the secondary-side switch pipe conducting is controlled, in the week in this cycle
When time phase is equal to second benchmark, the secondary-side switch pipe shut-off is controlled.
The first ON time that the synchronous rectification control chip detects the primary side switch pipe in this cycle is less than institute
State the first benchmark, and both differences are more than or equal to the second setting value, meanwhile, when detecting circuit and being operated in discontinuous mode, then
It is not turned in secondary-side switch pipe described in this cycle, is off state.
The first ON time that the synchronous rectification control chip detects the primary side switch pipe in this cycle is less than institute
The first benchmark is stated, meanwhile, when detecting synchronous commutating control circuit and being operated in continuous mode, then the primary side in this cycle is opened
Close after pipe shut-off, control the secondary-side switch pipe conducting, when the cycle time in this cycle being equal to second benchmark, control
Make the secondary-side switch pipe shut-off.
It is delayed a period of time after the primary side switch pipe shut-off in this cycle or after shut-off, the synchronous rectification controls core
Piece controls the secondary-side switch pipe conducting.
The synchronous rectification control chip detects secondary-side switch pipe ON time described in this cycle more than the 3rd setting value,
Then turn off the secondary-side switch pipe.
The method for rectifying of synchronous commutating control circuit is described further below according to Fig. 9.
The synchronous commutating control circuit includes primary circuit, secondary circuit, and the primary circuit is in electromagnetic coupled mode
Secondary circuit is connected, the secondary circuit includes synchronous rectification control chip, secondary-side switch pipe, secondary inductance.The above one week
First duration of the effective voltage of phase secondary circuit and the cycle time of the synchronous commutating control circuit are foundation, incite somebody to action this
First duration of cycle effective voltage and the duration of the upper cycle effective voltage are compared, and are compared
Relatively result；According to the anti-phase terminal voltage of secondary inductance, oscillatory regime is sentenced between upper cycle effective voltage and this cycle effective voltage
The mode of operation of disconnected synchronous commutating control circuit；According to the comparative result and the mode of operation, control secondary-side switch pipe is led
Logical or cut-off, realizes and controls secondary circuit with Cycle by Cycle analogical pattern.
Using the first duration less than or equal to the upper cycle effective voltage as the first benchmark, with less than or equal to described
The cycle time in a upper cycle is the second benchmark.
When the anti-phase terminal voltage of the secondary inductance vibrates time between upper cycle effective voltage and this cycle effective voltage
When number is more than or equal to 2, decision circuitry is operated in discontinuous mode, and otherwise circuit is operated in continuous mode.
When synchronous commutating control circuit is operated in continuous mode, first duration of this cycle effective voltage is less than
During first benchmark, then after primary side switch pipe shut-off, the secondary-side switch pipe conducting, in the cycle time in this cycle
During equal to second benchmark, the secondary-side switch pipe is turned off.
When synchronous commutating control circuit is operated in discontinuous mode, first duration of this cycle effective voltage is less than
First benchmark, and both differences are less than the second setting value, then after primary side switch pipe shut-off, the secondary-side switch
Pipe is turned on, and when the cycle time in this cycle being equal to second benchmark, turns off the secondary-side switch pipe.
When synchronous commutating control circuit is operated in discontinuous mode, first duration of this cycle effective voltage is less than
First benchmark, and both differences are more than or equal to the second setting value, then after primary side switch pipe shut-off, the secondary
Switching tube is not turned on, and is off state.
It is more than first benchmark when first duration of this cycle effective voltage, then in the primary side switch pipe
After shut-off, the secondary-side switch pipe conducting, when the cycle time in this cycle being equal to second benchmark, turns off the secondary and opened
Guan Guan.
The secondary-side switch pipe conducting, is prolonged after primary side switch pipe shut-off, or in primary side switch pipe shut-off
When for a period of time, control secondary-side switch pipe conducting.
When the secondary-side switch pipe ON time is more than three setting values, the secondary-side switch pipe shut-off.
When secondary circuit detects the primary side switch pipe shut-off, control secondary-side switch pipe conducting, when secondary circuit inspection
When measuring the primary side switch pipe conducting, the pipe shut-off of control secondary-side switch.
Illustrate the course of work of circuit with reference to oscillogram：Ripple during discontinuous mode is operated in for circuit as shown in Figure 10
Shape figure, for convenience of description, is described in detail, by that analogy with time second round T2.
Between time period 1 T1, time second round T2, synchronous rectification control chip IC1 detects secondary inductance
L1 anti-phase terminal voltage Vd partial pressure Vs has two to the rising edge more than zero, decision circuit is operated in interrupted mould less than zero
Formula.
In time period 1 T1, synchronous rectification control chip IC1 record primary side switch pipes PR ON time t11, and
Using some numerical value less than or equal to t11 as the first benchmark, record is conducting to secondary inductance L1 from primary side switch pipe PR and discharged
Into the cycle time T1 before termination, and using some numerical value less than or equal to T1 as the second benchmark.
In time second round T2, when primary side switch pipe PR is turned on, i.e., there is electric current to lead on the t21 periods, primary inductor L p
Cross, primary inductor L p chargings, primary inductor L p in-phase ends voltage is equal to Vcs, and because electric current can not be mutated in inductance, Vcs gradually rises
Height, meanwhile, secondary inductance L1 senses electromagnetic energy, and secondary inductance L1 anti-phase terminal voltage Vd is equal to V2, synchronous rectification control
The partial pressure Vs that chip IC 1 detects the voltage Vd of secondary inductance L1 end of oppisite phase is more than first threshold and/or duration more than the
During two threshold values, got ready to allow secondary-side switch pipe SR to turn on, record the time value of t21 periods；
Set that voltage Vd partial pressure Vs is more than first threshold and/or the duration exceedes the judgement of Second Threshold, be in order to
Erroneous judgement is prevented, because when circuit is operated in discontinuous mode, between two cycles, secondary inductance voltage can produce vibration, but shake
The maximum voltage value V1 and duration t23 of the anti-phase terminal voltage of secondary inductance at least one is turned on than primary side switch pipe when swinging
When secondary inductance L1 end of oppisite phase voltage V2 and the duration it is small, and the setting of first threshold and Second Threshold, it is to avoid in pair
Secondary-side switch pipe SR misleads during the circuit oscillation of side.
In the t22 periods, primary side switch pipe PR is turned off, no current on primary inductor L p, and its anti-phase terminal voltage is E1, now,
The voltage Vd of secondary inductance L1 end of oppisite phase is sported less than zero (having but small oscillations), and secondary inductance L1 is put by parasitic diode D1
Electricity, secondary electric capacity C2 chargings, secondary current waveform is as shown in Is in figure, and synchronous rectification control chip IC1 is by time second round
T2 primary side switch pipe PR ON times t21 and time period 1 T1 the first benchmark is compared, and is divided into following several situations：
When primary side switch pipe PR ON times t21 is more than the first benchmark of period 1, T2 times time second round
Value be more than time period 1 T1 time values, synchronous rectification control chip IC1 detect voltage Vd drop to from effective voltage it is small
In zero, while or delay a period of time (in Fig. 10 be delay a period of time) output drive signal lead secondary-side switch pipe SR
Logical, synchronous rectification control chip IC1 exports cut-off signals when T2 times time second round being equal to the second benchmark, drives secondary
Switching tube SR is turned off, and realizes advanced shut-off；
When first benchmark of the primary side switch pipe PR ON times t21 less than the period 1, and both differences are less than second
During setting value, synchronous rectification control chip IC1 detects voltage Vd and drops to less than zero from effective voltage, while or one section of delay
Time (being delay a period of time in Figure 10) output drive signal turns on secondary-side switch pipe SR, in T2 times time second round
Cut-off signals are exported during equal to the second benchmark, advanced shut-off is realized in the SR shut-offs of driving secondary switching tube；
When primary side switch pipe PR ON times t21 is less than the first benchmark of period 1, and both difference is more than or equal to
During the second setting value, synchronous rectification control chip IC1 makes secondary-side switch pipe SR be in pass in this cycle output error protection signal
Disconnected state.
Oscillogram during continuous mode is operated in for circuit as shown in figure 11, continuous mode has similarity with discontinuous mode
Also there is difference.Equally for convenience of description, it is described in detail with time second round T2, by that analogy.
Similarity is：
In time period 1 T1, synchronous rectification control chip IC1 record primary side switch pipes PR ON time t11, and
Using some numerical value less than or equal to t11 as the first benchmark, record is conducting to secondary inductance L1 from primary side switch pipe PR and discharged
Into the cycle time T1 before termination, and using some numerical value less than or equal to T1 as the second benchmark.
In time second round T2, when primary side switch pipe PR opens conducting, i.e., there is electricity on the t21 periods, primary inductor L p
Stream passes through, primary inductor L p charging, primary inductor L p in-phase ends voltage be equal to Vcs, because electric current can not be mutated in inductance, Vcs by
Edge up height, meanwhile, secondary inductance L1 senses electromagnetic energy, and secondary inductance L1 anti-phase terminal voltage Vd is equal to V2, synchronous rectification
The partial pressure Vs that control chip IC1 detects the voltage Vd of secondary inductance L1 end of oppisite phase is more than first threshold or duration more than the
During two threshold values, got ready to allow secondary-side switch pipe SR to turn on, record the time value of t21 periods.
In the t22 periods, primary side switch pipe PR is turned off, no current on primary inductor L p, and its anti-phase terminal voltage is E1, now,
The voltage Vd of secondary inductance L1 end of oppisite phase is sported less than zero (having but small oscillations), and secondary inductance L1 is put by parasitic diode D1
Electricity, secondary electric capacity C2 chargings, synchronous rectification control chip IC1 is by time second round T2 primary side switch pipe PR ON times
T21 and time period 1 T1 the first benchmark is compared, and is divided into following several situations：
When primary side switch pipe PR ON times t21 is more than the first benchmark of period 1, T2 times time second round
Value be more than time period 1 T1 time values, synchronous rectification control chip IC1 detect voltage Vd drop to from effective voltage it is small
In zero, while or delay a period of time (in Fig. 10 be delay a period of time) output drive signal lead secondary-side switch pipe SR
Logical, synchronous rectification control chip IC1 exports cut-off signals when T2 times time second round being equal to the second benchmark, drives secondary
Switching tube SR is turned off, and realizes advanced shut-off；
It is a difference in that：
Between time period 1 T1, time second round T2, synchronous rectification control chip IC1 detects secondary inductance
L1 anti-phase terminal voltage Vd has two to the rising edge more than zero, decision circuit is operated in discontinuous mode less than zero.
But when circuit is operated in continuous mode, between two cycles, secondary inductance voltage will not produce vibration or produce
The vibration of number of times seldom, and vibration when the anti-phase terminal voltage of secondary inductance maximum voltage value V1 and duration t23 at least one
The voltage V2 of secondary inductance L1 end of oppisite phase and duration are small when item is turned on than primary side switch pipe, and first threshold and the second threshold
The setting of value, equally avoids the secondary-side switch pipe SR when secondary circuit vibrates and misleads.
When first benchmark of the primary side switch pipe PR ON times t21 less than the period 1, but during continuous mode work, frequency
It is fixed frequency, that is to say, that the cycle time T1 of period 1 is equal to the cycle time T2 of second round, therefore, even if former
Side switching tube PR ON times t21 is less than the first benchmark of period 1, and both differences are more than or equal to the second setting value, together
Step rectification control chip IC1 can mask the error protection signal under this mode of operation, detect voltage Vd from effective voltage
When dropping to less than zero, while or delay a period of time (be in Figure 10 delay a period of time) output drive signal make secondary-side switch
Pipe SR is turned on, and cut-off signals are exported when T2 times time second round being equal to the second benchmark, and driving secondary switching tube SR is turned off,
Realize advanced shut-off.
Although detailed description is given to embodiment of the present utility model above and is illustrated, it should be noted that
It is that we can carry out various equivalent changes and modification, the work(produced by it according to conception of the present utility model to aforesaid way
, all should be within protection domain of the present utility model when can act on the spirit still covered without departing from specification and accompanying drawing.
Claims (10)
1. a kind of synchronous rectification control chip, it is characterised in that the chip includes：
When turning on initializing circuit, voltage detecting circuit, pattern decision circuit, fault secure circuit, advanced breaking circuit, conducting
Between initialization circuit, selection circuit, control circuit, triggers circuit and drive circuit；
The conducting initializing circuit, voltage detecting circuit, pattern decision circuit connection Input voltage terminal；
The conducting initializing circuit connects the voltage detecting circuit；
The voltage detecting circuit connects the fault secure circuit, advanced breaking circuit, control circuit, triggers circuit；
The pattern decision circuit, fault secure circuit connect the input of the selection circuit；
The selection circuit, the voltage detecting circuit, the advanced breaking circuit, ON time initialization circuit connection institute
State the input of control circuit；
The output end of the control circuit connects the triggers circuit；
The output end of the triggers circuit connects the drive circuit.
2. synchronous rectification control chip according to claim 1, it is characterised in that：
The conducting initializing circuit is used for：When judging input voltage for effective input voltage, output allows Continuity signal；
The voltage detecting circuit is used for：Detect the first of numerical value, cycle time and the effective input voltage of input voltage
Duration；When the permission Continuity signal is effective, output control Continuity signal gives the triggers circuit；Described first is held
The continuous time is exported to the fault secure circuit；The cycle time is exported to the advanced breaking circuit；According to effectively defeated
Enter the comparative result of voltage and the first setting value, output voltage comparison signal gives the control circuit；
The pattern decision circuit is used to judge external circuit mode of operation, and the mode of operation includes：Continuous mode and/or discontinuously
Pattern；
The fault secure circuit according to first duration in a upper cycle and first duration in this cycle,
Export error protection signal；
The selection circuit judges whether the error protection signal is effective according to the mode of operation；
The advanced breaking circuit is according to the cycle time in this cycle and the cycle time in a upper cycle, output
Advanced cut-off signals；
The triggers circuit exports Continuity signal or pass according to the output signal of the voltage detecting circuit and the control circuit
Break signal；
The ON time initialization circuit is used for the maximum retention time for controlling the Continuity signal, and maximum is reached in ON time
Output overtime signal gives the control circuit during value；It is described control circuit according to the selection circuit, the voltage detecting circuit,
The output of the advanced breaking circuit, the ON time initialization circuit, output control cut-off signals give the triggers circuit；
The drive circuit is according to the Continuity signal and the cut-off signals, output drive signal.
3. synchronous rectification control chip according to claim 1 or 2, it is characterised in that：The conducting initializing circuit will
The magnitude of voltage of input voltage is compared with first threshold, while carrying out timing and by described in the duration of the magnitude of voltage
Duration is compared with Second Threshold, when the magnitude of voltage is more than more than the first threshold and/or the duration
It is effective input voltage during the Second Threshold, output allows Continuity signal to the voltage detecting circuit.
4. synchronous rectification control chip according to claim 3, it is characterised in that：
The first threshold includes the first high voltage threshold and the first low voltage threshold, and first high voltage threshold corresponds to height
Control source, first low voltage threshold is inputted corresponding to low-voltage.
5. synchronous rectification control chip according to claim 3, it is characterised in that：
The voltage detecting circuit is used to detect input voltage, when the permission Continuity signal is effective, in effective input
Voltage trailing edge is delayed a period of time after trailing edge, and output control Continuity signal gives the triggers circuit；The triggering
Circuit is according to the control Continuity signal output Continuity signal；The drive circuit is turned on according to the Continuity signal output driving
Signal.
6. synchronous rectification control chip according to claim 1 or 2, it is characterised in that：The pattern decision circuit according to
The number of oscillation of input voltage judges that mode of operation is continuous mode or discontinuous mode between two adjacent effective input voltages.
7. synchronous rectification control chip according to claim 6, it is characterised in that：When the number of oscillation is more than or equal to 2
When, external circuit is operated in discontinuous mode, otherwise, and external circuit is operated in continuous mode.
8. synchronous rectification control chip according to claim 2, it is characterised in that：The fault secure circuit with less than etc.
In a upper cycle first duration a certain numerical value be the first benchmark, according to first duration in this cycle
With the comparative result of first benchmark, error protection signal is exported.
9. synchronous rectification control chip according to claim 8, it is characterised in that：The selection circuit is according to the pattern
The output signal of decision circuitry judges whether the error protection signal is effective, the failure when mode of operation is continuous mode
Protection signal is shielded, and when mode of operation is discontinuous mode, the error protection signal is effective.
10. synchronous rectification control chip according to claim 1 or 2, it is characterised in that：
The initial time of the ON time initialization circuit sampling Continuity signal simultaneously starts timing, super when the Continuity signal duration
When crossing setting time, output overtime signal gives the control circuit.
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| CN201621157303.5U CN206442302U (en) | 2016-10-31 | 2016-10-31 | A kind of synchronous rectification control chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108494277A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous commutating control circuit improving electric efficiency |
| CN108964426A (en) * | 2018-08-27 | 2018-12-07 | 深圳市稳先微电子有限公司 | A kind of the control chip and AC-DC system of synchronous rectifier |
| CN112448705A (en) * | 2019-08-28 | 2021-03-05 | 上海顺久电子科技有限公司 | Mode selection circuit, integrated circuit, and electronic device |
-
2016
- 2016-10-31 CN CN201621157303.5U patent/CN206442302U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108494277A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous commutating control circuit improving electric efficiency |
| CN108964426A (en) * | 2018-08-27 | 2018-12-07 | 深圳市稳先微电子有限公司 | A kind of the control chip and AC-DC system of synchronous rectifier |
| CN108964426B (en) * | 2018-08-27 | 2020-09-15 | 深圳市稳先微电子有限公司 | Control chip of synchronous rectifier tube and AC-DC system |
| CN112448705A (en) * | 2019-08-28 | 2021-03-05 | 上海顺久电子科技有限公司 | Mode selection circuit, integrated circuit, and electronic device |
| CN112448705B (en) * | 2019-08-28 | 2024-05-03 | 上海顺久电子科技有限公司 | Mode selection circuit, integrated circuit and electronic device |
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