CN111200302B - Circuit for preventing battery from flowing backwards to USB - Google Patents
Circuit for preventing battery from flowing backwards to USB Download PDFInfo
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- CN111200302B CN111200302B CN201811366440.3A CN201811366440A CN111200302B CN 111200302 B CN111200302 B CN 111200302B CN 201811366440 A CN201811366440 A CN 201811366440A CN 111200302 B CN111200302 B CN 111200302B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Abstract
The invention discloses a circuit for preventing a battery from flowing backward to a USB (universal serial bus), which comprises a first operational amplifier, a second operational amplifier, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, a first resistor, a USB low-current detection circuit and a switch, wherein the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube, the drain electrode of the first MOS tube is respectively connected with the source electrode of the third MOS tube and the inverting input end of the second operational amplifier, the drain electrode of the second MOS tube is respectively connected with a battery end and the non-inverting input end of the second operational amplifier, and the grid electrode of the first MOS tube is further connected with the grid electrode of the second MOS tube through the switch. The invention can delay the starting time of the charging power tube by arranging the USB low-current detection circuit, thereby effectively preventing the battery from leaking electricity towards the USB direction in the short starting and charging time. The invention can be widely applied to the USB technology.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a circuit for preventing a battery from flowing backward to a USB.
Background
At present, a large number of portable electronic devices have the functions of USB and battery power supply, and can realize the charging of the battery by the USB. The USB ideal output voltage is 5V, and the maximum voltage of the lithium ion rechargeable battery is 4.2V. In practice, the USB voltage will connect other off-chip loads in addition to powering the chip. In addition, in order to prevent the chip from being damaged by the pulse voltage generated at the moment of USB insertion, a Schottky diode or a small resistor is connected in series before the USB voltage is connected into the chip, and the voltage of a USB pin of the chip is smaller than the voltage of a USB port. Under both of the above two application conditions, a sudden increase in the on-chip or off-chip load may cause the voltage of the USB pin to drop to approach or be less than the battery voltage. Such a situation may cause the system to falsely detect a USB unplug because the USB unplug detection threshold voltage is typically set to be slightly greater than the battery voltage in conventional charging control management systems.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a circuit for preventing a battery from flowing backward to a USB, which is capable of preventing a battery leakage current while a USB pull-out detection threshold voltage is lower than a battery voltage.
The technical scheme adopted by the invention is as follows:
a circuit for preventing a battery from flowing backward to a USB comprises a first operational amplifier, a second operational amplifier, a first MOS tube, a second MOS tube, a third MOS tube, a first resistor, a USB low-current detection circuit and a switch, wherein the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube, the drain electrode of the first MOS tube is respectively connected with the source electrode of the third MOS tube and the inverting input end of the second operational amplifier, the drain electrode of the second MOS tube is respectively connected with a battery end and the non-inverting input end of the second operational amplifier, the grid electrode of the first MOS tube is further connected with the grid electrode of the second MOS tube through the switch, the grid electrode of the third MOS tube is connected with the output end of the second operational amplifier, the drain electrode of the third MOS tube is connected with the non-inverting input end of the first MOS tube, the drain electrode of the third MOS tube is further connected with the ground through the first resistor, and the grid electrode of the third MOS tube is connected with the first input end of the USB low-current detection circuit.
As a further improvement of the invention, the USB low-power detection circuit comprises a fourth MOS tube, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, a first AND gate, a second AND gate, a first RS trigger, a first delay unit, a second delay unit, a third delay unit and a power adapter unit, wherein the source of the third MOS tube is connected with the source of the fourth MOS tube, the gate of the third MOS tube is connected with the gate of the fourth MOS tube, the drain of the fourth MOS tube is connected with the ground, the drain of the fourth MOS tube is connected with the input end of the second inverter, the output end of the second inverter is connected with the first input end of the second NAND gate through the second delay unit and the fourth inverter in sequence, the output end of the second inverter is connected with the second input end of the second NAND gate, the output end of the second NAND gate is connected with the first input end of the first NAND gate, the output end of the first inverter sequentially passes through the first delay unit and the third inverter and is further connected with the first input end of the first NAND gate, the output end of the first inverter is connected with the second input end of the first NAND gate, the output end of the first NAND gate is connected with the second input end of the first AND gate, the output end of the first AND gate is connected with the first input end of the power adaptation unit, the output end of the power adaptation unit is connected with the first input end of the second AND gate, the output end of the first RS trigger is connected with the second input end of the second AND gate, and the output end of the second AND gate is respectively connected with the input end of the fifth inverter and the input end of the third delay unit.
As a further improvement of the present invention, the USB low-power detection circuit includes a fifth MOS transistor, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a third nand gate, a fourth nand gate, a third and gate, a fourth and gate, a second RS flip-flop, a fourth delay unit, a fifth delay unit, a sixth delay unit, and a power adapter unit, wherein a source of the fifth MOS transistor is connected to a non-inverting input terminal of the second operational amplifier, a gate of the third MOS transistor is connected to a gate of the fifth MOS transistor, a drain of the fifth MOS transistor is connected to ground, a drain of the fifth MOS transistor is connected to an input terminal of the seventh inverter, an output terminal of the seventh inverter is connected to a first input terminal of the fourth nand gate through the fifth delay unit and the ninth inverter in sequence, the output end of the seventh inverter is connected with the second input end of the fourth nand gate, the output end of the fourth nand gate is connected with the first input end of the third nand gate, the output end of the sixth inverter sequentially passes through the fourth delay unit and the eighth inverter and is further connected with the first input end of the third nand gate, the output end of the sixth inverter is connected with the second input end of the third nand gate, the output end of the third nand gate is connected with the second input end of the third and gate, the output end of the third and gate is connected with the first input end of the power adaptation unit, the output end of the power adaptation unit is connected with the first input end of the fourth and gate, the output end of the second RS trigger is connected with the second input end of the fourth and gate, and the output end of the fourth and gate is respectively connected with the input end of the tenth inverter and the input end of the sixth delay unit.
As a further improvement of the present invention, the first MOS transistor, the second MOS transistor, and the third MOS transistor are all PMOS transistors.
As a further improvement of the present invention, the fourth MOS transistor is a PMOS transistor.
As a further improvement of the present invention, the fifth MOS transistor is a PMOS transistor.
The invention has the beneficial effects that:
the circuit for preventing the battery from flowing backward to the USB can set the USB pull-out detection threshold voltage to be lower than the battery voltage, eliminate the adverse effects of battery leakage and high-frequency oscillation of a charging control system caused by the USB dropping to any voltage, and realize the USB pull-out detection and prevent the high-frequency oscillation by temporarily turning off the charging. And the invention uses T d And starting the first MOS tube for a period, judging whether the USB voltage meets the normal charging requirement, if so, starting charging, and if not, immediately closing charging. During this period, through postponing second MOS pipe turn-on time, effectively prevent that the battery from passing through the second MOS pipe to the USB electric leakage under the short-term circumstances of opening of first MOS pipe to guarantee that there is not the electric leakage all the time in USB extracts or the fall period battery.
Drawings
FIG. 1 is a schematic circuit diagram of an embodiment 1 of a circuit for preventing a battery from flowing backward to a USB according to the present invention;
FIG. 2 is a schematic circuit diagram of embodiment 2 of a circuit for preventing a battery from flowing backward to a USB according to the present invention;
FIG. 3 is a diagram illustrating simulation results of USB dropping below the battery voltage during charging according to the present invention;
FIG. 4 is a schematic diagram of a simulation result of pulling out a USB during constant current charging according to the present invention;
fig. 5 is a schematic block diagram of a system application of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the accompanying drawings:
referring to fig. 1 and2, the circuit for preventing a battery from flowing backward to a USB of the present invention includes a first operational amplifier AMP1, a second operational amplifier AMP2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a first resistor R1, a USB low-current detection circuit, and a switch, wherein an output terminal of the first operational amplifier AMP1 is connected to a gate of the first MOS transistor M1, a source of the first MOS transistor M1 is connected to a source of the second MOS transistor M2, a drain of the first MOS transistor M1 is connected to a source of the third MOS transistor M3 and an inverting input terminal of the second operational amplifier AMP2, a drain of the second MOS transistor M2 is connected to a battery terminal and a non-inverting input terminal of the second operational amplifier AMP2, a gate of the first MOS transistor M1 is connected to a gate of the second MOS transistor M2 through the switch, a gate of the third MOS transistor M3 is connected to an output terminal of the second operational amplifier AMP2, a drain of the third MOS transistor M3 is connected to a non-inverting input terminal of the first MOS transistor M1, and a drain of the third MOS transistor M3 are connected to a non-inverting input terminal of the USB low-current detection circuit through the first operational amplifier AMP2, and a drain of the first MOS transistor M3.
The invention enables the system to exit the state to be charged Td by generating a pulse signal and then restores the state to be charged again. If USB is pulled out, T d And the USB voltage is reduced to be lower than the pull-out detection threshold voltage within the time, and the USB pull-out detection is completed. If the USB is not pulled out, the USB is turned on and the charging is immediately turned off by taking Td as a period during which the USB is less than the battery voltage. By delaying the turn-on time of the charging power tube, the battery is prevented from leaking electricity to the USB within the short turn-on charging time.
In embodiment 1 of the present invention, the USB low-power detection circuit includes a fourth MOS transistor M4, a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a fifth inverter I5, a first NAND gate NAND1, a second NAND gate NAND2, a first AND gate AND1, a second AND gate AND2, a first RS flip-flop, a first delay unit DE1, a second delay unit DE1, a third delay unit DE3, AND a power adapter unit, a source of the third MOS transistor M3 is connected to a source of the fourth MOS transistor M4, a gate of the third MOS transistor M3 is connected to a gate of the fourth MOS transistor M4, a drain of the fourth MOS transistor M4 is connected to ground, a drain of the fourth MOS transistor M4 is connected to an input terminal of the second inverter I2, an output terminal of the second inverter I2 is sequentially connected to the second delay unit DE1 AND the fourth inverter I4, AND further connected to a first input terminal of the second NAND gate 2, the output end of the second inverter I2 is connected with the second input end of the second NAND gate NAND2, the output end of the second NAND gate NAND2 is connected with the first input end of the first AND gate NAND1, the output end of the first inverter I1 is connected with the first input end of the first NAND gate NAND1 sequentially through the first delay unit DE1 AND the third inverter I3, the output end of the first inverter I1 is connected with the second input end of the first NAND gate NAND1, the output end of the first NAND gate NAND1 is connected with the second input end of the first AND gate AND1, the output end of the first AND gate AND1 is connected with the first input end of the power adaptation unit, the output end of the power adaptation unit is connected with the first input end of the second AND gate AND2, the output end of the first RS trigger is connected with the second input end of the second AND gate AND2, the output end of the second AND gate AND2 is respectively connected with the input end of the fifth inverter I5 AND the input end of the third delay unit DE3, the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3 are all PMOS tubes, and the fourth MOS tube M4 is a PMOS tube.
The loop where the first operational amplifier AMP1 is located is used for generating a reference current, and the second operational amplifier AMP2 causes the charging current and the reference current to be in a certain multiple relation by clamping. EN0 is the software enable control signal, ADPT _ IN is the USB insertion detect signal. EN0 and ADPT _ IN both go high with a delay Td (determined by system requirements, suggested to be chosen on the order of seconds) into a state to be charged. The system determines the charging mode to be trickle, constant current, constant voltage or waiting charging according to the battery voltage and the charging current. Under trickle charge conditions, CHG _ CTRL is always high. Under the condition of constant current or constant voltage, when the charging current is lower than a certain threshold value, clearing CHG _ CTRL (charging control signal) through CHG _ OK (full-charge signal), then clearing EN3, stopping charging and entering a state to be charged. When the battery voltage is below a certain threshold, RECHG (recharge signal) restarts charging by setting CHG _ CTRL to 1 and then EN3 to 1.
Wherein EN1 is high level under normal condition, and when V4 or CHG _ CTRL changesAt low, EN1 generates a low pulse. EN2 extends this low level pulse width to Td by a delay. EN3D rising edge is delayed by T compared to EN3 d1 The falling edge is synchronized EN3. Within time Td1
And finishing the judgment of the charging mode according to the sampling current. When EN3D is high level, the switch is connected with GATE to start charging, otherwise, the charging power tube is closed.
Constant current or constant voltage state of charge:
I M4 ＝I M3 ＝I M1 ＝KI M2
where K is the sampling coefficient, IM4 is greater than 0.5uA, V4 and CHG _ CTRL are high. When the USB suddenly drops below the battery voltage, V4 and CHG _ CTRL both go low, EN1 generates a low pulse, EN2 goes low and remains at Td. During this time, if USB is unplugged, ADPT _ IN goes low, USB unplugging detection is complete and EN3 will remain low all the time and exit the pending charge state.
If the USB voltage is just below the battery voltage but the USB is not pulled out, EN3 delays Td to start charging again, CHG _ OK responds immediately, CHG _ CTRL goes low, and EN3 turns off charging since the sampled current is less than the constant voltage charging threshold. Therefore, in this state, EN3 turns on the charge at Td period, and the turn-on time is very short. Since EN3D lags EN3, M2 is always in the off state, there is no leakage.
Trickle charge state:
when the USB is suddenly lower than the battery voltage, V4 changes to low level, EN1 generates a low level pulse, EN2 changes to low level and keeps for a time T d . During this time, if USB is unplugged, ADPT _ IN goes low, the USB unplugging detection is completed, and EN2 will always remain low and exit the state to be charged.
In embodiment 2 of the present invention, the USB low power detection circuit includes a fifth MOS transistor M5, a sixth inverter I6, a seventh inverter I7, an eighth inverter I8, a ninth inverter I9, a tenth inverter I10, a third NAND gate NAND3, a fourth NAND gate NAND4, a third AND gate AND3, a fourth AND gate AND4, a second RS flip-flop, a fourth delay unit DE4, a fifth delay unit DE5, a sixth delay unit DE6, AND a power adapter unit, a source of the fifth MOS transistor M5 is connected to the non-inverting input terminal of the second operational amplifier AMP2, a gate of the third MOS transistor M3 is connected to a gate of the fifth MOS transistor M5, a drain of the fifth MOS transistor M5 is connected to ground, a drain of the fifth MOS transistor M5 is connected to the input terminal of the seventh inverter I7, an output terminal of the seventh inverter I7 is sequentially connected to the first input terminal of the fourth NAND gate 4 through the fifth delay unit DE5 AND the ninth inverter I9, the output end of the seventh inverter I7 is connected to the second input end of the fourth NAND gate NAND4, the output end of the fourth NAND gate NAND4 is connected to the first input end of the third NAND gate NAND3, the output end of the sixth inverter I6 is connected to the first input end of the third NAND gate NAND3 by passing through the fourth delay unit DE4 AND the eighth inverter I8 in sequence, the output end of the sixth inverter I6 is connected to the second input end of the third NAND gate NAND3, the output end of the third NAND gate NAND3 is connected to the second input end of the third AND gate AND3, the output end of the third AND gate AND3 is connected to the first input end of the power adaptation unit, the output end of the power adaptation unit is connected to the first input end of the fourth AND gate 4, the output end of the second RS flip-flop is connected to the second input end of the fourth AND gate 4, AND4 output ends are connected to the input end of the tenth AND gate I10 AND the input end of the sixth delay unit DE6 respectively, the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are all PMOS transistors, and the fifth MOS transistor M5 is a PMOS transistor.
In embodiment 2, since V1 is equal to VBAT in the charging state, the source of the fourth MOS transistor M4 is connected to VBAT, so that the same effects as those in embodiment 1 can be achieved.
Fig. 3 shows that the USB voltage at the chip terminal continuously drops to be smaller than the battery voltage simulation result within the allowable range of the drop amplitude. After the USB is reduced, the EN3 is periodically opened and immediately turned off, the period is Td, and the EN3D lags the EN3, so that the power tube still keeps a closed state during the opening of the EN3, and the battery current does not flow backwards. And after the USB recovers to be normal, the charging management system continues to charge the battery, enters a state to be charged after being fully charged, and turns off the EN3. Fig. 4 shows a simulation result of pulling out the USB during the charging process. And after the USB is pulled out, the EN3 immediately becomes a low level, the charging power tube is closed, the ADPT _ IN becomes a low level, the USB voltage is finally 0, and the USB pull-out detection is completed.
Fig. 5 is a block diagram showing a system application of the design. The system detects USB insertion when the USB voltage is higher than the battery voltage, and USB unplugging when the USB voltage is 90% lower than the battery voltage. When the power consumption on and off the chip is small, the USB voltage is 5V, the Schottky diode drops by 0.5V, the USB \\ \ CHIP voltage is about 4.5V, and the system works normally; at the moment of starting charging or increasing the load in a CHIP, although the USB _ CHIP voltage is suddenly reduced, the voltage is always higher than the battery voltage, so that the system has no risk of false detection of USB pull-out;
when the off-CHIP load suddenly increases, the USB voltage decreases, eventually resulting in a corresponding decrease in the USB _ CHIP voltage. The lowest voltage allowable by USB (the worst case occurs when the lithium battery takes the highest voltage) within the full voltage range of the lithium battery is analyzed as follows:
maximum voltage of the battery: v BAT_MAX ＝4.2V
USB _ CHIP extraction detection voltage: v USB_CHIP_OUT ＝4.2×90％＝3.78V
Corresponding to the USB pull-out detection voltage: v USB_OUT ＝3.78+0.5＝4.25V
Therefore, the system has no risk of USB pull-out false detection before the voltage of the USB terminal is reduced to 4.25V. If the traditional USB control circuit scheme is used, the USB pull-out false detection is inevitable when the USB voltage is less than 4.7V (the maximum voltage of the battery is 4.2V plus the Schottky diode drop is 0.5V).
From the above, the invention can greatly improve the allowed USB dropping amplitude of the charging control system under the condition that the USB pull-out detection threshold voltage is set to be smaller than the battery voltage. When the USB dropping amplitude exceeds the allowable threshold value of the charging control system, the system automatically realizes USB pull-out detection and closes the charging control system. Within the allowable range of the drop amplitude, the USB can not generate the bad effects of USB pull-out false detection, high-frequency oscillation and battery electric leakage in continuous drop and instant drop.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. The utility model provides a prevent that battery from flowing backward current circuit to USB which characterized in that: the low-power detection circuit comprises a first operational amplifier, a second operational amplifier, a first MOS tube, a second MOS tube, a third MOS tube, a first resistor, a USB low-power detection circuit and a switch, wherein the output end of the first operational amplifier is connected with the grid electrode of the first MOS tube, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube, the drain electrode of the first MOS tube is respectively connected with the source electrode of the third MOS tube and the reverse phase input end of the second operational amplifier, the drain electrode of the second MOS tube is respectively connected with a battery end and the in-phase input end of the second operational amplifier, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube through the switch, the grid electrode of the third MOS tube is connected with the output end of the second operational amplifier, the drain electrode of the third MOS tube is connected with the in-phase input end of the first MOS tube, the drain electrode of the third MOS tube is further connected with the ground through the first resistor, and the grid electrode of the third MOS tube is connected with the first input end of the USB low-power detection circuit.
2. The circuit of claim 1, wherein the circuit for preventing the battery from flowing backward to the USB comprises: the USB low-current detection circuit comprises a fourth MOS tube, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, a second NAND gate, a first AND gate, a second AND gate, a first RS trigger, a first delay unit, a second delay unit, a third delay unit and a power supply adaptation unit, wherein the source electrode of the third MOS tube is connected with the source electrode of the fourth MOS tube, the gate electrode of the third MOS tube is connected with the gate electrode of the fourth MOS tube, the drain electrode of the fourth MOS tube is connected with the ground, the drain electrode of the fourth MOS tube is connected with the input end of the second inverter, the output end of the second inverter is connected with the first input end of the second NAND gate through the second delay unit and the fourth inverter in sequence, and the output end of the second inverter is connected with the second input end of the second NAND gate, the output end of the second NAND gate is connected with the first input end of the first NAND gate, the output end of the first inverter is connected with the first input end of the first NAND gate sequentially through the first delay unit and the third inverter, the output end of the first inverter is connected with the second input end of the first NAND gate, the output end of the first NAND gate is connected with the second input end of the first AND gate, the output end of the first AND gate is connected with the first input end of the power adaptation unit, the output end of the power adaptation unit is connected with the first input end of the second AND gate, the output end of the first RS trigger is connected with the second input end of the second AND gate, and the output end of the second AND gate is connected with the input end of the fifth inverter and the input end of the third delay unit respectively.
3. The circuit of claim 1, wherein the circuit for preventing the battery from flowing backward to the USB comprises: the USB low-current detection circuit comprises a fifth MOS tube, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, a third NAND gate, a fourth NAND gate, a third AND gate, a fourth AND gate, a second RS trigger, a fourth delay unit, a fifth delay unit, a sixth delay unit and a power supply adaptation unit, wherein the source electrode of the fifth MOS tube is connected with the non-inverting input end of the second operational amplifier, the gate electrode of the third MOS tube is connected with the gate electrode of the fifth MOS tube, the drain electrode of the fifth MOS tube is connected with the ground, the drain electrode of the fifth MOS tube is connected with the input end of the seventh inverter, the output end of the seventh inverter is connected with the first input end of the fourth NAND gate through the fifth delay unit and the ninth inverter in sequence, the output end of the seventh inverter is connected with the second input end of the fourth NAND gate, the output end of the fourth NAND gate is connected with the first input end of the third NAND gate, the output end of the sixth inverter sequentially passes through the fourth delay unit and the eighth inverter and is further connected with the first input end of the third NAND gate, the output end of the sixth inverter is connected with the second input end of the third NAND gate, the output end of the third NAND gate is connected with the second input end of the third AND gate, the output end of the third AND gate is connected with the first input end of the power adaptation unit, the output end of the power adaptation unit is connected with the first input end of the fourth AND gate, the output end of the second RS trigger is connected with the second input end of the fourth AND gate, and the output end of the fourth AND gate is respectively connected with the input end of the tenth inverter and the input end of the sixth delay unit.
4. The circuit of claim 1, wherein the circuit for preventing the battery from flowing backward to the USB comprises: the first MOS tube, the second MOS tube and the third MOS tube are PMOS tubes.
5. The circuit of claim 2, wherein the circuit for preventing the battery from flowing backward to the USB comprises: the fourth MOS tube is a PMOS tube.
6. The circuit of claim 3, wherein the circuit for preventing the battery from flowing backward to the USB comprises: and the fifth MOS transistor is a PMOS transistor.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101527465A (en) * | 2008-03-06 | 2009-09-09 | 株式会社理光 | Charging control circuit |
| CN103346597A (en) * | 2013-06-25 | 2013-10-09 | 华为技术有限公司 | Charging device |
| CN104092268A (en) * | 2014-07-29 | 2014-10-08 | Tcl通讯（宁波）有限公司 | Circuit for processing pre-charge voltage of battery of mobile terminal |
| CN204068306U (en) * | 2014-06-28 | 2014-12-31 | 青岛歌尔声学科技有限公司 | A kind of charging system of electronic product |
| CN106712207A (en) * | 2017-02-07 | 2017-05-24 | 长春工程学院 | Anti-reverse-connection anti-backflow battery charging protection circuit |
| CN106712199A (en) * | 2017-01-22 | 2017-05-24 | 湖南电将军新能源有限公司 | Over-current protection circuit and method for automobile starting power supply |
| CN207010345U (en) * | 2017-06-14 | 2018-02-13 | 无锡市中健科仪有限公司 | USB power source and the circuit of battery automatic switchover power supply |
| CN108494232A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7525392B2 (en) * | 2006-08-05 | 2009-04-28 | Tang System | XtalClkChip: trimming-free crystal-free precision reference clock oscillator IC chip |
-
2018
- 2018-11-16 CN CN201811366440.3A patent/CN111200302B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101527465A (en) * | 2008-03-06 | 2009-09-09 | 株式会社理光 | Charging control circuit |
| CN103346597A (en) * | 2013-06-25 | 2013-10-09 | 华为技术有限公司 | Charging device |
| CN204068306U (en) * | 2014-06-28 | 2014-12-31 | 青岛歌尔声学科技有限公司 | A kind of charging system of electronic product |
| CN104092268A (en) * | 2014-07-29 | 2014-10-08 | Tcl通讯（宁波）有限公司 | Circuit for processing pre-charge voltage of battery of mobile terminal |
| CN106712199A (en) * | 2017-01-22 | 2017-05-24 | 湖南电将军新能源有限公司 | Over-current protection circuit and method for automobile starting power supply |
| CN106712207A (en) * | 2017-02-07 | 2017-05-24 | 长春工程学院 | Anti-reverse-connection anti-backflow battery charging protection circuit |
| CN207010345U (en) * | 2017-06-14 | 2018-02-13 | 无锡市中健科仪有限公司 | USB power source and the circuit of battery automatic switchover power supply |
| CN108494232A (en) * | 2018-05-07 | 2018-09-04 | 电子科技大学 | A kind of synchronous commutating control circuit for preventing electric current from pouring in down a chimney |
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