CN108490803B

CN108490803B - Test simulation system

Info

Publication number: CN108490803B
Application number: CN201810123822.7A
Authority: CN
Inventors: 吕强; 王淼; 刘涛; 张进武; 郭中甲
Original assignee: Beijing Guodian Science & Technology Co Ltd
Current assignee: Beijing Guodian Science & Technology Co Ltd
Priority date: 2018-02-07
Filing date: 2018-02-07
Publication date: 2020-03-17
Anticipated expiration: 2038-02-07
Also published as: CN108490803A

Abstract

The invention provides a test simulation system, which comprises two CPCI industrial personal computers and CPCI computers, wherein each industrial personal computer is loaded with a universal signal processing platform as a data processing unit, the universal signal processing platforms are connected through a front panel of the CPCI industrial personal computer, a connecting interface comprises a 10MHz system clock output, a 10MHz clock input and a GTH/GTX sending and receiving interface, and each universal signal processing platform is connected with the CPCI computers through a PCI interface chip PLX9054 to convert a PCI bus protocol into a local bus protocol. The invention can change the front-end acquisition and output circuit according to the need, expand the type and quantity of the interface; the system can receive and generate broadband signals, can directly carry out radio frequency band-pass sampling, is more suitable for the requirements of software radio, and can meet the requirements of common measurement and control, communication and radar signal processing algorithms.

Description

Test simulation system

Technical Field

The invention relates to a communication device, in particular to a test simulation system.

Background

The Compact Peripheral Component Interconnect (CPCI) is a bus interface standard proposed by international association of industrial computer manufacturers in 1994, and is a high-performance industrial bus using the PCI electrical specification as a standard. The CPU and peripherals of the CPCI are the same as the standard PCI, and the CPCI system uses the same chips, firewalls and related software as the traditional PCI system. The conversion of a standard PCI card into a CPCI card requires little redesign, as long as it is physically reassigned. In short, the CPCI bus is the electrical specification of the PCI bus + standard pin jack connector (IEC-1076-4-101) + european card specification (IEC297/IEEE 1011.1).

The advent of CPCI not only enables many original PC-based technologies and mature products such as CPUs, hard disks, etc. to be continuously applied, but also enables servers, industrial computers, etc. using CPCI technology to have the advantages of high reliability and high density due to significant improvements in the places such as interfaces, etc. CPCI is a high-performance industrial bus developed based on PCI electrical specifications and is suitable for the design of circuit plugboards with the height of 3U and 6U. The CPCI circuit card is plugged into the cabinet from the front, and the outlet of the I/O data can be an interface on the front panel or the backplane of the cabinet. The CPCI technology is formed by modification on the basis of the PCI technology, and specifically has three aspects: firstly, the PCI local bus technology is continuously adopted; secondly, the PCI traditional mechanical structure is abandoned, and a high-reliability European card structure which is tested in practice for 20 years is used, so that the heat dissipation condition is improved, the vibration and impact resistance is improved, and the electromagnetic compatibility requirement is met; and thirdly, a golden finger type interconnection mode of the PCI is abandoned, and a pin hole connector with the density of 2mm is used instead, so that the gas tightness and the corrosion resistance are realized, the reliability is further improved, and the load capacity is increased. CPCI has hot-pluggable, high openness and high reliability. The most prominent and attractive feature in CPCI technology is hot plugging. In short, it is a technique for pulling out or inserting the function template without destroying the normal operation of the system under the condition that the operation system is not powered off. Hot plugging has been a requirement for telecommunications applications and is also desired for every industrial automation system. The realization is as follows: three pin contact pins with different lengths are adopted structurally, so that when the template is inserted or pulled out, a power supply, a grounding signal, a PCI bus signal and a hot plug starting signal are carried out in sequence; adopting a bus isolation device and soft start of a power supply; in software, the operating system is to have plug and play functionality. The CPCI bus hot plug technology is currently moving from the basic hot-swap technology to high availability.

With diversification of market demands, higher requirements are provided for complex circuit designs, and when specific small function requirements change, resource waste is caused by a circuit board with huge functions and corresponding economic loss is caused. Based on the design of the carrier plate and the FMC daughter card interconnection structure, not only can multiple independent single functions required by a user be realized, but also the limitation on the element area of the daughter card PCB is broken, so that the design work is more flexible, and different requirements of the user are met.

The FMC standard describes a generic module that is targeted to a range of applications, environments and markets. The standard was developed by a consortium of companies, including FPGA vendors and end users, aimed at providing standard daughter card dimensions, connectors and module interfaces for FPGAs on card carriers. By separating the I/O interface from the FPGA in this way, the design of the I/O interface module is simplified, and the repeated utilization rate of the card is maximized. The FMC standard is different from PMC and XMC standards that are connected to a carrier card by using PCI, CPCI, PCI-X, PCI-E, Serial RapidIO or other complex interfaces, and only requires that a core I/O transceiver circuit be directly connected to an FPGA on the carrier card. The design of the FMC sub-modules minimizes design effort and resources by eliminating fixed protocols, minimal system support, and flexible pin assignment. This can improve efficiency and bring significant advantages in design reusability, data throughput, multiple I/O, compatibility, stability, etc.

However, in the prior art in the field of measurement and control or radar communication, the CPCI and the FMC board card are not combined to utilize the two systems or platforms with respective advantages, and the existing test simulation system has the problems that single functions are independent, the element area is limited, diversified requirements cannot be met, and the like.

Disclosure of Invention

In view of the above problems in the prior art, the present invention provides a test simulation system.

The test simulation system selects the design based on the interconnection structure of the CPCI carrier plate and the FMC daughter board, not only can realize various independent single functions required by a user, but also breaks the limitation on the element area of the daughter card PCB, so that the design work is more flexible, and different requirements of the user are met.

The invention adopts a test simulation system, which comprises two CPCI industrial personal computers and CPCI computers, wherein each industrial personal computer is loaded with a universal signal processing platform as a data processing unit, the universal signal processing platforms are connected through a front panel of the CPCI industrial personal computer, a connecting interface comprises a 10MHz system clock output 1 path, a 10MHz clock input 1 path and a GTH/GTX transmitting and receiving interface, and each universal signal processing platform is connected with the CPCI computers through a PCI interface chip PLX9054 to convert a PCI bus protocol into a local bus protocol.

Preferably, the common signal processing platform comprises a CPCI carrier board, the CPCI carrier board comprises a field programmable gate array and two FMC mounting slots, an intermediate frequency FMC daughter board and a high-speed FMC daughter board are respectively mounted on the two FMC slots, and the intermediate frequency FMC daughter board comprises 1 path of intermediate frequency output interface, 2 paths of intermediate frequency input interface, a band-pass filter and an intermediate frequency amplifier; the high-speed FMC daughter board comprises 4 paths of 720M intermediate frequency output interfaces, 2 paths of 720M intermediate frequency input interfaces and a band-pass filter.

Preferably, in the intermediate frequency FMC daughter board, the analog-to-digital converter selects a dual-channel 16-bit ADS42LB69 of TI, and the maximum sampling frequency of the ADS42LB69 is 250MSPS, and the input full amplitude is 2.5 Vpp; the intermediate frequency output interface is suitable for 70M intermediate frequency output and is realized by using a digital-to-analog converter device AD9788, an externally input clock can be multiplied by frequency through an internal PLL to be used as an operating clock, the AD9788 is a digital-to-analog converter with 16-Bit data input, 2/4/8 times of interpolation and filtering can be performed inside the digital-to-analog converter, and the digital-to-analog converter has multiple operating modes.

Preferably, the bandwidth of an input spread-spectrum signal of an intermediate frequency input interface in the high-speed FMC daughter board is 102MHz, the digitization of an input echo signal is realized by adopting a structure of an intermediate frequency quadrature demodulator and an analog-to-digital converter, wherein the intermediate frequency quadrature demodulator selects ADRF6850 of ADI corporation, the ADRF6850 is internally integrated with PLL and VCO capable of fractional frequency division, a local mixing carrier can be internally generated only by providing a frequency reference, a differential carrier is externally input, an analog-to-digital converter chip selects AD9691 of the ADI corporation, the AD9691 is a dual-channel, 14-bit, 1.25GSPS analog-to-digital converter, an on-chip buffer and a sample-and-hold circuit are arranged in the AD9691, a multi-stage and differential pipeline architecture is adopted for a kernel, and output error correction logic is integrated, the AD9691 supports parameter configuration of the AD interface, including programmable gain, sampling offset and the like, and an SPI configuration pin, the field programmable gate array performs working parameter configuration management and state monitoring on the field programmable gate array.

Preferably, an intermediate frequency output port in the high-speed FMC daughter board adopts a structure of an intermediate frequency quadrature demodulator and an analog-digital converter, an AD9144 of ADI company is selected as an output chip of the low-intermediate frequency digital-analog converter, the low-intermediate frequency digital-analog converter is a four-channel, 16-bit and high-dynamic-range digital-analog converter, the highest sampling rate of 2.8GSPS is provided, the input data rate exceeds 1GSPS is supported, the design of low stray and distortion is provided, a dual-DAC (digital-to-analog converter) mode, multi-chip synchronization, fixed delay and data generator delay compensation are supported, a phase-locked loop clock frequency multiplier and a digital anti-sinc filter are built in the low-intermediate frequency digital-analog converter, an SPI (serial peripheral interface) is further provided, the internal parameters are allowed to be programmed and read back, wherein an SPI configuration pin is connected with; the quadrature modulator compatible with AD9144 selects ADI's ADRF6720-27, which internally integrates a fractional PLL and VCO.

Preferably, the CPCI carrier further includes 4 low-speed DA output interfaces, a digital signal processing module, a complex programmable logic device, a synchronous dynamic random access memory, and a clock management chip, wherein the complex programmable logic device is configured to perform online configuration on the field programmable gate array and the digital signal processing module, configure a working clock on the carrier, and connect the external synchronous dynamic random access memory to an EMIF port of the digital signal processing module, wherein the EMIF port is capable of implementing connection between the digital signal processing module and different types of memories, the field programmable gate array is also connected to the EMIF port of the digital signal processing module, so that the digital signal processing module can access internal resources of the field programmable gate array, and the CPCI carrier further includes 32 LVTTL input and output interfaces, and a clock management chip having the same structure, 16 paths of LVDS input and output interfaces with the same structure, 1 path of external 10M clock input and 1 path of 10M clock output.

Preferably, the digital signal processing module is a floating point operation digital signal processing module of TI company, an HPI interface of the digital signal processing module is connected with the complex programmable logic device, two external dynamic random access memories are externally hung on an EMIF interface of the digital signal processing module and are simultaneously connected with a field programmable gate array, a program of the digital signal processing module is configured through the HPI interface, and the HPI interface is directly connected with the complex programmable logic device.

Preferably, the digital signal processing module configures 128M BYTE chips of the synchronous dynamic random access memory, an EMIF interface of the digital signal processing module is connected to an I/O pin of the field programmable gate array for accessing internal resources of the field programmable gate array, the digital signal processing module distinguishes access to the synchronous dynamic random access memory and the field programmable gate array by chip selection signals, and the digital signal processing module is good at processing floating point numbers and completing control of a process with complicated state conversion, and is mainly used for resolving a distance of a ranging processing unit.

Preferably, the FLASH memory is used for storing configuration information of the field programmable gate array and calibration information of the board card, the FLASH memory selects a 64M Bit FLASH memory ST39VF6401, and data in the FLASH memory needs to be updated through a PCI interface during configuration.

Preferably, the complex programmable logic device is configured to perform a decoding operation on a PCI bus and an address bus, and performing local decoding by the complex programmable logic device enables a computer to implement dynamic loading of the field programmable gate array and the digital signal processing module firmware program through the PCI bus, where the complex programmable logic device has its own operating clock.

The test simulation system related by the invention is more advanced in the same type of products, and mainly shows the following aspects:

(1) aiming at different communication systems, the analog circuit at the front end has larger change requirements, the universal signal processing platform is provided with two FMC interfaces, the front end acquisition and output circuit can be replaced as required, and the type and the number of the interfaces are expanded;

(2) the high-speed FMC daughter board front end is from taking the down converter, and the up-down frequency conversion frequency covers L and S wave band, can directly send and receive radio frequency signal in simple application, need not purchase dedicated down converter alone, saves cost and space, and the advantage is obvious. This function is not available on the original platform.

(3) The high-speed acquisition board is provided with high-speed AD and DA, can receive and generate broadband signals, can directly carry out radio frequency band-pass sampling, and is more suitable for the requirements of software radio, and the index is in the front in the existing data processing platform in the current market; the high-performance Vritex 7XC7SX690T FPGA is adopted, the data processing capacity is strong, the front row of the data processing platforms sold in the market at present is enough to meet the requirements of common measurement and control, communication and radar signal processing algorithms.

Drawings

FIG. 1 is a block diagram of a generic signal processing platform in a test simulation system to which the present invention relates;

FIG. 2 is a front-end circuit diagram of ADS42LB69 in a general signal processing platform according to the present invention;

FIG. 3 is a diagram of an upstream output front-end circuit of an intermediate frequency output interface in a general signal processing platform according to the present invention;

FIG. 4 is a circuit diagram of an output driver in a generic signal processing platform to which the present invention relates;

FIG. 5 is a diagram of the AD9788 clock input in a general purpose signal processing platform to which the present invention relates;

fig. 6 is a signal connection reference circuit diagram of a two-channel DAC and analog quadrature modulation in a general signal processing platform according to the present invention.

Detailed Description

In order that those skilled in the art will better understand the technical solutions of the present invention, the following detailed description of the present invention is provided in conjunction with the accompanying drawings and the detailed description thereof.

The embodiment relates to a test simulation system which is generally applied to measurement and control or radar communication signal processing and comprises two CPCI industrial personal computers and CPCI computers, wherein a universal signal processing platform is loaded on each industrial personal computer to serve as a data processing unit, the test simulation system is designed based on the idea of software radio, different programs are loaded to be respectively used as a ground simulator and an on-satellite simulator, and different working modes are realized by loading different algorithm kernels.

The general signal processing platforms are connected through a front panel of the CPCI, the connecting interfaces comprise 1 path of 10MHz system clock output and 1 path of 10MHz clock input, and 7 pairs of GTH/GTX transmitting and receiving interfaces respectively.

Each general signal processing platform is connected with the CPCI computer 2 through a PCI interface chip PLX9054, the PCI bus protocol is converted into a local bus protocol, local bus signals output by the PCI interface chip are subjected to address decoding through the complex programmable logic device 8, the PCI bus finishes access to HPI interfaces of the field programmable gate array 3 and the digital signal processing module 7 through the complex programmable logic device 8, loading of programs of the field programmable gate array 3 and the digital signal processing module 7 is finished, and the computer can finish updating of firmware programs through the PCI interfaces.

For the general signal processing platform, in order to simplify the design and realize better compatibility, the hardware design in the general signal processing platform needs to be considered comprehensively, so that the general signal processing platform can support two devices, namely a ground simulator and an on-satellite simulator, and each device can support an incoherent/bidirectional spread spectrum measurement and control system, a measurement and control data transmission integrated system and a spread spectrum frequency hopping mode, and is completely compatible in a hardware structure. The universal signal processing platform can send intermediate frequency signals, specifically comprises remote control instructions, ranging signals and remote measuring signals, simultaneously receives intermediate frequency signals, specifically comprises remote measuring signals, ranging signals and remote control instructions, and can also generate and receive necessary auxiliary signals.

Further, as shown in fig. 1, the general signal processing platform includes a CPCI carrier board 1 and a CPCI computer 2, the CPCI carrier board 1 includes a Field-Programmable Gate Array (FPGA) 3 and two FMC installation slots, the two FMC slots are respectively installed with an intermediate frequency FMC daughter board 4 capable of implementing 70M input and output and a high-speed FMC daughter board 5 capable of implementing 720M input and output, the intermediate frequency FMC daughter board 4 includes 1 path of intermediate frequency output interface, 2 paths of intermediate frequency input interface, a band pass filter and an intermediate frequency amplifier; the high-speed FMC daughter board 5 comprises a 4-path 720M intermediate frequency output interface, a 2-path 720M intermediate frequency input interface and a band-pass filter. The FMC is an FPGA (field programmable gate array) Mezzanine Card and is a universal module with a wide application range, a wide adaptive environment range and a wide market field range.

As an optimal choice, the type of the Field Programmable Gate Array 3 is selected to be a Vritex 7 platform developed by Xilinx corporation, and the specific type is XC7SX690T which is optimized specially for data processing. The field programmable gate array 3 is configured to complete the access timing control of the peripheral devices; processing the downlink signal is completed, and the remote control signal and the ranging information are demodulated; finishing the generation of uplink signals and generating ranging and remote control analog signals; the acquisition and modulation of low-speed parallel DA input signals are realized; finishing the generation and output of low-speed parallel DA output signals; finishing the generation of the control voltage of the front-end circuit AGC; test PCM signal generation and reception; sending and receiving ranging signals; simulating the Doppler frequency of the transmission signal; and transmitting and receiving data transmission signals.

In order to complete the external configuration of the field programmable gate array 3, hardware maintenance and upgrade of the device can be performed through a PCI interface without opening a chassis, the field programmable gate array 3 can be configured into a slave MAP (complex) configuration mode (CPLD configuration) or a JTAG/Boundary-Scan configuration mode through a jumper, a JTAG/Boundary-Scan mode configuration is used during debugging, a ChipScope tool can be used for debugging the FPGA, and a selectmap (parallel) configuration mode is used after the FPGA program of the device is basically shaped.

In the intermediate frequency FMC daughter board 4, the circuit structure of the intermediate frequency input interface is as shown in fig. 2, wherein the analog-to-digital converter ADC selects a dual-channel 16-bit ADS42LB69 of TI, and the maximum sampling frequency of the ADS42LB69 is 250MSPS, and the input full amplitude is 2.5 Vpp; the circuit structure of the intermediate frequency output interface is shown in fig. 3, which is implemented by using a high-speed digital-to-analog converter device AD9788 of analog devices, and is capable of multiplying an externally input clock by an internal PLL to be used as an operating clock, and applying 70M intermediate frequency output. The AD9788 has a 16-Bit data input digital-to-analog converter, which is internally capable of 2/4/8 times interpolation and filtering, with multiple modes of operation. The AD9788 first interpolates and filters the incoming baseband data, which can then be output directly or after quadrature modulation. The modulated analog output is a current type differential output, the typical value of the output current is 21.4mA, the output current can be set between 8.6mA and 31.6mA, the load is 50 omega impedance, and the passing impedance ratio is 1: 1, the signal is converted into a single-ended signal, the single-ended signal is filtered by a 70MHz passive band-pass filter 7BM65-70/T35, the passive filter uses a band-pass filter which is the same as an uplink intermediate frequency input channel and has insertion loss of 0.9dB, the output of the band-pass filter is subjected to alternating current coupling, the passive filter is driven by an emitter follower circuit and is output after serial matching, and the output of the driving circuit is 50 omega serial matching as shown in figure 4, so that the output signal has attenuation of 6 dB. The required output power is 0dBm to-60 dBm, and the output is 50 omega and is matched in series, so that 6dB of attenuation is brought. Therefore, the output power of the band-pass filter should be 0.9dB attenuation of the output band-pass filter, so the power of the AD9788 output should be 6.9dBm to-53.1 dBm, and the 50 Ω impedance upper current at the maximum output power of 6.9dBm is:

certain redundancy is reserved, the maximum output current of the AD9788 is set to be 30mA, the requirement of outputting the maximum output power of 0dBm can be met,

the current on the 50 Ω impedance for 53.1dBm is:

when the maximum output current is 30mA, the DA bit width required to output-59.1 dBm of power over a 50 Ω impedance is:

n is a natural number, and can be obtained by derivation:

by using a 12-Bit representation of the modulation signal by the DAC (loss of 4-Bit resolution), a sufficient resolution representation of the modulation signal can be provided without causing a problem of significant degradation of signal quality.

Therefore, the AD9788 can meet the requirement that the output power can be set between 0dBm and-60 dBm in the technical requirement.

The minimum resolution of the AD9788 output is:

the minimum resolution of the AD9788 output is much less than the requirement that the output power be adjustable in 1dB steps. The reference clock of the AD9788 is input differentially, and its interface form is shown in fig. 5.

In the high-speed FMC daughter board 5, for a high-speed intermediate-frequency input interface, the bandwidth of an input spread-spectrum signal is 102MHz according to the technical requirements. The design realization difficulty of the radio frequency down-conversion unit and the requirement of intermediate frequency signal sampling are comprehensively considered, and the design structure of the intermediate frequency quadrature demodulator and the high-speed analog-to-digital converter is adopted to realize the digitization of the input echo signal. The intermediate frequency quadrature demodulator selects adif 6850 by ADI for design constraints. The quadrature demodulator internally integrates PLL and VCO capable of dividing frequency by decimal number, and local mixing carrier can be generated internally only by providing frequency reference; a differential carrier having a more preferable phase noise characteristic can be inputted from the outside. RF input frequency range of ADRF 6850: 100MHz to 1000MHz, with LO output interface, capable of integrating fractional-N PLL and VCO, input P1dB of 12dBm (0dB gain), input IP3 of 22.5dBm (0dB gain), noise figure of 11dB, programmable HD3/IP3 adjustment, baseband 1dB bandwidth of 250MHz (wideband mode) and 50MHz (narrowband mode). Meanwhile, a high-speed analog-to-digital converter is adopted to collect 720M input signals, and an analog-to-digital converter chip selects AD9691 of ADI company. AD9691 is a dual channel, 14 bit, 1.25GSPS analog to digital converter. The device is internally provided with an on-chip buffer and a sampling hold circuit, and the dual-channel analog-to-digital converter kernel adopts a multi-stage and differential pipeline architecture and integrates output error correction logic. Each ADC has a wide bandwidth input, supporting IF signal sampling up to 1.5 GHz. The main characteristics include realization of JESD204B encoded serial digital output, total power consumption per channel of 1.9W, SFDR 77dBFS (340MHz), signal-to-noise ratio (SNR) 63.4dBFS (340MHz, AIN-1.0 dBFS), noise density-152.6 dBFS/Hz, dc power supply with 1.25V, 2.50V and 3.3V, 1.58V p-p differential full-scale input voltage, flexible termination impedance of 400 Ω, 200 Ω, 100 Ω and 50 Ω differential, 1.5GHz available analog input full power bandwidth and 95dB channel isolation/crosstalk.

AD9691 supports parameter configuration thereof through the SPI interface, including programmable gain, sample offset, etc. And the SPI configuration pin is connected with the FPGA, and the FPGA performs working parameter configuration management and state monitoring on the SPI configuration pin.

For the high-speed intermediate frequency output port in the high-speed FMC daughter board 5, because the required output intermediate frequency is high, if the direct output mode of the high-speed digital-to-analog converter is adopted to realize the high-speed intermediate frequency output port, the technical difficulty and risk are high, and the type selection of components is also greatly limited. Therefore, the technical measure adopted in the scheme is to output the signal to an appropriate low intermediate frequency fIF0 by using a digital-to-analog converter, and then convert the low intermediate frequency signal to the required intermediate frequency point by using a quadrature modulator. The signal links are as follows:

considering that the system has a distance measurement function, when the radio frequency closed loop works, in order to avoid generating phase errors in the sending process, an output intermediate frequency point consistent with an input intermediate frequency signal is considered, namely 2 paths of 1.5GHz intermediate frequency signals are output to the radio frequency subsystem. For the direct play mode, when a 600MHz intermediate frequency signal needs to be directly output, only the local oscillation frequency of the quadrature modulator needs to be changed.

The low-intermediate frequency digital-to-analog converter output chip selects AD9144 of ADI company. AD9144 is a four-channel, 16-bit, high dynamic range digital-to-analog converter that provides the 2.8GSPS maximum sampling rate. The digital to analog converter output is optimized to seamlessly interface with the ADRF672x analog quadrature modulator from ADI. The digital phase-locked loop clock frequency multiplier supports an input data rate exceeding 1GSPS, is specially designed with low spurious and distortion, has an 8-channel JESD204B interface when SFDR is 82dBc (DC IF and 9 dBFS), supports a double DAC mode (2.8 GSPS), supports multi-chip synchronization, fixed delay and data generator delay compensation, can select a 1x interpolation filter, a 2x interpolation filter, a 4x interpolation filter and an 8x interpolation filter, has an input signal power detection function, is used for protecting an emergency braking function of a downstream analog circuit, is internally provided with a high-performance and low-noise phase-locked loop clock frequency multiplier, is internally provided with a digital anti-sinc filter, and has low power consumption, specifically 1.6W (1.6GSPS) and 1.7W (2.0 GSPS).

In addition, AD9144 provides an SPI interface, allowing for programming and readback of internal parameters. The SPI configuration pin is connected to XC6SLX100 of the field programmable gate array 3, and the field programmable gate array 3 performs configuration management of operating parameters and status monitoring.

The quadrature modulator associated with AD9144 selects adif 6720-27 from ADI corporation. The ADRF6720-27 internally integrates a fractional-N PLL and a VCO, so that a separate VCO device is not required to be additionally configured, and only a frequency reference signal is required to be provided. The main performance parameters of ADRF6720-27 include: the RF output frequency range is 400MHz to 3000MHz, the internal LO frequency range is 356.25MHz to 2855MHz, output P1dB is 10.8dBm (2140MHz), output IP3 is 31.1dBm (2140MHz), the carrier feed-through is-44.3 dBm (2140MHz), the sideband suppression is-40.8 dBc (2,140MHz), the noise floor is-159.5 dBm/Hz (2140MHz), the baseband 1dB modulation bandwidth is >1000MHz, the baseband input bias level is 2.68V, the power supply is 3.3V/425mA, and the integrated RF tunable balun allows for single ended RF output, has multi-core integrated VCO and HD3/IP3 optimization, has sideband suppression and carrier feed-through optimization.

When the device works in the acquisition playback mode or the real-time convolution playback mode, the input and output intermediate frequency of the simulator are both 1.5Ghz, and the intermediate frequency demodulator and the intermediate frequency modulator are ensured to adopt the same local oscillation signal. The approach taken in this design is to have intermediate frequency modulators ADRF6720-27 operating in internal local oscillation mode, generate the required local oscillation signal according to the input system frequency reference, and output to intermediate frequency demodulator ADRF6820, and ADRF6820 operating in external local oscillation mode.

Both AD9144 and ADRF6720-27 provide SPI interfaces, allowing for programming and readback of internal parameters. The SPI configuration pin is connected to the field programmable gate array 31XC6SLX100, and is subjected to the configuration management of the operating parameters and the state monitoring by the field programmable gate array 3. The reference connection circuit for AD9122 and ADRF6720-27 is shown in fig. 6:

in addition, the CPCI carrier 1 further comprises 4 low-speed DA output interfaces 6, and the CPCI carrier 1 further comprises a digital signal processing module 7(DSP), a complex programmable Logic Device 8(complex programmable Logic Device, CPLD), a synchronous dynamic random access memory 9(SDRAM), and a clock management chip 10, in addition to the field programmable gate array 3, wherein the complex programmable Logic Device 8 is used for configuring the field programmable gate array 3 and the digital signal processing module 7 online, configuring the working clock on the carrier, and connecting the external synchronous dynamic random access memory 9(SDRAM) to the EMIF port of the digital signal processing module 7, wherein the EMIF interface can realize the connection between the digital signal processing module 7 and different types of memories (SRAM, Flash RAM, DDR-RAM, etc.), and in addition, the field programmable gate array 3 is also connected to the EMIF port of the digital signal processing module 7, so that the digital signal processing module 7 has access to the internal resources of the field programmable gate array 3.

In addition, the general signal processing platform also includes 32 configured LVTTL input/output interfaces (the number of customized back boards can be expanded) configured to monitor PCM data and clock outputs, PCM clock and data inputs during external PCM modulation, and also used as inputs of external remote control signals, and test signals, such as: pulse per second signal, lock model, I, Q test signal, etc. In order to process high-speed PCM signals, the general signal processing platform also comprises 16 paths of LVDS input and output interfaces with the same structure (the number of customized back boards can be expanded), and the interfaces are mainly used for inputting high-speed data and clocks.

The general signal processing platform also comprises 1 path of external 10M clock input and 1 path of 10M clock output, one path of 10.23M clock input and clock output, the AD, the DA and the FPGA can work in one of the two systems in a programmable mode (the clock can be configured into other frequency points if necessary), the input clock can automatically select to use the external clock or the clock carried by the board according to the set priority, and can also select to use the clock input by the external clock or the clock carried by the board card as the clock source of the system through software control.

The digital signal processing module 7 is a floating point operation digital signal processing module of TI company, the HPI interface of the digital signal processing module 7 is connected with the complex programmable logic device 8, the digital signal processing module 7 is preferably a TMS320C6747 chip, two external EEPRAMs are externally hung on the EMIF port of the digital signal processing module 7 and are used for internal expansion of the digital signal processing module 7, the EMIF port of the digital signal processing module 7 is simultaneously connected with the field programmable gate array 3 and is used for data exchange with the field programmable gate array 3, the program of the digital signal processing module 7 is configured through the HPI port, the HPI port is directly connected with the complex programmable logic device 8 and is decoded through the complex programmable logic device 8, so that the configuration of the digital signal processing module 7 does not need to be transferred through the field programmable gate array 3, but the digital signal processing module 7 wants to normally work, the configuration of the field programmable gate array 3 needs to be completed first, because the clock of the digital signal processing module 7 is provided by the field programmable gate array 3, so that the computer can update the program of the digital signal processing module 7 through the PCI interface, complete the dynamic loading of the program of the digital signal processing module 7, in order to increase the processing capacity of the digital signal processing module 7, the digital signal processing module 7 is provided with a 128M BYTE off-chip synchronous dynamic random access memory 9, the synchronous dynamic random access memory 9 is connected to the EMIF interface of the digital signal processing module 7, while the EMIF interface of the digital signal processing module 7 is connected to the I/O pins of the field programmable gate array 3, for accessing the internal resources of the field programmable gate array 3, the access of the digital signal processing module 7 to the synchronous dynamic random access memory 9 and the field programmable gate array 3 is distinguished by chip selection signals. The digital signal processing module 7 is good at processing floating point numbers and completing control of a process with more complex state conversion, and is mainly used for resolving the distance of the ranging processing unit.

The signal processing platform also comprises a FLASH memory 11 for storing the configuration information of the field programmable gate array 3 and the calibration information of the board card, and the FLASH memory 11 is a 64M Bit FLASH memory-ST 39VF 6401. The data in the FLASH can be updated through the PCI interface when the configuration is carried out.

In order to realize data exchange with a computer, PLX9054 is used as a PCI interface chip to complete the conversion between the PCI bus protocol and the local bus protocol. PLX9054 supports a 32-bit data bus, DMA operations, and hardware interrupts. The method has high data reading and writing speed and can meet the data exchange requirement of ground test equipment.

The complex programmable logic device 8(CPLD) is configured and used for decoding operations such as a PCI bus and an address bus, and the purpose of using the complex programmable logic device 8 for local decoding is to enable a computer to realize dynamic loading of firmware programs of the field programmable gate array 3 and the digital signal processing module 7 through the PCI bus, so that the upgrading of hardware of the equipment and the switching of working modes can update the configuration programs of the hardware in a PCI bus loading mode, and the upgrading of the equipment can be completed without opening a case. In addition, the complex programmable logic device 8 is also configured to complete access and initialization of the clock management chip, the clock of the system needs to work normally, and the correct clock can be output only after the correct configuration, the complex programmable logic device 8 has a working clock of itself, the configuration can be completed by electrifying, the clock management chip is configured through the complex programmable logic device 8, and the system can work normally after the system clock works normally; the complex programmable logic device 8 also needs to complete the reading and writing of the registers inside the field programmable gate array 3.

While there has been described what are believed to be the preferred embodiments of the present invention, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the principles of the invention, and it is intended to cover all such changes and modifications as fall within the true scope of the invention.

Claims

1. A test simulation system comprises two CPCI industrial personal computers and CPCI computers (2), wherein each industrial personal computer is loaded with a universal signal processing platform as a data processing unit, the universal signal processing platforms are connected through a front panel of the CPCI industrial personal computer, a connecting interface comprises a 10MHz system clock output 1 path, a 10MHz clock input 1 path and a GTH/GTX sending and receiving interface, and each universal signal processing platform is connected with the CPCI computers (2) through a PCI interface chip PLX9054 to convert a PCI bus protocol into a local bus protocol;

the general signal processing platform comprises a CPCI (compact peripheral component interconnect) support plate (1), the CPCI support plate (1) comprises a field programmable gate array (3) and two FMC installation groove positions, an intermediate frequency FMC sub-plate (4) and a high-speed FMC sub-plate (5) are respectively installed on the two FMC groove positions, and the intermediate frequency FMC sub-plate (4) comprises 1 path of intermediate frequency output interface, 2 paths of intermediate frequency input interfaces, a band-pass filter and an intermediate frequency amplifier; the high-speed FMC daughter board (5) comprises 4 paths of 720M intermediate frequency output interfaces, 2 paths of 720M intermediate frequency input interfaces and a band-pass filter;

in the intermediate frequency FMC daughter board (4), a dual-channel 16-bit ADS42LB69 of TI is selected as an analog-to-digital converter, and the maximum sampling frequency of the ADS42LB69 is 250MSPS, and the input full amplitude is 2.5 Vpp; the intermediate frequency output interface is suitable for 70M intermediate frequency output and is realized by using a digital-to-analog converter device AD9788, an externally input clock can be used as an operating clock after being multiplied by frequency through an internal PLL, the AD9788 is a digital-to-analog converter with 16Bit data input, 2/4/8 times of interpolation and filtering can be performed inside the digital-to-analog converter, and the digital-to-analog converter has multiple operating modes;

the bandwidth of an input spread-spectrum signal of an intermediate frequency input interface in the high-speed FMC daughter board (5) is 102MHz, it adopts the structure of intermediate frequency quadrature demodulator and analog-digital converter to implement digitization of input echo signal, wherein, the intermediate frequency quadrature demodulator selects ADRF6850 of ADI company, which integrates PLL and VCO capable of fractional division internally, only provides frequency reference to generate local mixing carrier internally, inputs differential carrier from outside, the AD9691 of ADI company is selected by the analog-to-digital converter chip, it is a dual-channel, 14-bit, 1.25GSPS analog-to-digital converter, in which an on-chip buffer and a sample-and-hold circuit are built, the kernel adopts a multi-stage, differential pipeline architecture, the AD9691 supports parameter configuration through an SPI interface, an SPI configuration pin is connected with a field programmable gate array (3), and the field programmable gate array (3) performs working parameter configuration management and state monitoring on the SPI configuration pin;

an intermediate frequency output port in the high-speed FMC daughter board (5) adopts a structure of an intermediate frequency quadrature demodulator and an analog-digital converter, an AD9144 of ADI company is selected as an output chip of the low-intermediate frequency digital-analog converter, the low-intermediate frequency digital-analog converter is a four-channel, 16-bit and high-dynamic-range digital-analog converter, the highest sampling rate of 2.8GSPS is provided, the input data rate exceeds 1GSPS is supported, the low-intermediate frequency digital-analog converter has low stray and distortion design, a double-DAC (digital-to-analog converter) mode, multi-chip synchronization, fixed delay and data generator delay compensation are supported, a phase-locked loop clock frequency multiplier and a digital anti-sinc filter are built in the low-intermediate frequency digital-analog converter, an SPI (serial peripheral) interface is also provided, and internal parameters are allowed to be programmed and read back, wherein an SPI configuration pin is connected; the quadrature modulator matched with AD9144 selects ADRF6720-27 of ADI company, which integrates fractional PLL and VCO inside;

the CPCI carrier board (1) further comprises a 4-way low-speed DA output interface (6), a digital signal processing module (7), a complex programmable logic device (8), a synchronous dynamic random access memory (9) and a clock management chip (10), wherein the complex programmable logic device (8) is used for carrying out online configuration on the field programmable gate array (3) and the digital signal processing module (7), carrying out on-board working clock configuration and connecting the external synchronous dynamic random access memory (9) to an EMIF interface of the digital signal processing module (7), the EMIF interface can realize the connection of the digital signal processing module (7) and different types of memories, the field programmable gate array (3) is also connected to the EMIF interface of the digital signal processing module (7) so that the digital signal processing module (7) can access internal resources of the field programmable gate array (3), the LVTTL circuit also comprises 32 paths of LVTTL input and output interfaces with the same structure, 16 paths of LVDS input and output interfaces with the same structure, 1 path of external 10M clock input and 1 path of 10M clock output.

2. The test simulation system according to claim 1, wherein the digital signal processing module (7) is a floating point arithmetic digital signal processing module of TI company, an HPI interface of the digital signal processing module is connected with the complex programmable logic device (8), two external dynamic random access memories (9) are externally hung on an EMIF interface of the digital signal processing module (7) and are simultaneously connected with the field programmable gate array (3), a program of the digital signal processing module (7) is configured through the HPI interface, and the HPI interface is directly connected with the complex programmable logic device (8).

3. The test simulation system according to claim 2, wherein the digital signal processing module (7) configures 128M BYTE chips of the SDRAM (9), and an EMIF interface of the digital signal processing module (7) is connected to an I/O pin of the FPGA (3) for accessing internal resources of the FPGA (3), the access of the SDRAM (9) and the FPGA (3) by the digital signal processing module (7) is differentiated by chip selection signals, and the digital signal processing module (7) is good at processing floating point numbers and performing control of a process with more complex state transition for resolving a distance of a ranging processing unit.

4. The test simulation system of claim 3, further comprising a FLASH memory (11) for storing configuration information of the field programmable gate array (3) and calibration information of the board, wherein the FLASH memory (11) is a 64M Bit FLASH memory ST39VF6401, and data in the FLASH memory needs to be updated through the PCI interface during configuration.

5. The test simulation system according to claim 3, wherein the complex programmable logic device (8) is configured to perform a decoding operation on a PCI bus and an address bus, wherein the local decoding by the complex programmable logic device (8) enables a computer to realize dynamic loading of the field programmable gate array (3) and the firmware program of the digital signal processing module (7) through the PCI bus, and the complex programmable logic device (8) has its own operating clock.