CN114598348B - Universal hardware platform for short wave communication technology verification and signal processing method thereof - Google Patents
Universal hardware platform for short wave communication technology verification and signal processing method thereof Download PDFInfo
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Abstract
The invention provides a short-wave communication technology verification universal hardware platform and a signal processing method thereof, wherein the short-wave communication technology verification universal hardware platform comprises a channel unit, a service unit, a main control unit and a switching chip unit SW; the exchange chip unit SW is used for signal transmission among the channel unit, the service unit and the main control unit; the channel unit is used for receiving and transmitting radio frequency signals; the service unit is used for modulating and demodulating the digital baseband signal; the system-on-chip SOC module of the main control unit comprises a processing system PS submodule and a programmable logic PL submodule, wherein the processing system PS submodule is used for controlling the channel unit and the service unit, and the programmable logic PL submodule is used for processing the digital baseband signals and managing an external interface of the main control unit. The device of the invention selects a chip with high main frequency and large resources, adopts internal single interface high-speed serial bus SRIO connection, and solves the problems of reliability reduction and the like caused by the fact that the existing radio platform does not support the development of new technology and too many interfaces.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a general hardware platform for short wave communication technology verification and a signal processing method thereof.
Background
With the continuous development of communication technology, in recent years, the field of short-wave communication has emerged a plurality of new technologies, such as short-wave broadband, universal-path receiving, autonomous frequency selection, and the like. Meanwhile, the requirements of new technology on hardware platforms are higher and higher, and the original hardware platform of a short-wave radio station can not meet the requirements of the new technology on resources, so that the development of a general-purpose and standardized hardware platform with comprehensive functions, sufficient resources and rich interfaces is also urgent.
Currently, the existing short-wave radio station core processing unit comprises a service unit, a channel unit and a main control unit, wherein the service unit adopts a digital signal processor DSP+field programmable gate array FPGA architecture, the channel unit adopts a field programmable gate array FPGA+AD/DA architecture, and the main control unit adopts an ARM+peripheral interface chip architecture. Table 1 shows the main components of the core processing unit of the conventional short-wave radio station.
The service unit mainly completes the functional service of the active system such as the modulation and demodulation of radio station data and voice, frequency fixing, automatic control communication, frequency hopping and the like; the channel unit mainly realizes radio frequency digitization of signals, namely, baseband modulation signals from the service unit are converted into radio frequency signals and then sent out, or received single-channel radio frequency signals are converted into baseband signals and then sent to the service unit for demodulation; the main control unit mainly completes the control of the units such as business, channel, power amplifier, antenna tuning, filter and the like, and the management of the external interfaces of the radio station.
Table 1 main device of core processing unit of existing shortwave radio station
When receiving signals, the radio station receives radio frequency signals through the antenna and sends the radio frequency signals to the channel unit through the power amplifier and the filter. The radio frequency front end in the channel unit comprises attenuation, amplification, low-pass filtering and the like, the signal amplitude is adjusted to be within the input range of the analog-to-digital converter ADC, and then one path of signal is changed into two paths of differential signals through a transformer and is sent to the analog-to-digital converter ADC. The analog-digital converter ADC directly samples and digitizes the radio frequency signal at 73.728MSPS sampling rate, and outputs the parallel data with 16bit width, then the parallel data is digitally mixed with the direct digital frequency synthesis DDS signal generated by the control of the channel unit FPGA, the data rate is reduced from 73.728MHz to the baseband rate of 8KHz, the total extraction multiple is 9216, thereby converting the radio frequency signal to the baseband signal, finally the radio frequency signal is sent to the FPGA module of the field programmable gate array of the service unit through the multichannel buffer serial interface MCBSP, the FP FPGA module is sent to the DSP through the external memory interface EMIF for digital signal demodulation processing, the demodulated baseband data is sent to the audio DAC through the serial peripheral interface SPI for conversion into the analog audio signal to be sent to the audio unit, and the analog audio signal is sent to the audio interface of the radio station after audio amplification, and the voice can be heard by the external earphone microphone set.
When signals are transmitted, voice analog signals generated by the earphone microphone set are transmitted to an audio ADC of a service unit after passing through a radio station audio unit, the audio ADC converts the analog signals into digital signals at a sampling rate of 8K, the digital signals are transmitted to a digital signal processor DSP for modulation processing through a serial peripheral interface SPI, the modulated data are transmitted to a field programmable gate array FPGA module through an external memory interface EMIF, the field programmable gate array FPGA module is transmitted to a channel unit for up-conversion processing through a multichannel buffer serial interface MCBSP interface, the data rate is moved to 73.728Mb from 8Kb, then the frequency is moved to radio frequency after being mixed with direct digital frequency synthesis DDS signals generated by the channel unit field programmable gate array FPGA module, the radio frequency is converted into radio frequency analog signals through a radio frequency DAC, the radio frequency analog signals are amplified and filtered through the front end of the channel unit, and finally the radio frequency is transmitted through a power amplifier and an antenna. Table 2 shows the main interface relationships between the internal units or the inter-unit units of the core processing unit of the conventional short-wave radio station.
TABLE 2 Main interface relationships within or among core processing units of existing shortwave radio
In the prior art, the service, the channel and the main control are divided into three independent units so as to facilitate debugging and problem investigation, but the resources of main devices are smaller, the integration level is not high, the interfaces among the units are more, the reliability is lower, and the problems in actual production are more.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention aims to provide a short wave communication technology verification universal hardware platform, which integrates a service unit, a channel unit and a main control unit, wherein a chip with higher main frequency and larger resource is selected as a main device, and an internal single interface high-speed serial bus SRIO is adopted for connection, so that the aim of solving the problems that the existing radio platform does not support the development of new technology and the reliability is reduced due to too many interfaces is fulfilled.
In order to achieve the above purpose, the present invention is realized by the following technical scheme.
The invention relates to a short wave communication technology verification universal hardware platform, which comprises a channel unit, a service unit, a main control unit and a switching chip unit SW;
the exchange chip unit SW comprises a high-speed serial bus SRIO exchange chip, and the high-speed serial bus SRIO exchange chip is respectively connected with the channel unit, the service unit and the main control unit through the high-speed serial bus SRIO and is used for signal transmission among the channel unit, the service unit and the main control unit.
The channel unit comprises a Field Programmable Gate Array (FPGA) module, a radio frequency front end module and a digital-to-analog conversion module;
the channel unit is used for mixing the received radio frequency signals with direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module after the radio frequency front end module processing and the analog-to-digital conversion module processing, and the field programmable gate array FPGA module performs down-conversion on the mixed signals to output digital baseband signals, and finally sends the digital baseband signals to the service unit through the exchange chip unit SW;
the channel unit is also used for carrying out digital up-conversion processing on the digital baseband signals input by the service unit through the exchange chip unit SW through the field programmable gate array FPGA module, then carrying out frequency mixing on the digital baseband signals and the direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module, processing the mixed digital signals through the analog-to-digital conversion module, outputting radio frequency signals, and processing the radio frequency signals through the radio frequency front end module and then sending the radio frequency signals.
The business unit comprises a Digital Signal Processor (DSP) module; the service unit is used for demodulating the digital baseband signal sent by the channel unit through the exchange chip unit SW, and sending the demodulated digital baseband signal to the main control unit through the exchange chip unit SW by the high-speed serial bus SRIO interface; the service unit is also used for modulating the digital baseband signal sent by the main control unit through the exchange chip unit SW, and sending the modulated digital baseband signal into the channel unit through the exchange chip unit SW through the high-speed serial bus SRIO interface.
The main control unit comprises a system-on-chip SOC module, and the system-on-chip SOC module is provided with an external interface; the main control unit configures a switching chip unit SW through an integrated circuit bus I2C; the main control unit is used for controlling the channel unit and the service unit and processing the digital baseband signal sent by the service unit through the exchange chip unit SW; the main control unit is also used for receiving and analyzing the instruction input by the external interface of the system on chip SOC module, and then sending the analyzed instruction to the service unit through the exchange chip unit SW.
The system-on-chip SOC module comprises a processing system PS submodule and a programmable logic PL submodule, wherein the processing system PS submodule is used for controlling the channel unit and the service unit, and the programmable logic PL submodule is used for processing the digital baseband signals and managing an external interface of the main control unit.
Preferably, in the channel unit, the digital-to-analog conversion module comprises a digital-to-analog converter DAC and an analog-to-digital converter ADC;
preferably, in the channel unit, the radio frequency front end module includes a radio frequency receiving front end module and a radio frequency transmitting front end module; wherein: the radio frequency receiving front-end processing module comprises a band-pass filter, an adjustable attenuator and a fixed amplifier, radio frequency signals are filtered by the band-pass filter and sequentially pass through the adjustable attenuator and the fixed amplifier, and after the signal amplitude is adjusted, the radio frequency signals enter the digital-to-analog conversion module;
the radio frequency transmission front-end processing module comprises a band-pass filter, an adjustable amplifier and a band filter; the radio frequency signals sent by the digital-to-analog conversion module sequentially pass through a band-pass filter, an adjustable amplifier and a band filter, and the processed radio frequency signals are transmitted.
Preferably, in the main control unit, an external interface of the SOC module includes: the device comprises an audio interface, a data interface, a display interface, a tone interface and a power amplifier interface.
Preferably, the specific steps of the programmable logic PL submodule for managing the external interface of the main control unit are as follows:
the audio interface is managed through a serial peripheral interface SPI, and the data interface, the display interface, the antenna tuning interface and the power amplifier interface are managed through an asynchronous receiving and transmitting transmitter UART.
Preferably, the short wave communication technology verification universal hardware platform further comprises a clock management unit.
Preferably, the short-wave communication technology verification universal hardware platform further comprises a power management unit.
The invention discloses a signal processing method for verifying a general hardware platform based on a short-wave communication technology, which comprises the following three processing steps:
(1) A received signal processing step: the radio frequency signal is processed by a radio frequency receiving front-end module of a channel unit, the processed radio frequency signal is sent to an analog-to-digital converter ADC for direct sampling and digitizing, and then is subjected to digital mixing down-conversion with a direct digital frequency synthesis DDS signal of a field programmable gate array FPGA module, and a digital baseband signal is output; the digital baseband signal is sent into a Digital Signal Processor (DSP) module of a service unit through a high-speed serial bus (SRIO) for demodulation, the demodulated digital baseband signal is sent into a system-on-chip (SOC) module of a main control unit through a switching chip unit (SW) through the high-speed serial bus (SRIO), and the SOC module sends the digital baseband signal into an external interface through a Serial Peripheral Interface (SPI) or an asynchronous transceiver transmitter (UART);
(2) A transmission signal processing step: the digital baseband signal is sent to the system on chip SOC module of the main control unit through the external interface of the system on chip SOC module, then sent to the digital signal processor DSP module of the service unit through the high-speed serial bus SRIO interface by the exchange chip unit SW to be modulated, the modulated digital baseband signal is sent to the field programmable gate array FPGA module of the channel unit through the high-speed serial bus SRIO interface to be subjected to digital up-conversion processing to output a digital signal; mixing the digital signal with a direct digital frequency synthesis DDS signal generated by a field programmable gate array FPGA module, converting the mixed digital signal into a radio frequency signal through a digital-to-analog converter DAC, and transmitting the radio frequency signal through a radio frequency transmitting front-end module;
(3) The signal processing step of the main control part: the main control part digital signals comprise control signals and feedback signals, wherein the control signals are issued to a System On Chip (SOC) module of the main control unit through an external interface of the SOC module, the control signals are received by a Programmable Logic (PL) sub-module in the SOC module and forwarded to a Processing System (PS) sub-module, and the processing system PS sub-module finishes analysis of the control signals; the feedback signal is issued to the system on chip SOC module of the main control unit through an external interface of the system on chip SOC module, the programmable logic PL submodule in the system on chip SOC module receives the feedback signal and forwards the feedback signal to the processing system PS submodule, and the processing system PS submodule finishes analysis of the feedback signal.
Preferably, in the step of processing the received signal, the sampling rate of the analog-to-digital converter ADC is 100MSPS.
Preferably, in the step of processing the received signal, the total decimation factor of the frequency mixing down-conversion is 12500.
Compared with the prior art, the invention has the following advantages:
(1) The hardware platform is highly integrated in design, and the functions are more comprehensive;
(2) The high-speed processor and the ultra-large resource capacity effectively support the development of new research technology;
(3) The design of the single interface among the core devices solves the problem of reliability reduction caused by excessive interfaces in the prior art.
Drawings
The invention will now be described in further detail with reference to the drawings and to specific examples.
FIG. 1 is a functional block diagram of a generic hardware platform of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only for illustrating the present invention and should not be construed as limiting the scope of the present invention.
The short-wave communication technology verifies that the universal hardware platform can realize full-digital processing from a short-wave baseband signal to a radio frequency signal or from a radio frequency signal to a baseband signal. Radio frequency digitization belongs to the software radio SDR category, and the essence of the software radio technology is that ADC/DAC is close to the radio frequency antenna end, so that the signal processing part is performed in the digital domain as soon as possible, and the flexibility and upgrading capability of a radio station are improved to the greatest extent.
Referring to fig. 1, a schematic block diagram of a communication module according to the present invention is shown. The invention relates to a short wave communication technology verification universal hardware platform, which comprises a channel unit, a service unit, a main control unit and a switching chip unit SW;
the exchange chip unit SW comprises a high-speed serial bus SRIO exchange chip, and the high-speed serial bus SRIO exchange chip is respectively connected with the channel unit, the service unit and the main control unit through the high-speed serial bus SRIO and is used for signal transmission among the channel unit, the service unit and the main control unit.
The channel unit comprises a Field Programmable Gate Array (FPGA) module, a radio frequency front end module and a digital-to-analog conversion module;
the channel unit is used for mixing the received radio frequency signals with direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module after the radio frequency front end module processing and the analog-to-digital conversion module processing, and the field programmable gate array FPGA module performs down-conversion on the mixed signals to output digital baseband signals, and finally sends the digital baseband signals to the service unit through the exchange chip unit SW;
the channel unit is also used for carrying out digital up-conversion processing on the digital baseband signals input by the service unit through the exchange chip unit SW through the field programmable gate array FPGA module, then carrying out frequency mixing on the digital baseband signals and the direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module, processing the mixed digital signals through the analog-to-digital conversion module, outputting radio frequency signals, and processing the radio frequency signals through the radio frequency front end module and then sending the radio frequency signals.
As an improvement of the invention, the digital-to-analog conversion module comprises a digital-to-analog converter DAC and an analog-to-digital converter ADC.
As an improvement of the invention, the radio frequency front end module comprises a radio frequency receiving front end module and a radio frequency transmitting front end module; the radio frequency receiving front-end processing module comprises a band-pass filter, an adjustable attenuator and a fixed amplifier, radio frequency signals are filtered by the band-pass filter and then sequentially pass through the adjustable attenuator and the fixed amplifier, and after the amplitude of the signals is adjusted, the radio frequency signals enter an analog-to-digital converter ADC; the radio frequency transmission front-end processing module comprises a band-pass filter, an adjustable amplifier and a band filter; the radio frequency signals sent by the digital-to-analog converter DAC sequentially pass through the band-pass filter, the adjustable amplifier and the band filter, and the processed radio frequency signals are transmitted.
The business unit comprises a Digital Signal Processor (DSP) module; the service unit is used for demodulating the digital baseband signal sent by the channel unit through the exchange chip unit SW, and sending the demodulated digital baseband signal to the main control unit through the exchange chip unit SW by the high-speed serial bus SRIO interface; the service unit is also used for modulating the digital baseband signal sent by the main control unit through the exchange chip unit SW, and sending the modulated digital baseband signal into the channel unit through the exchange chip unit SW through the high-speed serial bus SRIO interface.
The main control unit comprises a system-on-chip SOC module, and the system-on-chip SOC module is provided with an external interface; the main control unit configures a switching chip unit SW through an integrated circuit bus I2C; the main control unit is used for controlling the channel unit and the service unit and processing the digital baseband signal sent by the service unit through the exchange chip unit SW; the main control unit is also used for receiving and analyzing the instruction input by the external interface of the system on chip SOC module, and then sending the analyzed instruction to the service unit through the exchange chip unit SW;
the system-on-chip SOC module comprises a processing system PS submodule and a programmable logic PL submodule, wherein the processing system PS submodule is used for controlling the channel unit and the service unit, and the programmable logic PL submodule is used for processing the digital baseband signals and managing an external interface of the main control unit.
As an improvement of the present invention, in the main control unit, an external interface of the SOC module includes: the device comprises an audio interface, a data interface, a display interface, a tone interface and a power amplifier interface.
As an improvement of the invention, the programmable logic PL sub-module of the SOC module comprises the following specific steps of managing the external interface of the main control unit:
the audio interface is managed through a serial peripheral interface SPI, and the data interface, the display interface, the antenna tuning interface and the power amplifier interface are managed through an asynchronous receiving and transmitting transmitter UART.
Specifically, the system-on-chip SOC module is a chip integration of an information system core, and key components of the system are integrated on a chip. The system-on-chip SOC architecture chip Zynq-7045 of the Xilinx company integrates the software programmability of the ARM processor and the hardware programmability of the field programmable gate array FPGA.
The high-speed serial bus SRIO is a serial rapidIO interface which is applied to connection of a serial backboard, a digital signal processor DSP and a related serial data plane, and the data transmission rate of a 5Gb processing system PS is supported at most.
Specifically, the short wave communication technology verifies that the universal hardware platform adopts a digital signal processor DSP+a field programmable gate array FPGA+a system on chip SOC architecture, and the digital signal processor DSP module of the service unit not only supports the realization of the original functions of a radio station, but also can realize the service functions of autonomous frequency selection, broadband data processing, multipath baseband signal processing and the like; the field programmable gate array FPGA module of the channel unit is mainly used for receiving and transmitting broadband radio frequency signals; the system-on-chip SOC module of the main control unit selects XC7Z045 in Zynq-7000 series of Xilinx company, and two parts of a processing system PS submodule and a programmable logic PL submodule are integrated inside, wherein the processing system PS submodule mainly completes control functions of a channel unit and a service unit for a dual-core ARM, and comprises a power amplifier, a antenna regulator, a filter and the like; the programmable logic PL submodule is a K7 series field programmable gate array FPGA which mainly assists in completing broadband data baseband signal processing and management of an external interface of the main control unit.
As an improvement of the invention, the short wave communication technology verification universal hardware platform further comprises a clock management unit.
As an improvement of the invention, the short wave communication technology verification universal hardware platform further comprises a power management unit.
The system on chip SOC module is configured through a network port (2 RJ 45), the digital signal processor DSP module is configured through a network port (3 RJ 45), the field programmable gate array FPGA module is configured through a high-speed serial bus SRIO interface by the system on chip SOC, and the register parameters of the exchange chip unit modules are configured through an integrated circuit bus I2C interface by the system on chip SOC module.
As shown in Table 3, the main device performance parameter table of the general hardware platform is verified for the short-wave communication technology of the invention.
The chip model is foreign name, but three main devices, namely a digital signal processor DSP, a field programmable gate array FPGA and a system on chip SOC, are all domestic substitution products at present.
Table 3 short wave communication technology verifies general hardware platform main device performance parameter table
The invention discloses a signal processing method for verifying a general hardware platform based on a short-wave communication technology, which comprises the following three processing steps:
(1) A received signal processing step: the radio frequency signal is processed by a radio frequency receiving front-end module of a channel unit, the processed radio frequency signal is sent to an analog-to-digital converter ADC for direct sampling and digitizing, and then is subjected to digital mixing down-conversion with a direct digital frequency synthesis DDS signal of a field programmable gate array FPGA module, and a digital baseband signal is output; the digital baseband signal is sent into a Digital Signal Processor (DSP) module of a service unit through a high-speed serial bus (SRIO) for demodulation, the demodulated digital baseband signal is sent into a system-on-chip (SOC) module of a main control unit through a switching chip unit (SW) through the high-speed serial bus (SRIO), and the SOC module sends the digital baseband signal into an external interface through a Serial Peripheral Interface (SPI) or an asynchronous transceiver transmitter (UART);
the radio frequency signal is an audio signal or a radio station signal, the digital baseband signal obtained after the audio signal is subjected to the signal receiving and processing step is transferred to an audio unit accessed by a data interface through a serial peripheral interface SPI by a system on chip SOC module, and the digital baseband signal obtained after the radio station signal is subjected to the signal receiving and processing step is transferred to a radio station accessed by the data interface through a universal asynchronous receiving and transmitting transmitter UART by the system on chip SOC module;
specifically, the radio frequency front end module of the universal hardware platform channel unit is verified by a short wave communication technology through radio frequency signals received from the power amplification unit, the radio frequency front end module comprises a band-pass filter, an adjustable attenuator, a fixed amplifier and the like, the signal amplitude is adjusted to a reasonable amplitude, and one path of signals are changed into two paths of differential signals through a transformer and are sent to the analog-to-digital conversion module ADC. The analog-to-digital conversion module ADC directly samples and digitizes the radio frequency signal at the sampling rate of the 100MS processing system PS, outputs parallel data, and then carries out digital mixing with the direct digital frequency synthesis DDS signal generated by the control of the field programmable gate array FPGA module, and directly down-converts the direct digital frequency synthesis DDS signal to a baseband. The FPGA module realizes digital down-conversion DDC processing, the corresponding data rate is reduced from 100MHz to 8KHz of baseband rate, the total extraction multiple is 12500, the output I/Q two baseband signals are sent to the DSP module of the service unit through the SRIO interface for demodulation processing, the demodulated baseband data are sent to the SOC module of the main control unit through the SRIO interface, and finally the SOC module of the system on chip is transferred to the audio unit through the SPI.
As an improvement of the invention, the sampling rate of the analog-to-digital converter ADC is 100MSPS.
As an improvement of the invention, the total extraction multiple of the frequency mixing down-conversion is 12500.
(2) A transmission signal processing step: the digital baseband signal is sent to the system on chip SOC module of the main control unit through the external interface of the system on chip SOC module, then sent to the digital signal processor DSP module of the service unit through the high-speed serial bus SRIO interface by the exchange chip unit SW to be modulated, the modulated digital baseband signal is sent to the field programmable gate array FPGA module of the channel unit through the high-speed serial bus SRIO interface to be subjected to digital up-conversion processing to output a digital signal; mixing the digital signal with a direct digital frequency synthesis DDS signal generated by a field programmable gate array FPGA module, converting the mixed digital signal into a radio frequency signal through a digital-to-analog converter DAC, and transmitting the radio frequency signal through a radio frequency transmitting front-end module;
specifically, the digital baseband signal is a digital audio signal or a digital radio signal, the audio unit accessed by the digital audio signal through the data interface is sent to the system on chip SOC module of the main control unit through the serial peripheral interface SPI, and the radio accessed by the digital radio signal through the data interface is sent to the system on chip SOC module of the main control unit through the universal asynchronous receiver transmitter UART;
specifically, the audio unit sends digital audio signals to a system-on-chip SOC module of a main control unit of a short wave communication technology verification universal hardware platform through a serial peripheral interface SPI, the system-on-chip SOC module sends the digital audio signals to a digital signal processor DSP module of a service unit through a high-speed serial bus SRIO interface, the digital signal processor DSP module carries out modulation processing, the modulated data are sent to a field programmable gate array FPGA module of a channel unit through the high-speed serial bus SRIO interface, the field programmable gate array FPGA module carries out digital up-conversion processing, the data rate is converted from 8KHz to 100MHz, then the frequency is mixed with direct digital frequency generated by the field programmable gate array FPGA module to synthesize DDS signals, the frequency is shifted to radio frequency, the high-speed data are converted into two analog differential signals through a DAC, the two signals are converted into one signal through a transformer, and the two signals are sent to a power amplification unit after passing through a band-pass filter, an adjustable amplifier and a band filter of a radio frequency front end module.
The receiving and transmitting flow of the radio station data is similar to the receiving and transmitting of the audio frequency, and the difference is that the upper computer interacts with the radio station through a data interface.
(3) The signal processing step of the main control part: the main control part digital signals comprise control signals and feedback signals, wherein the control signals are issued to a System On Chip (SOC) module of the main control unit through an external interface of the SOC module, the control signals are received by a Programmable Logic (PL) sub-module in the SOC module and forwarded to a Processing System (PS) sub-module, and the processing system PS sub-module finishes analysis of the control signals; the feedback signal is issued to the system on chip SOC module of the main control unit through an external interface of the system on chip SOC module, the programmable logic PL submodule in the system on chip SOC module receives the feedback signal and forwards the feedback signal to the processing system PS submodule, and the processing system PS submodule finishes analysis of the feedback signal.
Specifically, the signal processing flow of the main control part is as follows:
the digital signals comprise control signals issued by the radio stations and feedback signals of the radio stations, wherein the control signals are issued to the main control unit through a universal asynchronous receiving and transmitting transmitter UART by the radio stations accessed by the display interface, a programmable logic PL submodule in a system-on-chip SOC module of the main control unit realizes a universal asynchronous receiving and transmitting transmitter UART interface function through software, received control signal data is forwarded to a processing system PS submodule in the system-on-chip SOC module of the main control unit, instruction analysis is completed by the processing system PS submodule according to a control protocol, and the content of the instruction mainly comprises a current working mode, parameters in corresponding modes, time information, receiving and transmitting states, channel frequencies, channel signals, power levels, antenna tuning control, antenna type selection and the like.
The feedback signals of the radio station mainly comprise a module startup self-checking state, a working mode, a mode parameter, a receiving and transmitting state, a power abnormal signal, a sky tuning state and the like. The power class and the power abnormality signal are communicated with the power amplifier module of the radio station through the power amplifier interface, and the antenna type selection and the antenna tuning state are communicated with the antenna tuning module of the radio station through the antenna tuning interface.
The control signal processing flow of the upper computer is similar to that of the main control part, and the difference is that the upper computer communicates with the radio station through a network port (1 RJ 45).
The main chip module software configuration flow is that the system on chip SOC module is configured through a network port (2 RJ 45), the digital signal processor DSP module is configured through a network port (3 RJ 45), the field programmable gate array FPGA module is configured through a high-speed serial bus SRIO interface by the system on chip SOC, and the exchange chip unit register parameters are configured through an integrated circuit bus I2C interface by the system on chip SOC.
The short-wave communication technology of this embodiment verifies the general hardware platform, and main technical indexes are as follows:
1) General index
a) Frequency range: 2-30 MHz;
b) Frequency interval: 100Hz;
c) Frequency stability: better than 0.5X10-7/d;
d) Signal bandwidth: modulation bandwidths 3K, 6K, 12K, 24K and 48K;
e) Transmit/receive switching time: and less than or equal to 10ms.
2) Hair main index
a) Excitation output: 0 dBm+ -2 dB (2-30 MHz,50 Ω impedance);
b) Carrier suppression: less than or equal to-60 dB;
c) Sideband suppression: less than or equal to-60 dB;
d) In-band side wave: less than or equal to-60 dB;
e) In-band noise: and is less than or equal to-110 dB/Hz.
3) Receive the main index
a) Sensitivity: -113dBm (sinad=16 dB, 50Ω) (3 kHz bandwidth);
b) Large signal to noise ratio: not less than 45dB;
c) Spurious frequency suppression ratio: more than or equal to 70dB;
d) Out-of-band intermodulation: more than or equal to 80dB;
e) Automatic gain control: starting from 2 times of reference sensitivity, the input change is 100dB, and the output change is less than or equal to 2dB.
While the invention has been described in detail in this specification with reference to the general description and the specific embodiments thereof, it will be apparent to one skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.
Claims (10)
1. The utility model provides a general hardware platform of short wave communication technique verification, includes channel unit, service unit, main control unit and exchange chip unit SW, its characterized in that:
the exchange chip unit SW comprises a high-speed serial bus SRIO exchange chip which is respectively connected with the channel unit, the service unit and the main control unit through the high-speed serial bus SRIO and is used for transmitting signals among the channel unit, the service unit and the main control unit;
the channel unit comprises a Field Programmable Gate Array (FPGA) module, a radio frequency front end module and a digital-to-analog conversion module;
the channel unit is used for mixing the received radio frequency signals with direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module after the radio frequency front end module processing and the analog-to-digital conversion module processing, and the field programmable gate array FPGA module performs down-conversion on the mixed signals to output digital baseband signals, and finally sends the digital baseband signals to the service unit through the exchange chip unit SW;
the channel unit is also used for carrying out digital up-conversion processing on the digital baseband signals input by the service unit through the exchange chip unit SW through the field programmable gate array FPGA module, mixing the digital baseband signals with direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module, processing the mixed digital signals through the analog-to-digital conversion module, outputting radio frequency signals, processing the radio frequency signals through the radio frequency front end module, and sending the radio frequency signals;
the business unit comprises a Digital Signal Processor (DSP) module; the service unit is used for demodulating the digital baseband signal sent by the channel unit through the exchange chip unit SW, and sending the demodulated digital baseband signal to the main control unit through the exchange chip unit SW by the high-speed serial bus SRIO interface; the service unit is also used for modulating the digital baseband signal sent by the main control unit through the exchange chip unit SW, and sending the modulated digital baseband signal into the channel unit through the exchange chip unit SW through the high-speed serial bus SRIO interface;
the main control unit comprises a system-on-chip SOC module, and the system-on-chip SOC module is provided with an external interface; the main control unit configures a switching chip unit SW through an integrated circuit bus I2C; the main control unit is used for controlling the channel unit and the service unit and processing the digital baseband signal sent by the service unit through the exchange chip unit SW; the main control unit is also used for receiving and analyzing the instruction input by the external interface of the system on chip SOC module, and then sending the analyzed instruction to the service unit through the exchange chip unit SW;
the system-on-chip SOC module comprises a processing system PS submodule and a programmable logic PL submodule, wherein the processing system PS submodule is used for controlling the channel unit and the service unit, and the programmable logic PL submodule is used for processing the digital baseband signals and managing an external interface of the main control unit.
2. The short wave communication technology verification universal hardware platform of claim 1, wherein: in the channel unit, the digital-to-analog conversion module comprises a digital-to-analog converter DAC and an analog-to-digital converter ADC.
3. The short wave communication technology verification universal hardware platform of claim 1, wherein: in the channel unit, the radio frequency front end module comprises a radio frequency receiving front end module and a radio frequency transmitting front end module;
the radio frequency receiving front-end processing module comprises a band-pass filter, an adjustable attenuator and a fixed amplifier, radio frequency signals are filtered by the band-pass filter and sequentially pass through the adjustable attenuator and the fixed amplifier, and after the signal amplitude is adjusted, the radio frequency signals enter the digital-to-analog conversion module;
the radio frequency transmission front-end processing module comprises a band-pass filter, an adjustable amplifier and a band filter; the radio frequency signals sent by the digital-to-analog conversion module sequentially pass through a band-pass filter, an adjustable amplifier and a band filter, and the processed radio frequency signals are transmitted.
4. The short wave communication technology verification universal hardware platform according to claim 1, wherein the external interface of the system on chip SOC module in the master control unit comprises: the device comprises an audio interface, a data interface, a display interface, a tone interface and a power amplifier interface.
5. The short wave communication technology verification universal hardware platform according to claim 1 or 4, wherein: the programmable logic PL sub-module comprises the following specific steps of managing an external interface of a main control unit: the audio interface is managed through a serial peripheral interface SPI, and the data interface, the display interface, the antenna tuning interface and the power amplifier interface are managed through an asynchronous receiving and transmitting transmitter UART.
6. The short wave communication technology verification universal hardware platform of claim 1, wherein: the short wave communication technology verification universal hardware platform further comprises a clock management unit.
7. The short wave communication technology verification universal hardware platform of claim 1, wherein: the short wave communication technology verification universal hardware platform further comprises a power management unit.
8. A signal processing method for verifying a general hardware platform based on the short-wave communication technology as claimed in claim 1, comprising the following three processing steps:
(1) A received signal processing step: the radio frequency signal is processed by a radio frequency receiving front-end module of a channel unit, the processed radio frequency signal is sent to an analog-to-digital converter ADC for direct sampling and digitizing, and then is subjected to digital mixing down-conversion with a direct digital frequency synthesis DDS signal of a field programmable gate array FPGA module, and a digital baseband signal is output; the digital baseband signal is sent into a Digital Signal Processor (DSP) module of a service unit through a high-speed serial bus (SRIO) for demodulation, the demodulated digital baseband signal is sent into a system-on-chip (SOC) module of a main control unit through a switching chip unit (SW) through the high-speed serial bus (SRIO), and the SOC module sends the digital baseband signal into an external interface through a Serial Peripheral Interface (SPI) or an asynchronous transceiver transmitter (UART);
(2) A transmission signal processing step: the digital baseband signal is sent to the system on chip SOC module of the main control unit through the external interface of the system on chip SOC module, then is sent to the digital signal processor DSP module of the service unit through the high-speed serial bus SRIO interface by the exchange chip unit SW for modulation, and the modulated digital baseband signal is sent to the field programmable gate array FPGA module of the channel unit through the high-speed serial bus SRIO interface for digital up-conversion processing, and digital signals are output; mixing the digital signal with a direct digital frequency synthesis DDS signal generated by a field programmable gate array FPGA module, converting the mixed digital signal into a radio frequency signal through a digital-to-analog converter DAC, and transmitting the radio frequency signal through a radio frequency transmitting front-end module;
(3) The signal processing step of the main control part: the main control part digital signals comprise control signals and feedback signals, wherein the control signals are issued to a System On Chip (SOC) module of the main control unit through an external interface of the SOC module, the control signals are received by a Programmable Logic (PL) sub-module in the SOC module and forwarded to a Processing System (PS) sub-module, and the processing system PS sub-module finishes analysis of the control signals; the feedback signal is issued to the system on chip SOC module of the main control unit through an external interface of the system on chip SOC module, the programmable logic PL submodule in the system on chip SOC module receives the feedback signal and forwards the feedback signal to the processing system PS submodule, and the processing system PS submodule finishes analysis of the feedback signal.
9. The signal processing method according to claim 8, wherein: in the step of processing the received signal, the sampling rate of the analog-to-digital converter ADC is 100MSPS.
10. The signal processing method according to claim 8, wherein: in the received signal processing step, the total decimation multiple of the frequency mixing down-conversion is 12500.
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| CN103414484A (en) * | 2013-07-05 | 2013-11-27 | 熊猫电子集团有限公司 | Short-wave four-channel integrated channel machine |
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| CN109347504A (en) * | 2018-09-26 | 2019-02-15 | 西安烽火电子科技有限责任公司 | A kind of short-wave radio frequency digital processing system |
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| CN103414484A (en) * | 2013-07-05 | 2013-11-27 | 熊猫电子集团有限公司 | Short-wave four-channel integrated channel machine |
| CN104158561A (en) * | 2014-08-12 | 2014-11-19 | 西安烽火电子科技有限责任公司 | Short wave frequency hopping signal processing method |
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