CN114598348A - General hardware platform for short-wave communication technology verification and signal processing method thereof - Google Patents
General hardware platform for short-wave communication technology verification and signal processing method thereof Download PDFInfo
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Abstract
The invention provides a short wave communication technology verification general hardware platform and a signal processing method thereof, wherein the short wave communication technology verification general hardware platform comprises a channel unit, a service unit, a main control unit and an exchange chip unit SW; the switching chip unit SW is used for signal transmission among the channel unit, the service unit and the main control unit; the channel unit is used for receiving and transmitting radio frequency signals; the service unit is used for modulating and demodulating the digital baseband signal; the SOC module of the main control unit comprises a processing system PS submodule and a programmable logic PL submodule, wherein the processing system PS submodule is used for controlling the channel unit and the service unit, and the programmable logic PL submodule is used for processing the digital baseband signal and managing an external interface of the main control unit. The device of the invention adopts a chip with high main frequency and large resources and adopts the SRIO connection of the high-speed serial bus with a single internal interface, thereby solving the problems that the prior radio platform does not support the development of newly-developed technology and the reliability is reduced caused by excessive interfaces.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a universal hardware platform for short-wave communication technical verification and a signal processing method thereof.
Background
With the continuous development of communication technology, many new technologies, such as short-wave broadband, multi-channel reception, autonomous frequency selection, etc., have emerged in the field of short-wave communication in recent years. Meanwhile, the requirement of the new technology on a hardware platform is higher and higher, and the original hardware platform of the short-wave radio station cannot meet the requirement of the new technology on resources, so that the research and development of a general and standardized hardware platform with comprehensive functions, sufficient resources and rich interfaces is urgent.
At present, a core processing unit of an existing short-wave radio station comprises a service unit, a channel unit and a main control unit, wherein the service unit adopts a Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) architecture, the channel unit adopts a field programmable FPGA + AD/DA architecture, and the main control unit adopts an advanced reduced instruction set computer (ARM) and peripheral interface chip architecture. Table 1 shows the core processing unit of the conventional shortwave radio.
The service unit mainly completes the functional services of the active systems such as modulation and demodulation, fixed frequency, automatic control communication, frequency hopping and the like of radio station data and voice; the channel unit mainly realizes the radio frequency digitization of signals, namely converting baseband modulation signals from the service unit into radio frequency signals and then sending out the radio frequency signals or converting received single-path radio frequency signals into baseband signals and sending the baseband signals to the service unit for demodulation; the main control unit mainly completes control of units such as services, channels, power amplifiers, antenna modulators, filters and the like, and management of external interfaces of the radio station.
Table 1 core processing unit main device of existing short wave radio station
When receiving signals, the radio station receives radio frequency signals through the antenna, and the radio frequency signals are sent to the channel unit through the power amplifier and the filter. The radio frequency front end in the channel unit comprises attenuation, amplification, low-pass filtering and the like, the signal amplitude is adjusted to be within the input range of the analog-to-digital converter ADC, and then one path of signal is changed into two differential paths of signals through a transformer and sent to the analog-to-digital converter ADC. The analog-digital converter ADC is used for directly sampling and digitizing a radio frequency signal at the sampling rate of 73.728MSPS and outputting parallel data with the bit width of 16 bits, then the parallel data and a direct digital frequency synthesis DDS signal generated by the control of a channel unit field programmable gate array FPGA are subjected to digital mixing, the data rate is reduced from 73.728MHz to the base band rate of 8KHz, the total extraction multiple in the period is 9216, so that the radio frequency signal is converted into a base band signal in a frequency conversion mode, finally the base band signal is sent to a field programmable gate array FPGA module of a service unit through a multichannel buffer serial interface MCBSP, the FP field programmable gate array module is sent to a digital signal processor DSP through an external memory interface EMIF for digital signal demodulation processing, the demodulated base band data is sent to an audio DAC through a serial peripheral interface SPI to be converted into an analog audio signal and sent to an audio unit, the analog audio signal is sent to an audio interface of a radio station after audio amplification, the voice can be heard by externally connecting an earphone and microphone set.
When sending signals, the voice analog signals generated by the earphone microphone set are transmitted to the audio ADC of the service unit after passing through the radio audio unit, the audio ADC converts the analog signals into digital signals at a sampling rate of 8K and transmits the digital signals to the DSP through the SPI, the modulation processing is carried out, the modulated data are transmitted to the FPGA module through the EMIF, the FPGA module is transmitted to the channel unit through the MCBSP interface for up-conversion processing, the data rate is shifted from 8Kb to 73.728Mb, and then the data are mixed with the DDS signals generated by the FPGA module for direct digital frequency synthesis, the frequency is shifted to radio frequency, the radio frequency DAC is transmitted to be converted into radio frequency analog signals, the analog signals are amplified and filtered by the front end of the channel unit and then are transmitted, and finally, the antenna is used for transmitting the signal through a power amplifier and an antenna tone. Table 2 shows the relationship between the main interfaces inside or between the core processing units of the conventional short-wave radio.
TABLE 2 Main interface relationship inside or between core processing units of existing shortwave radio
In the prior art, a service, a channel and a main control are divided into three independent units so as to facilitate debugging and problem troubleshooting, but the main devices have the disadvantages of smaller resources, low integration level, more interfaces among the units, lower reliability and more problems in actual production.
Disclosure of Invention
Aiming at the problems in the prior art, the invention aims to provide a universal hardware platform for short-wave communication technology verification, which integrates a service unit, a channel unit and a main control unit together, adopts chips with higher main frequency and larger resources as main devices, and adopts an internal single-interface high-speed serial bus (SRIO) for connection, thereby achieving the purpose of solving the problems that the prior radio platform does not support newly-researched technical development, the reliability is reduced due to excessive interfaces and the like.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme.
The invention discloses a general hardware platform for short-wave communication technology verification, which comprises a channel unit, a service unit, a main control unit and an exchange chip unit SW;
the switching chip unit SW comprises a high-speed serial bus SRIO switching chip, and the high-speed serial bus SRIO switching chip is respectively connected with the channel unit, the service unit and the main control unit through the high-speed serial bus SRIO and is used for signal transmission among the channel unit, the service unit and the main control unit.
The channel unit comprises a Field Programmable Gate Array (FPGA) module, a radio frequency front end module and a digital-to-analog conversion module;
the channel unit is used for processing the received radio frequency signal by the radio frequency front end module and the analog-to-digital conversion module, then mixing the radio frequency signal with a direct digital frequency synthesis DDS signal generated by the field programmable gate array FPGA module, performing down-conversion on the mixed signal by the field programmable gate array FPGA module to output the mixed signal as a digital baseband signal, and finally sending the digital baseband signal to the service unit through the switching chip unit SW;
the channel unit is also used for performing digital up-conversion processing on digital baseband signals input by the service unit through the switch chip unit SW through the field programmable gate array FPGA module, and then performing frequency mixing with direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module, wherein the digital signals after frequency mixing are processed by the analog-to-digital conversion module and then output radio frequency signals, and the radio frequency signals are processed by the radio frequency front end module and then are transmitted.
The service unit comprises a DSP module; the service unit is used for demodulating the digital baseband signal sent by the channel unit through the switching chip unit SW and sending the demodulated digital baseband signal to the main control unit through the switching chip unit SW through the SRIO interface of the high-speed serial bus; the service unit is also used for modulating the digital baseband signals sent by the main control unit through the switching chip unit SW, and sending the modulated digital baseband signals to the channel unit through the switching chip unit SW through the high-speed serial bus SRIO interface.
The main control unit comprises a system-on-chip SOC module, and the system-on-chip SOC module is provided with an external interface; the main control unit configures a switching chip unit SW through an integrated circuit bus I2C; the main control unit is used for controlling the channel unit and the service unit and processing the digital baseband signals sent by the service unit through the switching chip unit SW; the main control unit is also used for receiving and analyzing an instruction input by an external interface of the SOC module, and then sending the analyzed instruction to the service unit through the exchange chip unit SW.
The SOC module comprises a processing system PS submodule and a programmable logic PL submodule, wherein the processing system PS submodule is used for controlling a channel unit and a service unit, and the programmable logic PL submodule is used for processing a digital baseband signal and managing an external interface of a main control unit.
Preferably, in the channel unit, the digital-to-analog conversion module includes a digital-to-analog converter DAC and an analog-to-digital converter ADC;
preferably, in the channel unit, the radio frequency front end module includes a radio frequency receiving front end module and a radio frequency transmitting front end module; wherein: the radio frequency receiving front-end processing module comprises a band-pass filter, an adjustable attenuator and a fixed amplifier, a radio frequency signal is filtered by the band-pass filter, then sequentially passes through the adjustable attenuator and the fixed amplifier, and after the signal amplitude is adjusted, the radio frequency signal enters the digital-to-analog conversion module;
the radio frequency transmitting front-end processing module comprises a band-pass filter, an adjustable amplifier and a wave band filter; the radio frequency signal sent by the digital-to-analog conversion module is transmitted to the radio frequency signal after being processed by the band-pass filter, the adjustable amplifier and the band filter in sequence.
Preferably, in the main control unit, the external interface of the SOC module includes: audio interface, data interface, display interface, sky tone interface and power amplifier interface.
Preferably, the specific steps of the programmable logic PL submodule managing the external interface of the main control unit are as follows:
the audio interface is managed through a serial peripheral interface SPI, and the data interface, the display interface, the antenna interface and the power amplifier interface are managed through a UART (universal asynchronous receiver transmitter), a display interface, a sky tone interface and a power amplifier interface.
Preferably, the short-wave communication technology verification general hardware platform further comprises a clock management unit.
Preferably, the short-wave communication technology verification general hardware platform further comprises a power management unit.
The invention discloses a signal processing method for verifying a universal hardware platform based on a short-wave communication technology, which comprises the following three processing steps:
(1) a received signal processing step: the radio frequency signal is processed by a radio frequency receiving front end module of the channel unit, the processed radio frequency signal is sent to an analog-to-digital converter (ADC) for direct sampling and digitization, then is subjected to digital mixing down-conversion with a direct digital frequency synthesis DDS signal of a Field Programmable Gate Array (FPGA) module, and a digital baseband signal is output; the digital baseband signals are sent to a DSP module of a service unit through a high-speed serial bus SRIO for demodulation, the demodulated digital baseband signals are sent to a system-on-chip SOC module of a main control unit through a switching chip unit SW through the high-speed serial bus SRIO, and the system-on-chip SOC module sends the digital baseband signals to an external interface through a serial peripheral interface SPI or an asynchronous receiving and transmitting transmitter UART;
(2) a transmission signal processing step: the digital baseband signals are sent to a system-on-chip SOC module of a main control unit through an external interface of the system-on-chip SOC module, then sent to a digital signal processor DSP module of a service unit through a high-speed serial bus SRIO interface by a switching chip unit SW for modulation, and the modulated digital baseband signals are sent to a field programmable gate array FPGA module of a channel unit through a high-speed serial bus SRIO interface for digital up-conversion processing and digital signal output; the digital signal is mixed with a direct digital frequency synthesis DDS signal generated by a field programmable gate array FPGA module, the mixed digital signal is changed into a radio frequency signal through a digital-to-analog converter DAC, and the radio frequency signal is sent through a radio frequency sending front end module;
(3) signal processing of the main control part: the digital signals of the main control part comprise control signals and feedback signals, wherein the control signals are issued to a system-on-chip SOC module of the main control unit through an external interface of the system-on-chip SOC module, a programmable logic PL sub-module in the system-on-chip SOC module receives the control signals and forwards the control signals to a processing system PS sub-module, and the processing system PS sub-module completes analysis of the control signals; the feedback signal is issued to the SOC module of the main control unit through an external interface of the SOC module, a programmable logic PL submodule in the SOC module receives the feedback signal and forwards the feedback signal to a processing system PS submodule, and the processing system PS submodule completes analysis of the feedback signal.
Preferably, in the received signal processing step, the sampling rate of the analog-to-digital converter ADC is 100 MSPS.
Preferably, in the received signal processing step, the total decimation multiple of the mixing down-conversion is 12500.
Compared with the prior art, the invention has the following advantages:
(1) the hardware platform is highly integrated in design, and the functions are more comprehensive;
(2) the high-speed processor and the ultra-large resource capacity effectively support the newly-researched technical development;
(3) the design of the simplified interfaces among the core devices solves the problem of reliability reduction caused by excessive interfaces in the prior art.
Drawings
The invention is described in further detail below with reference to the figures and specific embodiments.
FIG. 1 is a schematic block diagram of a generic hardware platform of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention.
The short-wave communication technology verifies that the universal hardware platform can realize full digitalization processing from short-wave baseband signals to radio frequency signals or from the radio frequency signals to the baseband signals. The radio frequency digitization belongs to the software radio SDR category, and the essence of the software radio technology is that an ADC/DAC is close to a radio frequency antenna end, a signal processing part is made in a digital domain as soon as possible, and the flexibility and the upgrading capability of a radio station are improved to the greatest extent.
Referring to fig. 1, a schematic block diagram of a communication module of the present invention is shown. The invention discloses a general hardware platform for short-wave communication technology verification, which comprises a channel unit, a service unit, a main control unit and an exchange chip unit SW;
the switching chip unit SW comprises a high-speed serial bus SRIO switching chip, and the high-speed serial bus SRIO switching chip is respectively connected with the channel unit, the service unit and the main control unit through the high-speed serial bus SRIO and is used for signal transmission among the channel unit, the service unit and the main control unit.
The channel unit comprises a Field Programmable Gate Array (FPGA) module, a radio frequency front end module and a digital-to-analog conversion module;
the channel unit is used for processing the received radio frequency signal by the radio frequency front end module and the analog-to-digital conversion module, then mixing the radio frequency signal with a direct digital frequency synthesis DDS signal generated by the field programmable gate array FPGA module, performing down-conversion on the mixed signal by the field programmable gate array FPGA module to output the mixed signal as a digital baseband signal, and finally sending the digital baseband signal to the service unit through the switching chip unit SW;
the channel unit is also used for performing digital up-conversion processing on digital baseband signals input by the service unit through the switch chip unit SW through the field programmable gate array FPGA module, and then performing frequency mixing with direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module, wherein the digital signals after frequency mixing are processed by the analog-to-digital conversion module and then output radio frequency signals, and the radio frequency signals are processed by the radio frequency front end module and then are transmitted.
As an improvement of the present invention, the digital-to-analog conversion module includes a digital-to-analog converter DAC and an analog-to-digital converter ADC.
As an improvement of the present invention, the rf front-end module includes an rf receiving front-end module and an rf transmitting front-end module; the radio frequency receiving front-end processing module comprises a band-pass filter, an adjustable attenuator and a fixed amplifier, a radio frequency signal is filtered by the band-pass filter, then sequentially passes through the adjustable attenuator and the fixed amplifier, and after the signal amplitude is adjusted, the radio frequency signal enters an analog-to-digital converter (ADC); the radio frequency transmitting front-end processing module comprises a band-pass filter, an adjustable amplifier and a wave band filter; and the radio-frequency signal sent by the digital-to-analog converter DAC is transmitted to the processed radio-frequency signal through the band-pass filter, the adjustable amplifier and the band filter in sequence.
The service unit comprises a DSP module; the service unit is used for demodulating the digital baseband signal sent by the channel unit through the switching chip unit SW and sending the demodulated digital baseband signal to the main control unit through the switching chip unit SW through the high-speed serial bus SRIO interface; the service unit is also used for modulating the digital baseband signals sent by the main control unit through the switching chip unit SW, and sending the modulated digital baseband signals to the channel unit through the switching chip unit SW through the high-speed serial bus SRIO interface.
The main control unit comprises a system-on-chip SOC module, and the system-on-chip SOC module is provided with an external interface; the main control unit configures a switching chip unit SW through an integrated circuit bus I2C; the main control unit is used for controlling the channel unit and the service unit and processing the digital baseband signals sent by the service unit through the switching chip unit SW; the main control unit is also used for receiving and analyzing an instruction input by an external interface of the SOC module and then sending the analyzed instruction to the service unit through the exchange chip unit SW;
the SOC module comprises a processing system PS submodule and a programmable logic PL submodule, wherein the processing system PS submodule is used for controlling a channel unit and a service unit, and the programmable logic PL submodule is used for processing a digital baseband signal and managing an external interface of a main control unit.
As an improvement of the present invention, in the main control unit, an external interface of the SOC module includes: audio interface, data interface, display interface, sky tone interface and power amplifier interface.
As an improvement of the present invention, the specific steps of the programmable logic PL submodule of the SOC module on the chip managing the external interface of the main control unit are as follows:
the audio interface is managed through a serial peripheral interface SPI, and the data interface, the display interface, the antenna interface and the power amplifier interface are managed through a UART (universal asynchronous receiver transmitter), a display interface, a sky tone interface and a power amplifier interface.
Specifically, the SOC module is a chip integration of the core of the information system, and integrates system key components on one chip. The Xilinx SOC architecture chip Zynq-7045 integrates the software programmability of an ARM processor and the hardware programmability of a Field Programmable Gate Array (FPGA).
The high-speed serial bus SRIO is a serial RapidIO interface for connecting and applying a serial backboard, a Digital Signal Processor (DSP) and a related serial data plane, and the PS data transmission rate of a 5Gb processing system is supported at the highest.
Specifically, the short-wave communication technology verifies that a general hardware platform adopts a digital signal processor DSP + field programmable gate array FPGA + system-on-chip SOC architecture, and a digital signal processor DSP module of a service unit not only supports the realization of the original functions of a radio station, but also can realize the service functions of autonomous frequency selection, broadband data processing, multi-path baseband signal processing and the like; the FPGA module of the channel unit is mainly used for receiving and transmitting broadband radio frequency signals; the SOC module of the main control unit selects XC7Z045 in Zynq-7000 series of Xilinx company, and integrates a PS submodule of a processing system and a programmable logic PL submodule inside, wherein the PS submodule of the processing system is a dual-core ARM and mainly completes control functions of a channel unit and a service unit, including a power amplifier, a pitch modulator, a filter and the like; the programmable logic PL submodule is a K7 series field programmable gate array FPGA which is mainly used for assisting in completing broadband data baseband signal processing and management of an external interface of a main control unit.
As an improvement of the invention, the short-wave communication technology verification general hardware platform further comprises a clock management unit.
As an improvement of the invention, the short-wave communication technology verification general hardware platform further comprises a power management unit.
The method comprises the steps of main chip software configuration, system-on-chip SOC modules are configured through a network interface (2RJ45), a digital signal processor DSP module is configured through a network interface (3RJ45), a field programmable gate array FPGA module is configured through a high-speed serial bus SRIO interface by the system-on-chip SOC, and register parameters of a switching chip unit module are configured through an integrated circuit bus I2C interface by the system-on-chip SOC modules.
As shown in table 3, the table of the performance parameters of the main components of the universal hardware platform is verified for the short-wave communication technology of the present invention.
The model of the chip is named abroad, but the three main devices, namely a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA) and a System On Chip (SOC), are domestic substitute products at present.
Table 3 table for verifying general hardware platform main device performance parameter by short wave communication technology
The invention discloses a signal processing method for verifying a universal hardware platform based on a short-wave communication technology, which comprises the following three processing steps:
(1) a received signal processing step: the radio frequency signal is processed by a radio frequency receiving front end module of the channel unit, the processed radio frequency signal is sent to an analog-to-digital converter (ADC) for direct sampling and digitization, then is subjected to digital mixing down-conversion with a direct digital frequency synthesis DDS signal of a Field Programmable Gate Array (FPGA) module, and a digital baseband signal is output; the digital baseband signals are sent to a DSP module of a service unit through a high-speed serial bus SRIO for demodulation, the demodulated digital baseband signals are sent to a system-on-chip SOC module of a main control unit through a switching chip unit SW through the high-speed serial bus SRIO, and the system-on-chip SOC module sends the digital baseband signals to an external interface through a serial peripheral interface SPI or an asynchronous receiving and transmitting transmitter UART;
the radio frequency signal is an audio signal or a radio station signal, the digital baseband signal obtained after the audio signal is received and processed by the signal receiving and processing step is forwarded to an audio unit accessed by a data interface through a Serial Peripheral Interface (SPI) by a System On Chip (SOC) module, and the digital baseband signal obtained after the radio station signal is received and processed by the signal receiving and processing step is sent to a radio station accessed by the data interface through a universal asynchronous receiving and transmitting transmitter (UART) by the System On Chip (SOC) module;
specifically, the radio frequency signal received from the power amplifier unit is subjected to short wave communication technology to verify a radio frequency front end module of the universal hardware platform channel unit, the radio frequency front end module comprises a band-pass filter, an adjustable attenuator, a fixed amplifier and the like, the signal amplitude is adjusted to a reasonable amplitude, and then one path of signal is changed into two paths of differential signals through a transformer and sent to an analog-to-digital conversion module (ADC). The analog-to-digital conversion module ADC carries out direct sampling digitization on radio frequency signals at a PS sampling rate of a 100MS processing system, outputs parallel data, then carries out digital mixing with direct digital frequency synthesis DDS signals generated by the control of a field programmable gate array FPGA module, and directly carries out down-conversion to a baseband. The FPGA module realizes DDC processing of digital down-conversion, the corresponding data rate is reduced from 100MHz to baseband rate of 8KHz, the total extraction multiple is 12500, two paths of output I/Q baseband signals are sent to a DSP module of a digital signal processor of a service unit through a high-speed serial bus SRIO interface for demodulation processing, demodulated baseband data are sent to a system-on-chip SOC module of a main control unit through a switching chip unit through the high-speed serial bus SRIO interface, and finally the demodulated baseband data are forwarded to an audio unit through a serial peripheral interface SPI by the system-on-chip SOC module.
As an improvement of the present invention, the sampling rate of the analog-to-digital converter ADC is 100 MSPS.
As an improvement of the present invention, the total decimation factor of the mixing down-conversion is 12500.
(2) A transmission signal processing step: the digital baseband signals are sent to a system-on-chip SOC module of a main control unit through an external interface of the system-on-chip SOC module, then sent to a digital signal processor DSP module of a service unit through a high-speed serial bus SRIO interface by a switching chip unit SW for modulation, and the modulated digital baseband signals are sent to a field programmable gate array FPGA module of a channel unit through a high-speed serial bus SRIO interface for digital up-conversion processing and digital signal output; the digital signal and a direct digital frequency synthesis DDS signal generated by the FPGA module are subjected to frequency mixing, the digital signal after frequency mixing is converted into a radio frequency signal through a digital-to-analog converter (DAC), and the radio frequency signal is sent through a radio frequency sending front-end module;
specifically, the digital baseband signal is a digital audio signal or a digital radio signal, the digital audio signal is sent to the system on chip SOC module of the main control unit through the serial peripheral interface SPI by the audio unit accessed by the data interface, and the digital radio signal is sent to the system on chip SOC module of the main control unit through the universal asynchronous receiver transmitter UART by the radio station accessed by the data interface;
specifically, the audio unit sends a digital audio signal to a system on chip SOC module of a main control unit of a short-wave communication technology verification general hardware platform through a serial peripheral interface SPI, the system on chip SOC module sends the digital audio signal to a digital signal processor DSP module of a service unit through a high-speed serial bus SRIO interface by a switching chip unit, the digital signal processor DSP module performs modulation processing, modulated data is sent to a field programmable gate array FPGA module of a channel unit through the high-speed serial bus SRIO interface, the field programmable gate array FPGA module performs digital up-conversion processing to convert the data rate from 8KHz to 100MHz, then the data is mixed with a direct digital frequency synthesis DDS signal generated by the field programmable gate array FPGA module to carry out frequency mixing, the frequency is moved to the radio frequency, and the high-speed data is converted into two analog differential signals through a digital-to-analog conversion module DAC, and the two paths of signals are converted into one path of signal through a transformer, and the one path of signal is sent to a power amplification unit after passing through a band-pass filter, an adjustable amplifier and a band filter of the radio frequency front-end module.
The process of receiving and sending the radio station data is similar to that of audio receiving and sending, and the difference is that the upper computer interacts with the radio station through a data interface.
(3) Signal processing of the main control part: the digital signals of the main control part comprise control signals and feedback signals, wherein the control signals are issued to a system-on-chip SOC module of the main control unit through an external interface of the system-on-chip SOC module, a programmable logic PL sub-module in the system-on-chip SOC module receives the control signals and forwards the control signals to a processing system PS sub-module, and the processing system PS sub-module completes analysis of the control signals; the feedback signal is issued to the SOC module of the main control unit through an external interface of the SOC module, a programmable logic PL submodule in the SOC module receives the feedback signal and forwards the feedback signal to a processing system PS submodule, and the processing system PS submodule completes analysis of the feedback signal.
Specifically, the signal processing flow of the main control part is as follows:
the digital signal comprises a control signal sent by the radio station and a feedback signal of the radio station, wherein the control signal is sent to the main control unit by the radio station accessed by a display interface through a universal asynchronous receiving and sending transmitter UART, the programmable logic PL submodule in the SOC module of the main control unit realizes the UART interface function of the universal asynchronous receiving and sending transmitter through software, the received control signal data is forwarded to a processing system PS submodule in the SOC module of the main control unit, the processing system PS submodule completes instruction analysis according to a control protocol, and the content of the instruction mainly comprises a current working mode, parameters under the corresponding mode, time information, a receiving and sending state, channel frequency, a channel number, a power level, an adjusting and tuning control, an antenna type selection and the like.
The feedback signal of the radio station mainly comprises a module power-on self-test state, a working mode, a mode parameter, a receiving and transmitting state, a power abnormal signal, an adjusting and tuning state and the like. The power level and power abnormal signal is communicated with a power amplifier module of the radio station through a power amplifier interface, and the tuning control, the antenna type selection and the tuning state are communicated with the tuning module of the radio station through the tuning interface.
The upper computer control signal processing flow is similar to the main control part signal processing flow, and the difference is that the upper computer communicates with a radio station through a network port (1RJ 45).
The software configuration flow of the main chip module is that the SOC module is configured through a network port (2RJ45), the DSP module is configured through a network port (3RJ45), the FPGA module is configured through the SOC through a high-speed serial bus SRIO interface, and the register parameters of the switching chip unit are configured through an integrated circuit bus I2C interface by the SOC.
The short-wave communication technology of the embodiment verifies the universal hardware platform, and the main technical indexes are as follows:
1) general index
a) Frequency range: 2-30 MHz;
b) frequency interval: 100 Hz;
c) frequency stability: is better than 0.5 multiplied by 10 < -7 >/d;
d) signal bandwidth: modulation bandwidths are 3K, 6K, 12K, 24K and 48K;
e) transmission/reception switching time: less than or equal to 10 ms.
2) Index of hair growth
a) Excitation output: 0dBm +/-2 dB (2-30 MHz, 50 omega impedance);
b) and (3) carrier suppression: less than or equal to-60 dB;
c) sideband suppression: less than or equal to-60 dB;
d) in-band secondary waves: less than or equal to-60 dB;
e) in-band noise: less than or equal to-110 dB/Hz.
3) Receive the main index
a) Sensitivity: less than or equal to-113 dBm (SINAD is 16dB and 50 omega) (3kHz bandwidth);
b) large signal to noise ratio: not less than 45 dB;
c) spurious frequency rejection ratio: not less than 70 dB;
d) out-of-band intermodulation: not less than 80 dB;
e) automatic gain control: starting from 2 times of reference sensitivity, the input changes by 100dB, and the output changes by less than or equal to 2 dB.
Although the present invention has been described in detail in this specification with reference to specific embodiments and illustrative embodiments, it will be apparent to those skilled in the art that modifications and improvements can be made thereto based on the present invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (10)
1. A general hardware platform for short wave communication technology verification comprises a channel unit, a service unit, a main control unit and a switch chip unit SW, and is characterized in that:
the switching chip unit SW comprises a high-speed serial bus SRIO switching chip which is respectively connected with the channel unit, the service unit and the main control unit through the high-speed serial bus SRIO and is used for signal transmission among the channel unit, the service unit and the main control unit;
the channel unit comprises a Field Programmable Gate Array (FPGA) module, a radio frequency front end module and a digital-to-analog conversion module;
the channel unit is used for processing the received radio frequency signal by the radio frequency front end module and the analog-to-digital conversion module, then mixing the radio frequency signal with a direct digital frequency synthesis DDS signal generated by the field programmable gate array FPGA module, performing down-conversion on the mixed signal by the field programmable gate array FPGA module to output the mixed signal as a digital baseband signal, and finally sending the digital baseband signal to the service unit through the switching chip unit SW;
the channel unit is also used for carrying out digital up-conversion processing on digital baseband signals input by the service unit through the switching chip unit SW through the field programmable gate array FPGA module, and then carrying out frequency mixing on the digital baseband signals and direct digital frequency synthesis DDS signals generated by the field programmable gate array FPGA module, wherein the digital signals after frequency mixing are processed by the analog-to-digital conversion module and then output radio frequency signals, and the radio frequency signals are processed by the radio frequency front end module and then are sent;
the service unit comprises a DSP module; the service unit is used for demodulating the digital baseband signal sent by the channel unit through the switching chip unit SW and sending the demodulated digital baseband signal to the main control unit through the switching chip unit SW through the high-speed serial bus SRIO interface; the service unit is also used for modulating the digital baseband signals sent by the main control unit through the switching chip unit SW and sending the modulated digital baseband signals into the channel unit through the switching chip unit SW through the high-speed serial bus SRIO interface;
the main control unit comprises a system-on-chip SOC module, and the system-on-chip SOC module is provided with an external interface; the main control unit configures a switching chip unit SW through an integrated circuit bus I2C; the main control unit is used for controlling the channel unit and the service unit and processing the digital baseband signals sent by the service unit through the switching chip unit SW; the main control unit is also used for receiving and analyzing an instruction input by an external interface of the SOC module and then sending the analyzed instruction to the service unit through the exchange chip unit SW;
the SOC module comprises a processing system PS submodule and a programmable logic PL submodule, wherein the processing system PS submodule is used for controlling a channel unit and a service unit, and the programmable logic PL submodule is used for processing a digital baseband signal and managing an external interface of a main control unit.
2. The short wave communication technology validation generic hardware platform of claim 1, wherein: in the channel unit, the digital-to-analog conversion module comprises a digital-to-analog converter DAC and an analog-to-digital converter ADC.
3. The short wave communication technology validation generic hardware platform of claim 1, wherein: in the channel unit, the radio frequency front end module comprises a radio frequency receiving front end module and a radio frequency sending front end module;
the radio frequency receiving front-end processing module comprises a band-pass filter, an adjustable attenuator and a fixed amplifier, a radio frequency signal is filtered by the band-pass filter, then sequentially passes through the adjustable attenuator and the fixed amplifier, and after the signal amplitude is adjusted, the radio frequency signal enters the digital-to-analog conversion module;
the radio frequency transmitting front-end processing module comprises a band-pass filter, an adjustable amplifier and a wave band filter; the radio frequency signal sent by the digital-to-analog conversion module is transmitted to the radio frequency signal after being processed by the band-pass filter, the adjustable amplifier and the band filter in sequence.
4. The short-wave communication technology verification universal hardware platform as claimed in claim 1, wherein in the master control unit, an external interface of the System On Chip (SOC) module comprises: audio interface, data interface, display interface, sky tone interface and power amplifier interface.
5. The short wave communication technology validation generic hardware platform of claim 1 or 4, characterized in that: the specific steps of the programmable logic PL submodule and the external interface management main control unit are as follows: the audio interface is managed through a serial peripheral interface SPI, and the data interface, the display interface, the antenna interface and the power amplifier interface are managed through a UART (universal asynchronous receiver transmitter), a display interface, a sky tone interface and a power amplifier interface.
6. The short wave communication technology validation generic hardware platform of claim 1, wherein: the short-wave communication technology verification general hardware platform further comprises a clock management unit.
7. The short wave communication technology validation generic hardware platform of claim 1, wherein: the short-wave communication technology verification general hardware platform further comprises a power management unit.
8. A signal processing method for verifying a universal hardware platform based on the short-wave communication technology of claim 1 is characterized by comprising the following three processing steps:
(1) a received signal processing step: the radio frequency signal is processed by a radio frequency receiving front end module of the channel unit, the processed radio frequency signal is sent to an analog-to-digital converter (ADC) for direct sampling and digitization, then is subjected to digital mixing down-conversion with a direct digital frequency synthesis DDS signal of a Field Programmable Gate Array (FPGA) module, and a digital baseband signal is output; the digital baseband signals are sent to a DSP module of a business unit through a high-speed serial bus SRIO for demodulation, the demodulated digital baseband signals are sent to a system-on-chip SOC module of a main control unit through a switching chip unit SW through the high-speed serial bus SRIO, and the system-on-chip SOC module sends the digital baseband signals to an external interface through a serial peripheral interface SPI or an asynchronous receiving and transmitting transmitter UART;
(2) a transmission signal processing step: the digital baseband signal is sent to a system-on-chip SOC module of a main control unit through an external interface of the system-on-chip SOC module, then is sent to a digital signal processor DSP module of a service unit through a high-speed serial bus SRIO interface by a switching chip unit SW for modulation, and the modulated digital baseband signal is sent to a field programmable gate array FPGA module of a channel unit through the high-speed serial bus SRIO interface for digital up-conversion processing and digital signal output; the digital signal is mixed with a direct digital frequency synthesis DDS signal generated by a field programmable gate array FPGA module, the mixed digital signal is changed into a radio frequency signal through a digital-to-analog converter DAC, and the radio frequency signal is sent through a radio frequency sending front end module;
(3) the main control part comprises the following signal processing steps: the digital signals of the main control part comprise control signals and feedback signals, wherein the control signals are issued to a system-on-chip SOC module of the main control unit through an external interface of the system-on-chip SOC module, a programmable logic PL sub-module in the system-on-chip SOC module receives the control signals and forwards the control signals to a processing system PS sub-module, and the processing system PS sub-module completes analysis of the control signals; the feedback signal is issued to the SOC module of the main control unit through an external interface of the SOC module, a programmable logic PL submodule in the SOC module receives the feedback signal and forwards the feedback signal to a processing system PS submodule, and the processing system PS submodule completes analysis of the feedback signal.
9. The signal processing method according to claim 8, characterized in that: in the received signal processing step, the sampling rate of the analog-to-digital converter ADC is 100 MSPS.
10. The signal processing method according to claim 8, characterized in that: in the received signal processing step, the total decimation multiple of the mixing down-conversion is 12500.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116774644A (en) * | 2023-08-17 | 2023-09-19 | 武汉世炬信息技术有限公司 | Industrial automation control system and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080003971A1 (en) * | 2006-06-30 | 2008-01-03 | Nokia Corporation | Multi-function passive frequency mixer |
| CN103414484A (en) * | 2013-07-05 | 2013-11-27 | 熊猫电子集团有限公司 | Short-wave four-channel integrated channel machine |
| CN104158561A (en) * | 2014-08-12 | 2014-11-19 | 西安烽火电子科技有限责任公司 | Short wave frequency hopping signal processing method |
| CN109347504A (en) * | 2018-09-26 | 2019-02-15 | 西安烽火电子科技有限责任公司 | A kind of short-wave radio frequency digital processing system |
-
2022
- 2022-02-21 CN CN202210158667.9A patent/CN114598348B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080003971A1 (en) * | 2006-06-30 | 2008-01-03 | Nokia Corporation | Multi-function passive frequency mixer |
| CN103414484A (en) * | 2013-07-05 | 2013-11-27 | 熊猫电子集团有限公司 | Short-wave four-channel integrated channel machine |
| CN104158561A (en) * | 2014-08-12 | 2014-11-19 | 西安烽火电子科技有限责任公司 | Short wave frequency hopping signal processing method |
| CN109347504A (en) * | 2018-09-26 | 2019-02-15 | 西安烽火电子科技有限责任公司 | A kind of short-wave radio frequency digital processing system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116774644A (en) * | 2023-08-17 | 2023-09-19 | 武汉世炬信息技术有限公司 | Industrial automation control system and method |
| CN116774644B (en) * | 2023-08-17 | 2023-12-22 | 武汉世炬信息技术有限公司 | Industrial automation control system and method |
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