CN109344099B - FPGA application system wireless debugging download device - Google Patents

Abstract

The invention discloses a wireless debugging and downloading device for an FPGA application system, comprising: a debugging computer terminal, which is used to realize the conversion from USB to JTAG through a single-channel high-speed USB to multi-function UART/FIFO chip, and convert and output general JTAG signals TMS and TCK. , TDO and TDI, JTAG signals TMS, TCK and TDO are modulated in ASK mode through ultra-high frequency carrier, and after amplifying processing, the output is sent through the microstrip antenna; FPGA system main control terminal, FPGA system main control terminal and debugging computer In the wireless communication of the terminal, each channel of the transmitting terminal completes the modulation and real-time transmission of the signal in ASK mode through different carrier frequencies, and the receiving terminal completes the signal selection of the corresponding channel through the band-pass filter, and completes the demodulation, amplification and shaping. The device effectively guarantees the real-time performance of the JTAG signal and has the same effect as wired connection debugging.

Description

FPGA application system wireless debugging download device

technical field

The invention relates to the related technical field of FPGA (Field-Programmable Gate Array, field programmable gate array), in particular to a wireless debugging and downloading device for an FPGA application system.

Background technique

In the related art, (1) FPGA downloader, an independent download and debug module, one end is connected to the debugging computer through a USB (Universal Serial Bus, Universal Serial Bus) cable, and the other end is connected to a JTAG (Joint TestAction Group, Joint TestAction Group) cable through a cable. Test behavior organization) interface interconnection, which is very common at present, and is more suitable for debugging in the process of single-board development. When downloading and debugging the FPGA application system, the module needs to be taken out separately or the JTAG interface should be reserved on the front panel of the module.

(2) On-board USB-JTAG downloader, the USB interface chip + protocol controller or USB-to-serial interface chip is directly installed on the module board, and only one USB interface is reserved for the outside world. computer interconnection.

(3) Wireless USB transmission technology, based on wireless operation, enables new standards, can use existing USB infrastructure to achieve wireless transmission, conforms to USB specifications, and allows wireless devices and expansion ports to communicate under the USB protocol.

However, (1) the FPGA downloader needs to connect the USB cable and the JTAG cable when using it. The FPGA application system module needs to take out the module and supply power separately when debugging and downloading. Single-ended power supply has the risk of reverse power supply and short circuit. ;If the JTAG interface is reserved on the front panel of the module, you can directly connect the JTAG cable to the reserved interface on the panel for debugging. The debugging interface needs to be well designed for electrostatic protection to avoid damage to the control device during the long-term plugging and unplugging process. The application of the panel debugging interface cannot meet the requirements. EMC design requirements for the system.

(2) The on-board USB-JTAG downloader requires each board module to be designed on the board. The debugger does not need to bring his own FPGA downloader, and can directly debug and download through the USB cable interconnection. It is more convenient to use, but each board The USB-JTAG downloader needs to be designed on the card module, which will occupy a certain space, increase the power consumption of the board, and cause waste of resources, and the USB interface will occupy the panel space at the same time.

(3) To realize online download and debug module based on wireless USB transmission technology, it is necessary to send the USB interface protocol data wirelessly, which includes a lot of USB protocol information, which has high requirements on the transmission carrier frequency and bandwidth, and will carry Due to the long delay, the debugging tool cannot find the device or get a response in time; the receiving end needs to parse the USB protocol information and convert it into JTAG information, which increases the difficulty of the design; this method can only implement two wireless USB For transmission between terminals, if you need to connect multiple devices at the same time, you need to connect multiple wireless USB terminals on the debugging computer, which occupies more USB ports. If you use MA-USB technology, you need to get MA-USB certification, and you need an operating system. driver update support.

The related technology mainly adopts the wired way to realize downloading and debugging, and the wireless USB transmission technology has not been well supported and applied at present.

SUMMARY OF THE INVENTION

This application is made based on the inventor's knowledge and discovery of the following issues:

In a system integration environment in which multiple FPGAs and multiple boards work together, each FPGA involves online debugging and code download and curing, and each download link needs to be connected to the debugging computer through a USB cable, so that the computer can be connected to the computer. When debugging data transmission between devices, it is necessary to constantly plug and unplug to switch between different download links during debugging. It is very inconvenient to use in some special applications. For example, after the system chassis is placed on the shelf, it is very inconvenient to plug and unplug the USB cable. At the same time, the length of the cable is increased, resulting in serious attenuation of the transmission signal, resulting in unstable online debugging for a long time and a large amount of data download. ; If the system chassis is designed to be rear-plugged, it is inconvenient to move the cabinet, and it will be very inconvenient to plug and unplug cables. At the same time, the interconnection between devices through debugging cables will cause the isolation equipment to share the ground, causing the equipment to work abnormally.

The FPGA application system involves multiple FPGAs working together and multiple modules working at the same time. If you switch cables to debug and download the FPGA in a single module, the debugging efficiency will be reduced. If there are multiple modules of the same model at the same time, it is easy to make the devices difficult to distinguish. , which brings great inconvenience to debugging.

Combined with system integration technology and general VPX, CPCI (Compact Peripheral Component Interconnect, compact PCI) and other system specifications, the automatic serial connection of the system debugging download link and the wireless transmission of JTAG signals in the present invention are added to realize the system multi-device debugging and downloading device without physical connection. .

All FPGAs complete the code loading and online debugging of the device through the JTAG interface protocol. In the standard JTAG interface, the mode selection TMS and clock TCK can be driven by one, and the data output TDO of the upper-level device is connected to the data input TDI of the next level. The chain method realizes the serial connection of multiple devices, and finally aggregates them into a JTAG interface, which is interconnected with the debugging computer through wireless transmission. The JTAG interface of multiple FPGAs on a single module, the externally reserved JTAG interface and the backplane JTAG interface defined by the general specification are intelligently managed through CPLD (Complex Programmable Logic Device, complex programmable logic device), and automatically determine whether the wireless USB device is connected. Whether the module is the system master or not, the adaptive concatenation of the JTAG link.

The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

Therefore, the purpose of the present invention is to provide a wireless debugging and downloading device for an FPGA application system, which effectively ensures the real-time nature of the JTAG signal, responds in a timely manner during debugging, and has the same effect as wired connection debugging.

In order to achieve the above object, an embodiment of the present invention proposes a wireless debugging and downloading device for an FPGA application system, including: a debugging computer end, used for converting USB to JTAG through a single-channel high-speed USB to multi-function UART/FIFO chip, and converting Output general JTAG signals TMS, TCK, TDO and TDI, the JTAG signals TMS, TCK and TDO are modulated by the ultra-high frequency carrier and ASK mode, after amplifying processing, the output is sent through the microstrip antenna; the main control terminal of the FPGA system , the main control end of the FPGA system communicates wirelessly with the debugging computer end, wherein each channel of the transmitting end completes the modulation and real-time transmission of the signal in ASK mode through different carrier frequencies, and the receiving end completes the corresponding channel through the band-pass filter. Signal selection, and complete demodulation, amplification and shaping.

The wireless debugging and downloading device of the FPGA application system according to the embodiment of the present invention solves the inconvenience and problems caused by the wired connection in use by transmitting the JTAG signal wirelessly. The modulation and real-time transmission of the signal are completed in ASK mode through different carrier frequencies. The receiving end completes the signal selection of the corresponding channel through the band-pass filter, and completes the demodulation, amplification and shaping processing. The entire wireless transmission process does not involve the communication protocol between devices Therefore, the real-time performance of JTAG signal is effectively guaranteed, and the response is timely during debugging, which has the same effect as wired connection debugging.

In addition, the device for wireless debugging and downloading of the FPGA application system according to the foregoing embodiments of the present invention may also have the following additional technical features:

Further, in an embodiment of the present invention, the debugging computer terminal is powered by a USB port, and in a preset working condition, powered by an external power supply mode.

Further, in an embodiment of the present invention, the JTAG signal on the debugging computer side uses different carrier frequencies for signal real-time transmission, and the carrier frequencies include 315MHz, 1200MHz, 433MHz and 868.3MHz.

Further, in an embodiment of the present invention, it also includes: connecting multiple FPGA devices in series on the backplane, used for JTAG signals defined by each module slot on the system backplane, and realizing the series connection of data channels through TDO and TDI in series, TMS It is connected with TCK in a one-drive-multiple way.

Further, in an embodiment of the present invention, it also includes: multiple FPGA devices are connected in series wirelessly, each module in the system is designed with a JTAG wireless transmission function, and the local oscillator frequency of the TDO ultra-high frequency transmission channel and the TDI ultra-high frequency receiving channel are selected. Channel bandpass filter parameters for wireless connection between two modules TDO and TDI.

Further, in an embodiment of the present invention, the modulation principle of ASK is adopted, and the amplitude of the carrier wave varies with the modulated JTAG signal, so as to generate communication between the debugging computer terminal and the FPGA system main control terminal.

Further, in an embodiment of the present invention, the wireless serial connection of JTAG links of multiple devices is completed by adding different carrier frequencies of the TDO signal and the TDI signal.

Additional aspects and advantages of the present invention will be set forth, in part, from the following description, and in part will be apparent from the following description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

1 is a schematic structural diagram of a wireless debugging and downloading device for an FPGA application system according to an embodiment of the present invention;

2 is a schematic structural diagram of a wireless serial connection of multiple FPGA devices according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an application of an FPGA system of a wireless download device according to an embodiment of the present invention.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to explain the present invention and should not be construed as limiting the present invention.

The following describes the device for wireless debugging and downloading of an FPGA application system according to an embodiment of the present invention with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of an apparatus for wireless debugging and downloading of an FPGA application system according to an embodiment of the present invention.

As shown in FIG. 1 , the wireless debugging and downloading device 10 of the FPGA application system includes: a debugging computer terminal 100 and a main control terminal 200 of the FPGA system.

Among them, the debugging computer terminal 100 is used to realize the conversion from USB to JTAG through the single-channel high-speed USB to multi-function UART/FIFO chip, and convert and output the general JTAG signals TMS, TCK, TDO and TDI, and the JTAG signals TMS, TCK and TDO pass the super The high-frequency carrier is modulated in ASK mode, and the output is sent through the microstrip antenna after amplification. FPGA system main control terminal 200 The FPGA system main control terminal communicates wirelessly with the debugging computer terminal, wherein each channel of the transmitting end completes the modulation and real-time transmission of the signal in ASK mode through different carrier frequencies, and the receiving end completes the corresponding channel through the band-pass filter. Signal selection, and complete demodulation, amplification and shaping. The apparatus 10 in the embodiment of the present invention does not involve the analysis of the communication protocol between devices during the entire wireless transmission process, effectively ensuring the real-time nature of the JTAG signal, and the timely response during debugging, and has the same effect as wired connection debugging.

Specifically, the debugging computer terminal 100 realizes the conversion from USB to JTAG through the single-channel high-speed USB to multi-function UART/FIFO chip, and converts and outputs the general JTAG signals TMS, TCK, TDO and TDI; the JTAG signals TMS, TCK and TDO pass the ultra-high The frequency carrier is modulated in ASK mode, and after being amplified, the output is sent through the microstrip antenna. The main control terminal 200 of the FPGA system is arranged on the main control slot control board in the FPGA application system, and can transmit and receive wirelessly with the debugging computer terminal through UHF, and connect the JTAG signal after demodulation, amplification and shaping to the system equipment. Among them, TCK is used to test the clock input; TDI is used to test the data input, and the data is input to the JTAG port through TDI; TDO is used to test the data output, and the data is output from the JTAG port through TDO; TMS is used to test the mode selection, and TMS is used to set the JTAG The port is in a certain test mode.

Further, in an embodiment of the present invention, the debugging computer terminal 100 is powered through a USB port, and under a preset working condition, powered by an external power supply mode.

In an embodiment of the present invention, the JTAG signal on the debugging computer side uses different carrier frequencies for real-time signal transmission, and the carrier frequencies include 315MHz, 1200MHz, 433MHz and 868.3MHz.

Specifically, the debugging computer terminal 100 is powered through the USB port. For example, when using long-distance download debugging, the power of the transmitter needs to be increased, and an external power supply mode can be used; the JTAG signal of the debugging computer terminal 100 uses four different carrier frequencies for real-time signal processing For transmission, the carrier frequency f1 is 315MHz, f2 is 1200MHz, f3 is 433MHz, and f4 is 868.3MHz.

Further, in an embodiment of the present invention, the device 10 of the embodiment of the present invention adopts the modulation principle of ASK, and the carrier amplitude changes with the modulation of the JTAG signal. communication.

In the embodiment of the present invention, through the JTAG link of the main control terminal 200 of the FPGA system, combined with the serial connection of the JTAG link in the system backplane, the JTAG link of the FPGA in all modules in the FPGA application system is finally realized in series, and finally the system is completed through wireless transmission. Downloading and debugging of all devices, this method is more suitable for FPGA application systems with a large number of devices.

Further, in an embodiment of the present invention, the wireless serial connection of JTAG links of multiple devices is completed by adding different carrier frequencies of the TDO signal and the TDI signal.

Specifically, in this embodiment of the present invention, by increasing the different carrier frequencies of TDO and TDI signals, the wireless serial connection of JTAG links of multiple devices is completed. In order to reduce interference between frequency bands, this method is more suitable for FPGA application systems with fewer devices. middle.

The FPGA system application of the wireless download device is shown in Figure 2. A board in the equipment chassis is used as the main control terminal 200 of the FPGA system, which is responsible for the transmission and reception of wireless JTAG signals. The debugging computer terminal 100 is connected to the wireless debugging download device through USB to realize the FPGA application. The online debugging and download function of the FPGA of the system.

Further, in an embodiment of the present invention, as shown in FIG. 1 , the apparatus 10 in the embodiment of the present invention further includes: a multi-FPGA device backplane series connection 300 . Among them, the multi-FPGA device backplane series 300 is used for the JTAG signal defined by each module slot on the system backplane, and the data channel is connected in series through TDO and TDI. TMS and TCK are connected in a one-drive-many manner.

Further, in an embodiment of the present invention, as shown in FIG. 3 , the apparatus 10 in the embodiment of the present invention further includes: wireless serial connection of multiple FPGA devices. Among them, multiple FPGA devices are wirelessly connected in series, and each module in the system is designed with JTAG wireless transmission function. By selecting the local oscillator frequency of the TDO ultra-high frequency transmission channel and the band-pass filter parameters of the TDI ultra-high frequency receiving channel, the two modules TDO and Wireless connection between TDIs.

In addition, in the FPGA application system, the module is inserted into the automatic detection, and the JTAG link of the corresponding module on the backplane is automatically connected in series by monitoring. Each module in the system is designed with JTAG master/slave mode detection signal, the system master control terminal JTAG master mode, the master control terminal controls other slot modules to be slave mode, and connected in series through the backplane.

The embodiment of the present invention has the following beneficial effects:

(1) Solve the inconvenience and limitations caused by wired debugging.

(2) In the application system, it is only necessary to design wireless JTAG on the main control end to debug and download the FPGA in the entire system module.

(3) It is no longer considered whether the level matches when the JTAG is connected, and the device link is no longer damaged due to the level mismatch.

(4) The selection of frequency bands will not affect general wireless devices.

(5) When not in use, you can choose to turn off the JTAG wireless transmission function to reduce power consumption.

(6) When debugging the equipment, it can be far away from the noise caused by the system cooling fan, etc., and improve the debugging efficiency.

According to the wireless debugging and downloading device of the FPGA application system proposed by the embodiment of the present invention, the inconvenience and problems caused by wired connection in use are solved by wirelessly transmitting JTAG signals. Each channel completes signal modulation and real-time transmission in ASK mode through different carrier frequencies. The receiving end completes the signal selection of the corresponding channel through a band-pass filter, and completes demodulation, amplification and shaping processing. The entire wireless transmission process does not involve equipment. The analysis of the communication protocol effectively guarantees the real-time nature of the JTAG signal, and the response is timely during debugging, which has the same effect as the wired connection debugging.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

Although the embodiments of the present invention have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present invention. Embodiments are subject to variations, modifications, substitutions and variations.

Claims (7)

1. The utility model provides a wireless debugging download apparatus of FPGA application system which characterized in that includes:

the debugging computer terminal is used for converting a single-channel high-speed USB into a multifunctional UART/FIFO chip to realize conversion from the USB to the JTAG and converting and outputting universal JTAG signals TMS, TCK, TDO and TDI, wherein the JTAG signals TMS, TCK and TDO are modulated in an ASK mode through ultrahigh frequency carrier waves and are transmitted and output through a microstrip antenna after being amplified;

the FPGA system main control end is in wireless communication with the debugging computer end, wherein each path of the sending end completes signal modulation and real-time sending in an ASK mode through different carrier frequencies, and the receiving end completes signal selection of a corresponding channel through a band-pass filter and completes demodulation, amplification and shaping processing.

2. The FPGA application system wireless debugging and downloading device of claim 1, wherein the debugging computer terminal is powered by a USB port and is powered by an external power supply mode when the transmission power needs to be increased to meet remote debugging.

3. The wireless debugging and downloading device of claim 2, wherein the JTAG signal of the debugging computer terminal uses different carrier frequencies for signal real-time transmission, and the carrier frequencies include 315MHz, 1200MHz, 433MHz and 868.3 MHz.

4. The FPGA application system wireless debugging downloading device of claim 1, further comprising:

the multi-FPGA equipment backplane is connected in series and used for realizing series connection of data channels through JTAG signals defined by each module slot position of the system backplane and through TDO and TDI series connection, and the TMS and the TCK are connected in a one-drive-multi mode.

5. The FPGA application system wireless debugging downloading device of claim 4, further comprising:

the multiple FPGA devices are connected in series in a wireless mode, JTAG wireless transmission functions are designed for all modules in the system, and wireless connection between the TDO and the TDI is achieved by selecting the local oscillation frequency of the TDO ultrahigh frequency transmitting channel and the band-pass filter parameters of the TDI ultrahigh frequency receiving channel.

6. The FPGA application system wireless debugging download device of claim 1, wherein the amplitude of the carrier varies with the modulation of the JTAG signal by using ASK modulation principle to generate communication between the debugging computer terminal and the FPGA system main control terminal.

7. The FPGA application system wireless debugging download apparatus of claim 1, wherein the wireless serial connection of JTAG links of multiple devices is completed by adding different carrier frequencies of TDO signal and TDI signal.

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