CN108490803A - A kind of test emulation system - Google Patents
A kind of test emulation system Download PDFInfo
- Publication number
- CN108490803A CN108490803A CN201810123822.7A CN201810123822A CN108490803A CN 108490803 A CN108490803 A CN 108490803A CN 201810123822 A CN201810123822 A CN 201810123822A CN 108490803 A CN108490803 A CN 108490803A
- Authority
- CN
- China
- Prior art keywords
- signal processing
- gate array
- processing module
- digital signal
- programmable gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B17/00—Systems involving the use of models or simulators of said systems
- G05B17/02—Systems involving the use of models or simulators of said systems electric
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Logic Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention provides a kind of test emulation system, it includes two CPCI industrial personal computers and CPCI computers, general signal processing platform is loaded on every industrial personal computer as data processing unit, it is attached by the front panel of CPCI industrial personal computers between general signal processing platform, connecting interface includes that the output of 10MHz system clocks, the input of 10MHz clocks and GTH/GTX transmit and receive interface, each general signal processing platform is connected by pci interface chip PLX9054 with the CPCI computers, is local bus agreement by pci bus protocol conversion.The present invention can replace front-end collection, output circuit, expansion interface type and quantity as needed；Generation broadband signal can be received, radio frequency bandpass sampling can be directly carried out, be more suitable for the demand of software radio, it is sufficient to meet the needs of common observing and controlling, communication, Radar Signal Processing algorithm.
Description
Technical field
The present invention relates to communication device, specifically a kind of test emulation system.
Background technology
The structure type of compact PCI (Compact Peripheral Component Interconnect, CPCI),
It is a kind of bus interface standards that International Industry computer manufacture person federation puts forward in 1994, is to be with PCI electrical codes
The High performance industrial bus of standard.The CPU and peripheral hardware of CPCI is identical, and the use of CPCI systems and biography with standard PCI
The identical chip of system pci system, fire wall and related software.One standard PCI plug-in card is converted to CPCI plug-in cards to be almost not required to
It redesigns, as long as physically redistributing.The electrical code of cpci bus=pci bus+standard needle in brief
Hole connector (IEC-1076-4-101)+Eurocard specification (IEC297/IEEE 1011.1).
The appearance of CPCI not only allows many originally technologies based on PC such as CPU, hard disk and matured product that can continue
Using also due to having done significant improvement in places such as interfaces so that had using the server of CPCI technologies, industrial PC etc.
High reliability, highdensity advantage.CPCI is the High performance industrial bus developed based on PCI electrical codes, is suitable for 3U and 6U
The circuit plugboard of height designs.CPCI circuit plugboards are inserted into cabinet from front, and the outlet of I/O data can be connecing on front panel
The backboard of mouth or cabinet.CPCI technologies are by being transformed on PCI technical foundation, and specific there are three aspects：When
Continue to use PCI local bus technologies；Second is that abandon PCI traditional mechanical structures, using instead can by the height of 20 years practice tests
By European card structure, radiating condition is improved, anti-vibrating and impact ability is improved, meets EMC Requirements；Third, abandoning
The golden finger type interconnection mode of PCI uses the pin hole connector of 2mm density instead, has air-tightness, anti-corrosive properties, further improves
Reliability, and increase load capacity.CPCI has hot-swappable, high open, high reliability.It is most prominent in CPCI technologies
Go out, most attraction the characteristics of be hot plug.In short, being exactly to extract or be inserted under conditions of operating system does not power off
Functional template, a kind of technology of the normal work without destroying system.Hot plug is always the requirement of telecommunications application, is also each
A industrial automation system is craved for.Its realization is：The pin contact pin of three kinds of different lengths is used in structure so that template
When inserting or pull out, power supply and ground connection, pci bus signal, hot plug enabling signal sequentially carry out；Using Bus isolation device and
The soft start of power supply；On software, operating system will have plug-and-play feature.At present cpci bus hot plug technology from
Basic hot-swap technology develops to high availability direction.
With the diversification of the market demand, for complicated circuit design, more stringent requirements are proposed, is not difficult to find out very much
When changed when certain specific small functional requirements, one piece of huge circuit version of function has resulted in the wasting of resources, and
And also result in corresponding economic loss.It is designed based on support plate and FMC subcard interconnection architectures, user demand not only may be implemented
A variety of independent individual event functions, but also broken the limitation to the element area of subcard pcb board so that design work is cleverer
It is living, it is required to meet the different of user.
FMC standards describe a general module, it is with a certain range of application, and environment and market are target.
The standard is developed by the alliance of company including FPGA manufacturers and end user, it is intended to provide standard to carry the FPGA on card
Subcard size, connector and module interface.I/O interfaces are detached with FPGA in this way, not only simplify I/O interface moulds
Block designs, while also maximising the recycling rate of waterused for carrying card.FMC standards with using PCI, CPCI, PCI-X, PCI-E or
The complex interfaces such as Serial RapidIO are connected to PMC with the XMC standard differences for carrying card, and FMC standards only require core I/O transmitting-receivings
Device circuit is connected directly to the FPGA carried on card.The design of FMC submodules, by cancelling fixed protocol, minimum system
Support and flexible pin assignment, reduce the energy and resource of design to the maximum extent.Efficiency can be improved by doing so, and
Many significant advantages are brought in design reusing, data throughout, more I/O, compatibility, stability etc..
But observing and controlling or there has been no in the prior art for radar communication field mutually tie above-mentioned CPCI with FMC boards
It closes, with using the system or platform of the two respective advantages, that there are individual event functions is respectively independent for existing test emulation system,
Component side accumulates in limitation, the problems such as cannot meeting multiple demand.
Invention content
In view of the above-mentioned problems in the prior art, the present invention provides a kind of test emulation system.
Test emulation system of the present invention selects the design based on CPCI support plates Yu FMC daughter board interconnection architectures, not only
A variety of independent individual event functions of user demand may be implemented, but also broken the limitation to the element area of subcard pcb board, make
Design work is more flexible, required to meet the different of user.
The present invention uses a kind of test emulation system comprising two CPCI industrial personal computers and CPCI computers, described in every
General signal processing platform is loaded on industrial personal computer as data processing unit, passes through CPCI between the general signal processing platform
The front panel of industrial personal computer is attached, connecting interface include 10MHz system clocks export 1 tunnel, 10MHz clocks input 1 tunnel and
GTH/GTX transmits and receives interface, and each general signal processing platform passes through pci interface chip PLX9054 and the CPCI
Computer is connected, and is local bus agreement by pci bus protocol conversion.
Preferably, the general signal processing platform includes CPCI support plates, the CPCI support plates include field-programmable
An intermediate frequency FMC daughter boards and a high speed FMC are installed on described two FMC slots position in gate array and two FMC mounting grooves positions respectively
Daughter board, the intermediate frequency FMC daughter boards include 1 road intermediate frequency output interface, 2 road intermediate frequency input interfaces and bandpass filter and intermediate frequency
Amplifier；The high speed FMC daughter boards include 4 road 720M intermediate frequencies output interfaces, 2 road 720M intermediate frequencies input interfaces and bandpass filtering
Device.
Preferably, in the intermediate frequency FMC daughter boards, analog-digital converter therein selects the 16-bit's of twin-channel TI
ADS42LB69, the ADS42LB69 maximums sample frequency are that the full amplitude of 250MSPS inputs is 2.5Vpp；Intermediate frequency output interface is suitable
It is exported with 70M intermediate frequencies and is realized by using digital analog converter device AD9788, externally input clock can be passed through inside
It is the digital analog converter that there are 16Bit data to input that work clock, the AD9788 are used as after PLL frequencys multiplication, and inside can carry out
2/4/8 times of interpolation and filtering have multiple-working mode.
Preferably, it is 102MHz that jump signal bandwidth is expanded in the input of the intermediate frequency input interface in the high speed FMC daughter boards,
Digitlization to inputting echo-signal is realized using the structure of intermediate frequency quadrature demodulator and analog-digital converter, wherein intermediate frequency is just
The ADRF6850 for handing over demodulator selection ADI companies, inside be integrated with can fractional frequency division PLL and VCO, only need to provide frequency
With reference to that can generate local mixing carrier wave in inside, from external input difference carrier, analog-digital converter chip selects ADI companies
AD9691, is binary channels, 14,1.25GSPS analog-digital converters, built-in piece internal inner ring and sampling hold circuit, kernel
Using multistage, differential pipeline framework, and be integrated with output error correction logic, the AD9691 support by SPI interface to its into
Row parameter configuration, including programmable-gain, sample-offset, sample offset etc., SPI configuration pins and field programmable gate array phase
Even, running parameter configuration management and status monitoring are carried out to it by field programmable gate array.
Preferably, the medium frequency output end mouth in the high speed FMC daughter boards uses intermediate frequency quadrature demodulator and analog-to-digital conversion
The structure of device, the selection of Low Medium Frequency digital analog converter pio chip using ADI companies AD9144, be four-way, 16, it is high dynamic
State range digital analog converter provides 2.8GSPS highest sampling rates, supports that input data rate is more than 1GSPS, has low spurious
It is designed with distortion, supports double DAC patterns, multi-chip synchronization, fixed delay, number generator delay compensation, when built-in phaselocked loop
Clock frequency multiplier and digital inverse sinc filter, also provide SPI interface, allow to be programmed inner parameter and readback, wherein
SPI configuration pins are connected with the XC6SLX100 of field programmable gate array, and work ginseng is carried out to it by field programmable gate array
Number configuration management and status monitoring；The ADRF6720-27 of mating quadrature modulator selection ADI companies with AD9144, including
Portion be integrated with can fractional frequency division PLL and VCO.
Preferably, the CPCI support plates further include 4 road low speed DA output interfaces, it is a digital signal processing module, one multiple
Miscellaneous programmable logic device, a synchronous DRAM and Clock management chip, wherein the complex programmable logic
Device is used for the Configuration Online to the field programmable gate array and the digital signal processing module, work clock on support plate
It configuration and synchronizes the dynamic RAM by external and is connected on the EMIF mouths of the digital signal processing module,
In, the EMIF interfaces can realize the connection of the digital signal processing module and different kinds of memory, and the scene can
Programming gate array is also connected to the EMIF mouthfuls of the digital signal processing module so that the digital signal processing module energy
The internal resource for enough accessing the field programmable gate array further includes identical 32 tunnel of LVTTL input/output interfaces of structure, 16
The input of 10M clocks and 1 road 10M clocks output outside the identical LVDS input/output interfaces of line structure, 1 tunnel.
Preferably, the digital signal processing module is the floating-point operation digital signal processing module of TI companies, HPI
Interface is connected with the Complex Programmable Logic Devices, on the EMIF mouths of the digital signal processing module plug-in two pieces it is external
The dynamic RAM is simultaneously connected with field programmable gate array simultaneously, and the program of the digital signal processing module passes through
Described HPI mouthfuls is configured, and described HPI mouthfuls is directly connected with the Complex Programmable Logic Devices.
Preferably, synchronous DRAM described in the digital signal processing module configuration 128M BYTE pieces, together
The EMIF interfaces of Shi Suoshu digital signal processing modules are connected on the I/O pins of the field programmable gate array, for visiting
Ask the internal resource of the field programmable gate array, the digital signal processing module is to the synchronous DRAM
Access with the field programmable gate array is distinguished by chip selection signal, and the digital signal processing module is good to floating
Points are handled and completion status converts the control of more complicated process, are mainly used for ranging processing unit distance
It resolves.
Preferably, further include a FLASH memory, for store the configuration information of the field programmable gate array with
And the calibration information of board, the FLASH memory select the FLASH memory ST39VF6401 of 64M Bit, when configuration, needs
The data in FLASH can be updated by pci interface.
Preferably, Complex Programmable Logic Devices configuration ground is for grasping pci bus, address bus into row decoding
Make, carrying out local decoding by the Complex Programmable Logic Devices enables to computer that can realize institute by pci bus
State the dynamic load of field programmable gate array and the digital signal processing module firmware program, the complex programmable logic
Device has the work clock of itself.
Test emulation system of the present invention is relatively advanced in similar-type products, is mainly manifested in following side
Face：
(1) it is directed to no communication system, the analog circuit of front end has the variation demand of bigger, general signal processing flat
There are two FMC interfaces for platform tool, can replace front-end collection, output circuit, expansion interface type and quantity as needed；
(2) high speed FMC daughter boards front end carries Up/Down Conversion device, Up/Down Conversion frequency coverage L and S-band, in simple application
In can directly transmit and receive radiofrequency signal, without individually buying special Up/Down Conversion device, save cost and space, advantage be bright
It is aobvious.The function does not have on original platform.
(3) there is high-speed AD, DA in high speed acquisition board, generation broadband signal can be received, can directly carry out radio frequency band
Logical sampling, is more suitable for the demand of software radio, this index is in forefront in existing market available data processing platform；It adopts
With high-performance Vritex 7XC7SX690T FPGA, data-handling capacity is powerful, flat in data processing currently sold on the market
Forefront is in platform, it is sufficient to meet the needs of common observing and controlling, communication, Radar Signal Processing algorithm.
Description of the drawings
Fig. 1 is the structure chart of general signal processing platform in test emulation system of the present invention；
Fig. 2 is the front-end circuit figure of ADS42LB69 in general signal processing platform of the present invention；
Fig. 3 is the uplink output front-end circuit figure of intermediate frequency output interface in general signal processing platform of the present invention；
Fig. 4 is output driver circuit figure in general signal processing platform of the present invention；
Fig. 5 is the schematic diagram that AD9788 clocks input in general signal processing platform of the present invention；
Fig. 6 is that binary channels DAC is connected with the signal of analog quadrature modulation in general signal processing platform of the present invention
Reference circuit figure.
Specific implementation mode
To make those skilled in the art more fully understand technical scheme of the present invention, below in conjunction with the accompanying drawings and specific embodiment party
Formula elaborates to the present invention.
The present embodiment is related to a kind of test emulation system, is generally used for observing and controlling or the signal of communication processing of radar
On, which includes two CPCI industrial personal computers and CPCI computers, and general signal processing is loaded on every industrial personal computer
Platform is as data processing unit, thought design of the test emulation system based on software radio, by loading different programs
It is used respectively as simulator on ground simulation device and star, different operating modes is realized by the algorithm kernel for loading different.
It is attached by the front panel of CPCI between general signal processing platform, when connecting interface includes 10MHz systems
Clock exports 1 tunnel, 10MHz clocks input 1 tunnel, and GTH/GTX transmits and receives each 7 pairs of interface.
Wherein, each general signal processing platform is connected by pci interface chip PLX9054 with CPCI computers 2, will
Pci bus protocol conversion is local bus agreement, and the local bus signal of pci interface chip output passes through complex programmable logic
Device 8 carries out address decoding, and pci bus is completed by Complex Programmable Logic Devices 8 to field programmable gate array 3 and number
The access of signal processing module 7HPI interfaces, completion add field programmable gate array 3 and 7 program of digital signal processing module
It carries so that computer can complete the update to firmware program by pci interface.
For general signal processing platform therein, in order to simplify design, preferably compatibility is realized, at universal signal
It needs to consider comprehensively when hardware design in platform so that general signal processing platform can be supported on ground simulation device and star
Two kinds of equipment of simulator, while each equipment can support incoherent/two-way Spread-spectrum TTC System, observing and controlling number to pass integrated body
System expands frequency-hopping mode, completely compatible on hardware configuration.Above-mentioned general signal processing platform can send intermediate-freuqncy signal, specifically
Including telecommand, distance measuring signal, telemetered signal, while receiving intermediate frequency signal, telemetered signal, distance measuring signal, distant is specifically included
Control instruction, additionally it is possible to generate and receive necessary auxiliary signal.
It further, should as shown in Figure 1, the general signal processing platform includes CPCI support plates 1 and CPCI computers 2
CPCI support plates 1 include field programmable gate array 3 (Field-Programmable Gate Array, FPGA) and two
FMC mounting grooves position installs an intermediate frequency FMC daughter boards 4 on the two FMC slots positions, can realize 70M input and output and one respectively
High speed FMC daughter boards 5, can realize 720M input and output, wherein intermediate frequency FMC daughter boards 4 include 1 road intermediate frequency output interface, 2 tunnels
Intermediate frequency input interface and bandpass filter and intermediate frequency amplifier；High speed FMC daughter boards 5 include 4 road 720M intermediate frequencies output interfaces,
2 road 720M intermediate frequencies input interfaces and bandpass filter.Wherein, FMC refers to FPGA Mezzanine Card, be application range,
Adapt to environmental field and all very wide general module of market segment range.
Field programmable gate array 3 (Field-Programmable Gate Array, FPGA) is believed as main intermediate frequency
Number processing apparatus is responsible for control and access, the data acquisition and output of each front-end circuit, is the core of IF processing unit,
Preferably, the model of field programmable gate array 3, which is chosen to be Xilinx companies, releases 7 platforms of Vritex, concrete model is special
Door carried out the XC7SX690T of optimization for data processing.The configuration of field programmable gate array 3 ground is for completing to periphery device
The accessing time sequence of part controls；The processing to downlink signal is completed, remote signal and ranging information are demodulated；Complete uplink signal
It generates, generates ranging and telecontrol analog signal；Realize the acquisition and modulation to low-speed parallel DA input signals；Complete low-speed parallel
The generation and output of DA output signals；Complete the generation of the control voltage of front-end circuit AGC；It tests the generation of PCM signal and connects
It receives；Distance measuring signal sends and receives；Send the simulation of signal Doppler frequency；Number communication number sends and receives.
In order to complete the exterior arrangement of field programmable gate array 3, realizes in the case where not opening cabinet, can pass through
Pci interface carries out hardware maintenance and upgrading, field programmable gate array 3 to equipment can be configured to Slave by wire jumper
Select MAP (parallel) configuration mode (CPLD configurations) or JTAG/Boundary-Scan
Configuration mode use JTAG/Boundary-Scan pattern configurations when debugging, can use ChipScope tools
FPGA is debugged, equipment FPGA programs use SelectMAP (parallel) configuration after finalizing the design almost
mode。
In intermediate frequency FMC daughter boards 4, the circuit structure of intermediate frequency input interface is as shown in Fig. 2, analog-digital converter ADC therein
It is that the full amplitude of 250MSPS inputs is to select the ADS42LB69 of the 16-bit of twin-channel TI, ADS42LB69 maximum sample frequencys
2.5Vpp；The circuit structure of intermediate frequency output interface is as shown in figure 3, it is applicable in the output of 70M intermediate frequencies and by using Analog
The high-speed A/D converter device AD9788 of Devices companies is realized, can externally input clock be passed through internal PLL frequencys multiplication
It is used as work clock afterwards.AD9788 have 16Bit data input digital analog converter, inside can carry out 2/4/8 times of interpolation and
Filtering has multiple-working mode.The base band data that AD9788 will be fed into carries out interpolation and filtering first, then can be directly defeated
Go out or orthogonal modulation after export.Modulated simulation output is current mode difference output, and the electric current representative value of output is
21.4mA, and being set between 8.6mA~31.6mA loads as 50 Ω impedances, is 1 by impedance ratio：Become after 1 transformer
Single-ended signal, by the passive bandpass filters 7BM65-70/T35 filtering of 70MHz, passive filter uses and uplink intermediate frequency is defeated
Enter the identical bandpass filter in channel, after thering is the Insertion Loss of 0.9dB, bandpass filter output to do AC coupled, uses emitter following circuit
It drives, is exported after serial matching, driving circuit matches as shown in figure 4, exporting for 50 Ω series connection, therefore the also 6dB of output signal
Decaying.It can be set it is required that output power is 0dBm~-60dBm, because output is 50 Ω series connection matching therefore can bring declining for 6dB
Subtract.So the output power of bandpass filter should be because output bandpass filter has the decaying of 0.9dB, AD9788 outputs
Power it is corresponding should be 6.9dBm~-53.1dBm, electric current in the corresponding 50 Ω impedances of when peak power output 6.9dBm
For：
Retain certain redundancy, the maximum output current that AD9788 is arranged is 30mA, you can meet output peak power output
The requirement of 0dBm,
Electric current is in the corresponding 50 Ω impedances of -53.1dBm：
When maximum output current is 30mA, the DA bit wides that output -59.1dBm power needs in 50 Ω impedances are：
N is natural number, can be obtained after derivation：
Modulated signal (resolution ratio of loss 4Bit) is indicated using the 12Bit of DAC, is capable of providing enough resolution ratio and is indicated
Modulated signal, the problem of signal quality degradation will not be caused.
So disclosure satisfy that the requirement that can be set between output power 0dBm~-60dBm in technology requirement using AD9788.
AD9788 output minimum resolution be：
The minimum resolution of AD9788 outputs is much smaller than the adjustable requirement of output power 1dB step-lengths.When the reference of AD9788
Clock inputs in a differential manner, and interface form is as shown in Figure 5.
It in high speed FMC daughter boards 5, for high speed intermediate frequency input interface, is required according to technology, input expands jump signal bandwidth and is
102MHz.Difficulty and if signal sampling demand are realized in the design for considering radio frequency down-conversion unit, using intermediate frequency quadrature solution
The design structure of device and high-speed AD converter is adjusted to realize the digitlization to inputting echo-signal.For design constraint,
Intermediate frequency quadrature demodulator selects the ADRF6850 of ADI companies.This quadrature demodulator inside be integrated with can fractional frequency division PLL
And VCO, need to only provide frequency reference can generate local mixing carrier wave in inside；Also more excellent phase can makes an uproar spy from external input
The difference carrier of property.The RF of ADRF6850 inputs frequency range：100MHz to 1000MHz can with LO output interfaces
Integrated fractional-N divide PLL and VCO, input P1dB are 12dBm (when 0dB gains), and input IP3 is 22.5dBm (when 0dB gains),
Noise coefficient is 11dB, can also may be programmed HD3/IP3 adjustment in addition, use base band 1dB bandwidth for 250MHz (broadband mode) and
50MHz (narrow band mode).720M input signals, the selection of analog-digital converter chip are acquired using high-speed AD converter simultaneously
The AD9691 of ADI companies.AD9691 is a binary channels, 14,1.25GSPS analog-digital converters.Buffering in piece built in the device
Device and sampling hold circuit, double-channel analog/digital converter kernel are integrated with output error correction using multistage, differential pipeline framework
Logic.Each ADC all has wide bandwidth input, supports the IF signal samplings for being up to 1.5GHz.Key property includes realizing
JESD204B encodes serial digital output, is 1.9W, SFDR=77dBFS (340MHz), signal-to-noise ratio (SNR) per channel total power consumption
For 63.4dBFS (340MHz, AIN=-1.0dBFS), noise density is -152.6dBFS/Hz, DC power supply using 1.25V,
2.50V and 3.3V, it is 400 Ω, 200 Ω, 100 Ω to have 1.58V p-p difference full scale input voltages, flexible termination impedance
With 50 Ω difference, 1.5GHz can use simulation input full power bandwidth and 95dB channel separations/crosstalk.
AD9691 supports to carry out it parameter configuration by SPI interface, including programmable-gain, sample-offset, sampling are partially
Move etc..SPI configuration pins are connected with FPGA, and running parameter configuration management and status monitoring are carried out to it by FPGA.
For the high speed medium frequency output end mouth in high speed FMC daughter boards 5, since required output IF frequency is higher, such as
Fruit is realized in such a way that high-speed A/D converter directly exports has larger technical difficulty and risk, and components selection
Also it can be very limited.Therefore, the technical measures taken in this programme are first to be exported signal to one with digital analog converter
Then it is defeated to be converted to required IF spot by a suitable Low Medium Frequency fIF0 using quadrature modulator for the low intermediate frequency signal
Go out.Signal link is as follows：
In view of this system has distance measurement function, in radio frequency Closed loop operation, in order to avoid generating phase in transmission process
Position error, therefore be considered as the output IF spot consistent with input intermediate-freuqncy signal, i.e., export 2 road 1.5GHz to Radio Frequency Subsystem
Intermediate-freuqncy signal.For directly playing operating mode, when needing directly to export 600MHz intermediate-freuqncy signals, then it need to only change positive intermodulation
The local frequency of device processed.
The selection of Low Medium Frequency digital analog converter pio chip uses the AD9144 of ADI companies.AD9144 is a four-way, 16
Position, high dynamic range digital analog converter, provide 2.8GSPS highest sampling rates.Digital analog converter output is by optimization, Ke Yiyu
The ADRF672x analogue quadrature moducator seamless interfacings of ADI companies.It supports that input data rate is more than 1GSPS, proprietary low miscellaneous
It dissipates and is designed with distortion, SFDR=82dBc (when DC IF, -9dBFS) has 8 channel JESD204B interfaces, supports double DAC patterns
(when 2.8GSPS) supports multi-chip synchronization, fixed delay, number generator delay compensation, optional 1x, 2x, 4x, 8x interpolation filter
Wave device, with input signal power detection function, the emergency braking function for protecting downstream analog circuit, built-in high-performance,
Low noise phase-locked loop clock frequency multiplier, embedded digital inverse sinc filter, have low-power consumption, in particular 1.6W (1.6GSPS),
1.7W(2.0GSPS)。
In addition, AD9144 provides SPI interface, allow to be programmed inner parameter and readback.SPI configuration pins and scene
The XC6SLX100 of programmable gate array 3 is connected, and running parameter configuration management and shape are carried out to it by field programmable gate array 3
State monitors.
The ADRF6720-27 of mating quadrature modulator selection ADI companies with AD9144.ADRF6720-27 collects in inside
At can fractional frequency division PLL and VCO, therefore need not additionally configure individual VCO devices, only need to provide frequency reference signal i.e.
It can.The Specifeca tion speeification of ADRF6720-27 includes：RF reference frequency outputs are 400MHz to 3000MHz, internal LO frequencies model
It is 10.8dBm (2140MHz) to enclose for 356.25MHz to 2855MHz, output P1dB, and output IP3 is 31.1dBm (2140MHz),
Carrier feed is -44.3dBm (2140MHz), and sideband is suppressed to -40.8dBc (2,140MHz), and bottom of making an uproar is -159.5dBm/Hz
(2140MHz), base band 1dB modulation bandwidths>1000MHz, base band input bias level for 2.68V, power supply 3.3V/425mA, together
When the tunable baluns of integrated form RF, allow single-ended RF to export, there is multinuclear integrated form VCO and HD3/IP3 optimization, there is sideband
Inhibit and carrier feed optimizes.
When working in acquisition playback mode or when real-time convolution playback mode, simulator to output and input IF frequency equal
For 1.5Ghz, it should ensure that if demodulator and IF modulator use identical local oscillation signal at this time.It is taken in the design
Mode is that IF modulator ADRF6720-27 is enabled to work in internal local oscillator pattern, according to the system frequency of input with reference to generation institute
The local oscillation signal needed, and export to if demodulator ADRF6820, ADRF6820 and work in external local oscillator pattern.
AD9144 and ADRF6720-27 are provided which SPI interface, allow to be programmed inner parameter and readback.SPI is configured
Pin is connected with field programmable gate array 31XC6SLX100, and running parameter configuration is carried out to it by field programmable gate array 3
Management and status monitoring.The reference connection circuit of AD9122 and ADRF6720-27 is as shown in Figure 6：
In addition, the CPCI support plates 1 further include 4 road low speed DA output interfaces 6, in addition to field-programmable on CPCI support plates 1
Further include a digital signal processing module 7 (DSP), 8 (Complex of a Complex Programmable Logic Devices except gate array 3
Programmable Logic Device, CPLD), a synchronous DRAM 9 (SDRAM) and Clock management chip
10, wherein Complex Programmable Logic Devices 8 is used to match field programmable gate array 3 and the online of digital signal processing module 7
It sets, work clock configures and external synchronous DRAM 9 (SDRAM) is connected to Digital Signal Processing mould on support plate
On the EMIF mouths of block 7, wherein EMIF interfaces can realize digital signal processing module 7 and different kinds of memory (SRAM,
Flash RAM, DDR-RAM etc.) connection, in addition, field programmable gate array 3 is also connected to digital signal processing module 7
EMIF mouthfuls so that digital signal processing module 7 is able to access that the internal resource of field programmable gate array 3.
In addition, general signal processing platform further includes identical 32 tunnel of LVTTL input/output interfaces of structure (customization back plate number
Measure expansible), configuration ground is for monitoring the output of PCM data and clock, when exterior PC M modulation, PCM clocks and data it is defeated
Enter, which is also used as the input of external remote control signal and the input of test signal, such as：Pps pulse per second signal, it is locking-typed
Number, I, Q test signal etc..In order to handle high speed PCM signal, general signal processing platform further includes the identical LVDS of 16 line structures
Input/output interface (customization back plate quantity is expansible), is mainly used for the input of high-speed data and clock.
General signal processing platform further includes the input of 10M clocks and 1 road 10M clocks output outside 1 tunnel, all the way when 10.23M
Clock inputs and clock output, and (clock can be configured to one of all program-controlled system when being operated in the two of AD, DA, FPGA if needed
Other frequency points), input clock can be automatically selected according to the priority of setting using clock on external clock or plate,
It can be inputted using external clock clock by software control selections or clock that board is included is as the clock source of system.
The digital signal processing module 7 is the floating-point operation digital signal processing module of TI companies, the Digital Signal Processing
The HPI interfaces of module 7 are connected with Complex Programmable Logic Devices 8, which is preferably model
TMS320C6747 chips, plug-in two pieces of external EEPRAM on the EMIF mouths of digital signal processing module 7 are used for digital signal
Processing module 7 it is interior from extension, the EMIF mouths of digital signal processing module 7 are connected with field programmable gate array 3 simultaneously, are used for
The program of data exchange between field programmable gate array 3, digital signal processing module 7 is configured by HPI mouthfuls,
HPI mouthfuls are directly connected with Complex Programmable Logic Devices 8, are decoded by Complex Programmable Logic Devices 8, at such digital signal
The configuration of module 7 is managed there is no need to pass through 3 transfer of field programmable gate array, but digital signal processing module 7 is wanted just
Often work, it is also necessary to the configuration of field programmable gate array 3 is first completed, because the clock of digital signal processing module 7 is by existing
What field programmable gate array 3 provided enables a computer to update 7 program of digital signal processing module by pci interface, completes
The dynamic load of 7 program of digital signal processing module, in order to increase the processing capacity of digital signal processing module 7, for number letter
Number processing module 7 configures the outer synchronous DRAM 9 of 128M BYTE pieces, the number that synchronous DRAM 9 is connected to
On the EMIF interfaces of word signal processing module 7, while the EMIF interfaces of digital signal processing module 7 are connected to field programmable gate
On the I/O pins of array 3, for accessing 3 internal resource of field programmable gate array, digital signal processing module 7 is dynamic to synchronizing
The access of state random access memory 9 and field programmable gate array 3 is distinguished by chip selection signal.Digital signal processing module 7
It is good at handling floating number and completion status converts the control of more complicated process, it is single is mainly used for ranging processing
The resolving of first distance.
Signal processing platform further includes a FLASH memory 11, the configuration information for storing field programmable gate array 3
And the calibration information of board, FLASH memory 11 select FLASH memory --- the ST39VF6401 of 64M Bit.When configuration
It is required to update the data in FLASH by pci interface.
In order to which the data exchange realized between computer uses PLX9054 as pci interface chip, pci bus is completed
The conversion of agreement and local bus agreement.PLX9054 supports 32-bit data/address bus, supports dma operation, supports hardware interrupts.
With faster reading and writing data speed, the requirement of ground checkout equipment data exchange disclosure satisfy that.
Complex Programmable Logic Devices 8 (CPLD) configuration ground for pci bus, address bus into operations such as row decodings,
The main purpose locally decoded using Complex Programmable Logic Devices 8 is to enable a computer to realize by pci bus
The dynamic load of 7 firmware program of field programmable gate array 3 and digital signal processing module, the upgrading of the hardware of such equipment and
The switching of operating mode can update the configurator of hardware by way of pci bus load, do not have to open cabinet, can complete
The upgrading of equipment.In addition, Complex Programmable Logic Devices 8 also configure for completes the access to clock managing chip and initially
Change, the clock of system wants normal work, it is necessary to correct clock can be exported after correctly configuration, complexity can
Programmed logic device 8 has the work clock of itself, and powering on can complete to configure, and be configured by Complex Programmable Logic Devices 8
Complete Clock management chip, after system clock works normally, system could work normally；Complex Programmable Logic Devices 8 also needs
Complete the read-write to 3 internal register of field programmable gate array.
Certainly, the above is the preferred embodiment of the present invention, it is noted that for the ordinary skill of the art
For personnel, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of test emulation system comprising two CPCI industrial personal computers and CPCI computers (2) fill on every industrial personal computer
General signal processing platform is carried as data processing unit, between the general signal processing platform by CPCI industrial personal computers before
Panel is attached, and connecting interface includes that 10MHz system clocks export 1 tunnel, 10MHz clocks input 1 tunnel and GTH/GTX is sent
Receiving interface, each general signal processing platform pass through pci interface chip PLX9054 and the CPCI computers (2) phase
Even, it is local bus agreement by pci bus protocol conversion.
2. test emulation system according to claim 1, which is characterized in that the general signal processing platform includes CPCI
Support plate (1), the CPCI support plates (1) include field programmable gate array (3) and two FMC mounting grooves positions, described two FMC
One intermediate frequency FMC daughter boards (4) and a high speed FMC daughter boards (5) are installed respectively, the intermediate frequency FMC daughter boards (4) include 1 tunnel on slot position
Intermediate frequency output interface, 2 road intermediate frequency input interfaces and bandpass filter and intermediate frequency amplifier；High speed FMC daughter boards (5) packet
Include 4 road 720M intermediate frequencies output interfaces, 2 road 720M intermediate frequencies input interfaces and bandpass filter.
3. test emulation system according to claim 2, which is characterized in that in the intermediate frequency FMC daughter boards (4), wherein
Analog-digital converter select twin-channel TI 16-bit ADS42LB69, the ADS42LB69 maximums sample frequency is
The full amplitude of 250MSPS inputs is 2.5Vpp；Intermediate frequency output interface is applicable in the output of 70M intermediate frequencies and by using digital analog converter device
AD9788 realizations, can be by externally input clock by being used as work clock after internal PLL frequencys multiplication, and the AD9788 is that have
The digital analog converter of 16Bit data input, inside can carry out 2/4/8 times of interpolation and filtering, have multiple-working mode.
4. test emulation system according to claim 2, which is characterized in that the intermediate frequency in the high speed FMC daughter boards (5) is defeated
The input of incoming interface, which is expanded, jumps signal bandwidth as 102MHz, is realized using the structure of intermediate frequency quadrature demodulator and analog-digital converter
To inputting the digitlization of echo-signal, wherein intermediate frequency quadrature demodulator selects the ADRF6850 of ADI companies, is being internally integrated
Can fractional frequency division PLL and VCO, need to only provide frequency reference can generate local mixing carrier wave in inside, from external input
Difference carrier, analog-digital converter chip select the AD9691 of ADI companies, are binary channels, 14,1.25GSPS analog-to-digital conversions
Device, built-in piece internal inner ring and sampling hold circuit, kernel are integrated with output and are entangled using multistage, differential pipeline framework
Wrong logic, the AD9691 support to carry out it parameter configuration, including programmable-gain, sample-offset, sampling by SPI interface
Offset etc., SPI configuration pins are connected with field programmable gate array (3), are worked it by field programmable gate array (3)
Parameter configuration management and status monitoring.
5. test emulation system according to claim 4, which is characterized in that the intermediate frequency in the high speed FMC daughter boards (5) is defeated
Exit port uses the structure of intermediate frequency quadrature demodulator and analog-digital converter, the selection of Low Medium Frequency digital analog converter pio chip to use
The AD9144 of ADI companies is four-way, 16, high dynamic range digital analog converter, provides 2.8GSPS highest sampling rates,
It supports that input data rate is more than 1GSPS, there is low spurious to be designed with distortion, support double DAC patterns, multi-chip synchronous, fixed
Delay, number generator delay compensation, built-in phaselocked loop clock multiplier and digital inverse sinc filter, also provide SPI interface,
Allow to be programmed inner parameter and readback, wherein the XC6SLX100 of SPI configuration pins and field programmable gate array (3)
It is connected, running parameter configuration management and status monitoring is carried out to it by field programmable gate array (3)；It is mating just with AD9144
Quadrature modulator selects the ADRF6720-27 of ADI companies, inside be integrated with can fractional frequency division PLL and VCO.
6. test emulation system according to claim 2, which is characterized in that the CPCI support plates (1) further include 4 road low speed
DA output interfaces (6), a digital signal processing module (7), a Complex Programmable Logic Devices (8), a synchronous dynamic random are deposited
Reservoir (9) and Clock management chip (10), wherein the Complex Programmable Logic Devices (8) is for that can compile the scene
In journey gate array (3) and the Configuration Online of the digital signal processing module (7), support plate work clock configuration and will it is external together
It walks the dynamic RAM (9) to be connected on the EMIF mouths of the digital signal processing module (7), wherein the EMIF
Interface can realize the connection of the digital signal processing module (7) and different kinds of memory, the field-programmable gate array
Row (3) are also connected to the EMIF mouthfuls of the digital signal processing module (7) so that the digital signal processing module (7)
It is able to access that the internal resource of the field programmable gate array (3), further includes the identical LVTTL input/output interfaces of structure 32
Road, the identical LVDS input/output interfaces of 16 line structures, the 10M clocks input of 1 tunnel outside and 1 road 10M clocks output.
7. test emulation system according to claim 6, which is characterized in that the digital signal processing module (7) is TI
The floating-point operation digital signal processing module of company, HPI interfaces are connected with the Complex Programmable Logic Devices (8), described
On the EMIF mouths of digital signal processing module (7) the plug-in two pieces external dynamic RAMs (9) and simultaneously and scene
Programmable gate array (3) is connected, and the program of the digital signal processing module (7) is configured by described HPI mouthfuls, described
HPI mouthfuls are directly connected with the Complex Programmable Logic Devices (8).
8. test emulation system according to claim 7, which is characterized in that digital signal processing module (7) configuration
Synchronous DRAM (9) described in 128M BYTE pieces, while the EMIF interfaces of the digital signal processing module (7) connect
It is connected on the I/O pins of the field programmable gate array (3), the inside for accessing the field programmable gate array (3)
Resource, the digital signal processing module (7) is to the synchronous DRAM (9) and the field programmable gate array
(3) access is distinguished by chip selection signal, and the digital signal processing module (7) is good at handling floating number, with
And completion status converts the control of more complicated process, is mainly used for the resolving of ranging processing unit distance.
9. test emulation system according to claim 8, which is characterized in that further include a FLASH memory (11), be used for
Store the configuration information of the field programmable gate array (3) and the calibration information of board, FLASH memory (11) choosing
With the FLASH memory ST39VF6401 of 64M Bit, when configuration, is required to update the data in FLASH by pci interface.
10. test emulation system according to claim 9, which is characterized in that the Complex Programmable Logic Devices (8) is matched
It is used to setting carry out decoded operation to pci bus, address bus, be carried out by the Complex Programmable Logic Devices (8) local
Decoding enables to computer that can be realized by pci bus at the field programmable gate array (3) and the digital signal
The dynamic load of module (7) firmware program is managed, the Complex Programmable Logic Devices (8) has the work clock of itself.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810123822.7A CN108490803B (en) | 2018-02-07 | 2018-02-07 | Test simulation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810123822.7A CN108490803B (en) | 2018-02-07 | 2018-02-07 | Test simulation system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108490803A true CN108490803A (en) | 2018-09-04 |
| CN108490803B CN108490803B (en) | 2020-03-17 |
Family
ID=63344690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810123822.7A Active CN108490803B (en) | 2018-02-07 | 2018-02-07 | Test simulation system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108490803B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109710551A (en) * | 2018-12-28 | 2019-05-03 | 中国科学院长春光学精密机械与物理研究所 | A kind of injected simulation system based on FMC standard |
| CN111367259A (en) * | 2020-03-17 | 2020-07-03 | 四川九洲电器集团有限责任公司 | Low-cost digital signal processing module automatic testing device and method |
| CN111552659A (en) * | 2020-04-23 | 2020-08-18 | 上海航天电子有限公司 | Hot switching system of back picture peg based on CPCI framework |
| CN112463660A (en) * | 2020-12-11 | 2021-03-09 | 北京航天自动控制研究所 | Multifunctional real-time interaction system based on CPCI bus |
| CN115865688A (en) * | 2022-11-25 | 2023-03-28 | 天津光电通信技术有限公司 | Double-channel high-speed analog acquisition playback equipment |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102812797B (en) * | 2007-12-21 | 2010-04-14 | 北京理工雷科电子信息技术有限公司 | Generalized signal processing platform based on FPGA |
| CN103885919A (en) * | 2014-03-20 | 2014-06-25 | 北京航空航天大学 | Multi-DSP and multi-FPGA parallel processing system and implement method |
| CN204102126U (en) * | 2014-10-29 | 2015-01-14 | 天津市英贝特航天科技有限公司 | Based on the bus-structured Communication Card of ARINC429 |
| CN105278404A (en) * | 2015-09-18 | 2016-01-27 | 广州北航新兴产业技术研究院 | Base-band device based on software radio |
| CN105281783A (en) * | 2015-09-25 | 2016-01-27 | 中国船舶重工集团公司第七二六研究所 | Signal decoding unit based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and realization method for signal decoding unit based on FPGA and DSP |
| CN108491157A (en) * | 2018-02-07 | 2018-09-04 | 北京国电高科科技有限公司 | A kind of general signal processing platform |
| CN208477509U (en) * | 2018-02-07 | 2019-02-05 | 北京国电高科科技有限公司 | A kind of general signal processing platform |
-
2018
- 2018-02-07 CN CN201810123822.7A patent/CN108490803B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102812797B (en) * | 2007-12-21 | 2010-04-14 | 北京理工雷科电子信息技术有限公司 | Generalized signal processing platform based on FPGA |
| CN103885919A (en) * | 2014-03-20 | 2014-06-25 | 北京航空航天大学 | Multi-DSP and multi-FPGA parallel processing system and implement method |
| CN204102126U (en) * | 2014-10-29 | 2015-01-14 | 天津市英贝特航天科技有限公司 | Based on the bus-structured Communication Card of ARINC429 |
| CN105278404A (en) * | 2015-09-18 | 2016-01-27 | 广州北航新兴产业技术研究院 | Base-band device based on software radio |
| CN105281783A (en) * | 2015-09-25 | 2016-01-27 | 中国船舶重工集团公司第七二六研究所 | Signal decoding unit based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and realization method for signal decoding unit based on FPGA and DSP |
| CN108491157A (en) * | 2018-02-07 | 2018-09-04 | 北京国电高科科技有限公司 | A kind of general signal processing platform |
| CN208477509U (en) * | 2018-02-07 | 2019-02-05 | 北京国电高科科技有限公司 | A kind of general signal processing platform |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109710551A (en) * | 2018-12-28 | 2019-05-03 | 中国科学院长春光学精密机械与物理研究所 | A kind of injected simulation system based on FMC standard |
| CN111367259A (en) * | 2020-03-17 | 2020-07-03 | 四川九洲电器集团有限责任公司 | Low-cost digital signal processing module automatic testing device and method |
| CN111367259B (en) * | 2020-03-17 | 2021-09-14 | 四川九洲电器集团有限责任公司 | Low-cost digital signal processing module automatic testing device and method |
| CN111552659A (en) * | 2020-04-23 | 2020-08-18 | 上海航天电子有限公司 | Hot switching system of back picture peg based on CPCI framework |
| CN112463660A (en) * | 2020-12-11 | 2021-03-09 | 北京航天自动控制研究所 | Multifunctional real-time interaction system based on CPCI bus |
| CN112463660B (en) * | 2020-12-11 | 2024-05-28 | 北京航天自动控制研究所 | Multifunctional real-time interaction system based on CPCI bus |
| CN115865688A (en) * | 2022-11-25 | 2023-03-28 | 天津光电通信技术有限公司 | Double-channel high-speed analog acquisition playback equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108490803B (en) | 2020-03-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108491157A (en) | A kind of general signal processing platform | |
| CN108490803A (en) | A kind of test emulation system | |
| CN104237905B (en) | Big Dipper detector | |
| CN107462876B (en) | Radar echo signal simulator | |
| CN1771668B (en) | Information processing terminal system and transmission/reception method using the same | |
| CN105278404A (en) | Base-band device based on software radio | |
| CN208000134U (en) | A kind of telemetering equipment for acquiring and storing telemetry | |
| CN110113275B (en) | Intelligent multichannel broadband interference signal produces device | |
| US6898766B2 (en) | Simplifying integrated circuits with a common communications bus | |
| CN208477509U (en) | A kind of general signal processing platform | |
| CN102386946A (en) | Data transmission rapid frequency hopping radio station | |
| CN114244909B (en) | Protocol conversion circuit and related device | |
| CN117353758A (en) | High-performance SDR platform based on domestic ware component | |
| US7167682B1 (en) | Radio frequency (RF) transceiver with substantially coincident communication of RF and related control signals | |
| CN112910542A (en) | Measure and control ground detection equipment and system | |
| CN103152111A (en) | Software radio test platform based on universal serial bus (USB) interface | |
| CN201994962U (en) | Ethernet-to-E1 channel adapter based on FPGA (Field Programmable Gate Array) chip architecture technology | |
| CN114421979A (en) | Software defined Radio development system based on SOUP and GNU Radio | |
| CN204086550U (en) | Big Dipper detector | |
| CN107563098B (en) | Radio demonstration platform for aircraft radio station software | |
| CN220526329U (en) | Novel sub-card circuit based on FMC multichannel synchronous acquisition | |
| Muro | Using a COTS SDR as a 5G Development Platform. | |
| CN111130545A (en) | DAC/ADC unit loop test system of digital-analog hybrid microsystem | |
| Mann et al. | A versatile sampling adc system for on-detector applications and the advancedtca crate standard | |
| CN212137647U (en) | Wireless data transmission communication device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |