CN108470803B - A kind of epitaxial wafer and production method of light emitting diode - Google Patents
A kind of epitaxial wafer and production method of light emitting diode Download PDFInfo
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- CN108470803B CN108470803B CN201810229571.0A CN201810229571A CN108470803B CN 108470803 B CN108470803 B CN 108470803B CN 201810229571 A CN201810229571 A CN 201810229571A CN 108470803 B CN108470803 B CN 108470803B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Abstract
The invention discloses a kind of epitaxial wafer of light emitting diode and production methods, belong to optoelectronic fabrication techniques field.The epitaxial wafer includes substrate and stacks gradually buffer layer on substrate, undoped gallium nitride layer, N-type layer, carrier improves layer, active layer, electronic barrier layer, P-type layer and p-type contact layer, it is metal conducting layer or metal conductive oxide layer that carrier, which improves layer, improve layer by the way that carrier is arranged between active layer and N-type layer, it is metal conducting layer or metal conductive oxide layer since carrier improves layer, the resistance that carrier improves layer is lower, and the resistance in each region is more uniform, it is extending transversely in carrier improvement layer to be conducive to electronics, make electronics is more uniform to enter in active layer, to improve the uniformity and consistency of each region light emission luminance of active layer.
Description
Technical field
The present invention relates to optoelectronic fabrication techniques field, in particular to the epitaxial wafer of a kind of light emitting diode and production side
Method.
Background technique
LED (Light Emitting Diode, light emitting diode) has many advantages, such as that small in size, the service life is long, low in energy consumption, mesh
Before be widely used in automobile signal light, traffic lights, display screen and lighting apparatus.
Existing LED mainly includes substrate and stacks gradually buffer layer, undoped gallium nitride layer, N-type on substrate
Layer, active layer, electronic barrier layer, P-type layer and p-type contact layer, after LED is powered, carrier (electronics and P-type layer including N-type layer
Hole) can be migrated to active layer, and the recombination luminescence in active layer.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
The mobility of different zones electronics since the mobility of electronics is very fast, and in N-type layer is also inconsistent, this makes
Each region light emission luminance of active layer is uneven.
Summary of the invention
Each region light emission luminance in order to solve the problems, such as active layer is non-uniform, and the embodiment of the invention provides one kind to shine
The epitaxial wafer and production method of diode.The technical solution is as follows:
On the one hand, the embodiment of the invention provides a kind of epitaxial wafer of light emitting diode, the epitaxial wafer include substrate with
And buffer layer, undoped gallium nitride layer, N-type layer, the carrier stacked gradually over the substrate improves layer, active layer, electronics
Barrier layer, P-type layer and p-type contact layer, it is metal conducting layer that the carrier, which improves layer, and the metal conducting layer uses single gold
Belong to or alloy is made, the single metal includes any one in Mg, Ca, Yb, and the alloy includes in Mg:Ag, Yb:Ag
Any one.
Optionally, the carrier improve layer with a thickness of 5~100nm.
On the other hand, the embodiment of the invention also provides a kind of production method of epitaxial wafer, the production method includes:
One substrate is provided；
Successively epitaxial growth buffer, undoped gallium nitride layer, N-type layer, carrier improve layer, active over the substrate
Layer, electronic barrier layer, P-type layer and p-type contact layer, it is metal conducting layer that the carrier, which improves layer, and the metal conducting layer is adopted
Be made of single metal or alloy, the single metal includes any one in Mg, Ca, Yb, the alloy include Mg:Ag,
Any one in Yb:Ag.
Optionally, the carrier improves layer and is made of physical vaporous deposition.
Optionally, it is 400~800 DEG C that the carrier, which improves the growth temperature of layer,.
Optionally, it is 5~150mtorr that the carrier, which improves the growth pressure of layer,.
Technical solution provided in an embodiment of the present invention has the benefit that by setting between active layer and N-type layer
Setting carrier improves layer, is metal conducting layer or metal conductive oxide layer since carrier improves layer, carrier improves layer
Resistance is lower, and the resistance in each region is more uniform, be conducive to electronics carrier improve layer in it is extending transversely, make electronics more
It uniformly enters in active layer, to improve the uniformity and consistency of each region light emission luminance of active layer.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structure chart of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of active layer provided in an embodiment of the present invention；
Fig. 3 is a kind of production method flow chart of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention；
Fig. 4 is the flow chart of the production method of another light emitting diode provided in an embodiment of the present invention；
Fig. 5~11 are a kind of preparation process schematic diagrames of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is a kind of structure chart of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention.As shown in Figure 1, this is outer
Prolonging piece includes substrate 10 and the buffer layer being sequentially laminated on substrate 10 20, undoped gallium nitride layer 30, N-type layer 40, current-carrying
Son improves layer 50, active layer 60, electronic barrier layer 70, P-type layer 80 and p-type contact layer 90, and carrier improves layer 50 leads for metal
Electric layer or metal conductive oxide layer.
The embodiment of the present invention improves layer by the way that carrier is arranged between active layer and N-type layer, since carrier improves layer
For metal conducting layer or metal conductive oxide layer, the resistance that carrier improves layer is lower, and the resistance in each region is more uniform, has
It is extending transversely in carrier improvement layer conducive to electronics, make electronics is more uniform to enter in active layer, so that improving has
The uniformity and consistency of each region light emission luminance of active layer.
In an embodiment of the present invention, metal conducting layer can be made of single metal.
Specifically, single metal may include any one in Mg, Ca, Yb, and Mg, Ca, Yb have good electric conductivity,
Be conducive to electronics it is more uniform move to active layer.
In another embodiment of the invention, metal conducting layer can also be made of alloy.
Specifically, alloy may include any one in Mg:Ag, Yb:Ag.
In another embodiment of the invention, metal conducting layer can be metal conductive oxide layer, metal oxide
Conductive layer may include the oxide of any one in Mg, Ca, Yb.The oxide of Mg, Ca, Yb also have good conduction
Property, be conducive to electronics it is more uniform move to active layer.
Optionally, the thickness that carrier improves layer 50 can be 5~100nm.Under the thickness, carrier improves layer 50 in half
Transparence, the light that active layer 60 can be issued are conducive to the positive light extraction efficiency for improving LED to 70 1 lateral reflection of P-type layer.
Optionally, substrate 10 can be Sapphire Substrate, and Sapphire Substrate is a kind of common substrate, technology maturation, cost
It is low.
Buffer layer 20 can be GaN buffer layer, and the thickness of buffer layer 20 can be 15~35nm, the GaN buffer layer of growth
Thickness it is different, the quality of finally formed epitaxial layer also can be different, if the thickness of GaN buffer layer is excessively thin, it is slow to will lead to GaN
The surface for rushing layer is more loose and coarse, cannot provide a good template for the growth of subsequent structural, as GaN buffers thickness
The increase of degree, the surface of GaN buffer layer gradually becomes comparatively dense and smooth, is conducive to the growth of subsequent structural, if but GaN
The thickness of buffer layer is blocked up, then the surface that will lead to GaN buffer layer is excessively fine and close, is equally unfavorable for the growth of subsequent structural, nothing
Method reduces the lattice defect in epitaxial layer.
Optionally, the thickness of undoped gallium nitride layer 30 can be 1~5 μm, in the present embodiment, undoped gallium nitride layer
30 with a thickness of 3 μm.
Optionally, N-type layer 40 is N-type GaN layer, and the thickness of N-type layer 40 can be 1~5 μm, and the Si's in N-type layer 40 mixes
Miscellaneous concentration can be 1018~1019cm-3。
Fig. 2 is a kind of structural schematic diagram of active layer provided in an embodiment of the present invention, as shown in Fig. 2, active layer 60 can be with
In including alternately stacked 5~11 periodsxGa1-xN layer 61 and GaN layer 62,0 < x < 1, wherein InxGa1-xThe thickness of N layer 61
It can be 2~4nm, the thickness of GaN layer 62 can be 9~20nm, in the present embodiment, InxGa1-xN layer 61 with a thickness of 3nm,
GaN layer 62 with a thickness of 15nm.
It should be noted that In shown in Fig. 2xGa1-xThe number of plies of N layer 61 and GaN layer 62 is only to illustrate, and do not have to
To limit its respective number of plies.
Electronic barrier layer 70 can be p-type AlyGa1-yN layers, wherein 0.1 < y < 0.5.The thickness of electronic barrier layer 70 can be with
For 50~150nm, in the present embodiment, electronic barrier layer 70 with a thickness of 100nm.
Optionally, P-type layer 80 is p-type GaN layer, and the thickness of P-type layer 80 can be 100~800nm, in the present embodiment, P
Type layer 80 with a thickness of 500nm.
Optionally, the thickness of p-type contact layer 90 can be 5~300nm, in the present embodiment, the thickness of p-type contact layer 90
For 200nm.
Fig. 3 is a kind of production method flow chart of the epitaxial wafer of light emitting diode provided in an embodiment of the present invention, for making
Make epitaxial wafer as shown in Figure 1, as shown in figure 3, the production method includes:
S11: a substrate is provided.
In the present embodiment, Sapphire Substrate is selected.
S12: successively epitaxial growth buffer, undoped gallium nitride layer, N-type layer, carrier improve layer, active on substrate
Layer, electronic barrier layer, P-type layer and p-type contact layer.
Wherein, it is metal conducting layer or metal conductive oxide layer that carrier, which improves layer,.
The embodiment of the present invention improves layer by the way that carrier is arranged between active layer and N-type layer, since carrier improves layer
For metal conducting layer or metal conductive oxide layer, the resistance that carrier improves layer is lower, and the resistance in each region is more uniform, has
It is extending transversely in carrier improvement layer conducive to electronics, make electronics is more uniform to enter in active layer, so that improving has
The uniformity and consistency of each region light emission luminance of active layer.
Fig. 4 is the flow chart of the production method of another light emitting diode provided in an embodiment of the present invention, below with reference to attached
The production method that Fig. 5~11 pair Fig. 4 is provided is described in detail:
S21: a substrate is provided.
When realization, which can be Sapphire Substrate, and Sapphire Substrate is a kind of common substrate, technology maturation, at
This is low.
In the step s 21, Sapphire Substrate can be pre-processed, is can specifically include in hydrogen atmosphere to blue precious
Stone lining bottom carries out annealing 8 minutes, and annealing temperature is 1000~1200 DEG C, then carries out nitrogen treatment to Sapphire Substrate.
S22: it is epitaxially grown on the substrate buffer layer.
As shown in figure 5, growth has GaN buffer layer 20 on substrate 10.
Wherein, the thickness of GaN buffer layer can be 15nm~35nm.The thickness of the GaN buffer layer of growth is different, most end form
At the quality of epitaxial layer also can be different, if the thickness of GaN buffer layer is excessively thin, the surface that will lead to GaN buffer layer is more dredged
It is loose and coarse, a good template cannot be provided for the growth of subsequent structural, with the increase of GaN buffer layer thickness, GaN buffering
The surface of layer gradually becomes comparatively dense and smooth, is conducive to the growth of subsequent structural, if but the thickness mistake of GaN buffer layer
Thickness, then the surface that will lead to GaN buffer layer is excessively fine and close, is equally unfavorable for the growth of subsequent structural, can not reduce in epitaxial layer
Lattice defect.
Specifically, when growing GaN buffer layer, growth temperature can be 400~600 DEG C, and growth pressure can be 400torr
~600torr.
After growing GaN buffer layer, in-situ annealing processing can also be carried out to buffer layer, temperature is 1000~1200 DEG C,
Annealing time is 5~10 minutes, and annealing pressure is 400torr~600torr.
S23: undoped gallium nitride layer is grown on the buffer layer.
As shown in fig. 6, growth has undoped gallium nitride layer 30 on buffer layer 20.The thickness of undoped gallium nitride layer 30 can
Think 1~5 μm, in the present embodiment, undoped gallium nitride layer 30 with a thickness of 3 μm.
The growth temperature of undoped gallium nitride layer 30 can be 1000~1100 DEG C, growth pressure can for 100torr~
500torr。
S24: N-type layer is grown on undoped gallium nitride layer.
As shown in fig. 7, growth has N-type layer 40 on undoped gallium nitride layer 30.
Realize ground, N-type layer 40 is N-type GaN layer, and the thickness of N-type layer 40 can be 1~5 μm, and the Si's in N-type layer 40 mixes
Miscellaneous concentration can be 1018~1019cm-3。
The growth temperature of N-type layer 40 can be 1000~1200 DEG C, and growth pressure can be 100torr~500torr.
S25: growing carrier in N-type layer improves layer.
As shown in figure 8, growth has carrier to improve layer 50 in N-type layer 40.Carrier improves layer 50 can lead for metal
Electric layer or metal conductive oxide layer.
In an embodiment of the present invention, metal conducting layer can be made of single metal.
Specifically, single metal may include any one in Mg, Ca, Yb, and Mg, Ca, Yb have good electric conductivity,
Be conducive to electronics it is more uniform move to active layer.
In another embodiment of the invention, metal conducting layer can also be made of alloy.
Specifically, alloy may include any one in Mg:Ag, Yb:Ag.
In another embodiment of the invention, metal conducting layer can be metal conductive oxide layer, metal oxide
Conductive layer may include the oxide of any one in Mg, Ca, Yb.The oxide of Mg, Ca, Yb also have good conduction
Property, be conducive to electronics it is more uniform move to active layer.
Specifically, carrier improves layer 50 and can be made of physical vaporous deposition.It can carry out under an argon atmosphere
Carrier improves the production of layer 50, and the spacing between substrate and target can be 4~15cm, and power is 2500~4000W, revolving speed
It can be 30~200r/min.
When realization, the purity of target is not less than 99.99%, with the quality for the metal conducting layer for ensuring to produce.
The growth temperature that carrier improves layer 50 can be 400~800 DEG C.
The growth pressure that carrier improves layer 50 can be 5~150mtorr.
S26: improve in carrier and grow active layer on layer.
As shown in figure 9, improving growth on layer 50 in carrier has active layer 60.
Specifically, active layer 60 may include the In in alternately stacked 5~11 periodsxGa1-xN layer 61 and GaN layer 62,
Wherein, 0 < x < 1.
Optionally, InxGa1-xThe thickness of N layer 61 can be 2~4nm, and the thickness of GaN layer 62 can be 9~20nm, this reality
It applies in example, InxGa1-xN layer 61 with a thickness of 3nm, GaN layer 62 with a thickness of 15nm.
When realization, InxGa1-xThe growth temperature of N layer 61 can be 720~829 DEG C, growth pressure can for 100~
500torr.The growth temperature of GaN layer 62 can be 850~959 DEG C, and growth pressure can be 100~500torr.
It should be noted that In shown in Fig. 9xGa1-xThe number of plies of N layer 61 and GaN layer 62 is only to illustrate, and do not have to
To limit its respective number of plies.
S27: electronic barrier layer is grown on active layer.
As shown in Figure 10, growth has electronic barrier layer 70 on active layer 60.Electronic barrier layer 70 can be p-type
AlyGa1-yN layers, wherein 0.1 < y < 0.5.
The growth temperature of electronic barrier layer 70 can be 850~1080 DEG C, and growth pressure can be 200~500torr.Institute
The thickness of the electronic barrier layer 70 of growth can be 50~150nm, in the present embodiment, electronic barrier layer 70 with a thickness of 100nm.
If the thickness of electronic barrier layer 70 is excessively thin, electronics is easier across electronic barrier layer 70, if electronic barrier layer 70 is blocked up, meeting
The absorption for increasing by 70 pairs of light of electronic barrier layer, causes brightness to reduce.
S28: the growing P-type layer on electronic barrier layer.
As shown in figure 11, growth has P-type layer 80 on electronic barrier layer 70.
Specifically, P-type layer 80 is p-type GaN layer, and the thickness of P-type layer 80 can be 100~800nm, in the present embodiment, P
Type layer 80 with a thickness of 500nm.
The growth temperature of P-type layer 80 can be 850~1080 DEG C, and growth pressure can be 100~300torr.
S29: the growing P-type contact layer in P-type layer.
Referring to Fig.1, growth has p-type contact layer 90 in P-type layer 80.
Specifically, the thickness of p-type contact layer 90 can be 5~300nm, in the present embodiment, the thickness of p-type contact layer 90
For 200nm.
The growth temperature of p-type contact layer 90 can be 850~1080 DEG C, and growth pressure can be 100~300torr.
After the growth for completing p-type contact layer 90, it can be made annealing treatment in ammonia atmosphere, annealing temperature 650
~850 DEG C, the annealing time is 5~15 minutes.
Following process can be carried out to epitaxial wafer after completing step S29, to complete the production of LED chip.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of epitaxial wafer of light emitting diode, which is characterized in that the epitaxial wafer includes substrate and is sequentially laminated on described
Buffer layer, undoped gallium nitride layer, N-type layer, carrier on substrate improve layer, active layer, electronic barrier layer, P-type layer and p-type
Contact layer, it is metal conducting layer that the carrier, which improves layer, and the metal conducting layer is made of single metal or alloy, described
Single metal includes any one in Mg, Ca, Yb, and the alloy includes any one in Mg:Ag, Yb:Ag.
2. epitaxial wafer according to claim 1, which is characterized in that the carrier improve layer with a thickness of 5~100nm.
3. a kind of production method of the epitaxial wafer of light emitting diode, which is characterized in that the production method includes:
One substrate is provided；
Over the substrate successively epitaxial growth buffer, undoped gallium nitride layer, N-type layer, carrier improve layer, active layer,
Electronic barrier layer, P-type layer and p-type contact layer, it is metal conducting layer that the carrier, which improves layer, and the metal conducting layer is using single
One metal or alloy is made, and the single metal includes any one in Mg, Ca, Yb, and the alloy includes Mg:Ag, Yb:Ag
In any one.
4. production method according to claim 3, which is characterized in that the carrier improves layer and uses physical vapour deposition (PVD)
Method production.
5. production method according to claim 3, which is characterized in that the growth temperature that the carrier improves layer is 400
~800 DEG C.
6. production method according to claim 3, which is characterized in that the carrier improve the growth pressure of layer be 5~
150mtorr。
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| CN109545918B (en) * | 2018-09-27 | 2020-11-27 | 华灿光电（浙江）有限公司 | Gallium nitride-based light emitting diode epitaxial wafer and preparation method thereof |
| CN110047982B (en) * | 2019-02-27 | 2020-07-07 | 华灿光电(苏州）有限公司 | Light emitting diode, epitaxial wafer and preparation method thereof |
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