CN108448891A - A kind of regulator circuit based on charge pump construction - Google Patents
A kind of regulator circuit based on charge pump construction Download PDFInfo
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- CN108448891A CN108448891A CN201810365621.8A CN201810365621A CN108448891A CN 108448891 A CN108448891 A CN 108448891A CN 201810365621 A CN201810365621 A CN 201810365621A CN 108448891 A CN108448891 A CN 108448891A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Abstract
The invention belongs to Analogous Integrated Electronic Circuits technical field of power management, specifically propose a kind of chip interior regulator circuit based on charge pump construction.This circuit is invented：Biasing circuit, start-up circuit, control circuit, oscillator and electric charge pump module.Output voltage is formed by the VBE clampers of zener diode and transistor, its voltage is lifted by charge pump construction when supply voltage is relatively low, and thus circuit generation is still directly provided by external circuit by control module control output voltage so that circuit is using more flexible.In addition start-up circuit is introduced so that allow charge pump to work normally when supply voltage is relatively low.This circuit is different from traditional LDO regulator circuits, does not need frequency compensation, faster, power consumption is relatively low for response speed, can play good voltage stabilizing function.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical field of power management, and in particular to a kind of based on the steady of charge pump construction
Volt circuit.
Background technology
In Analogous Integrated Electronic Circuits technology, a stable supply voltage for ensure circuit normal work to close weight
It wants.Since power input voltage variation range is bigger, while maximum voltage exceeds the pressure resistance of normal pressure device, so for chip
In most modules cannot directly be powered using supply voltage.Therefore chip needs a power conversion module will be unstable
Fixed supply voltage is converted into a relatively low performance of voltage value more preferably secondary power voltage.
Traditional secondary power generation circuit can sample LDO structures.Because LDO has good stabilizing voltage characteristic, ring simultaneously
Answer speed quickly.But LDO structures need frequency compensation, the more excellent LDO of performance, frequency compensation is often more complicated, and cost is higher,
This circuit is different from traditional LDO regulator circuits, and charge pumps structure does not need additional frequency compensation, and response speed is more
Soon, power consumption is relatively low, can play good voltage stabilizing function.
Invention content
Problems solved by the invention is to provide a kind of voltage stabilizing electricity based on charge pump construction applied to Analogous Integrated Electronic Circuits
Road.
The technical scheme is that：A kind of regulator circuit based on charge pump construction, circuit include：Biasing circuit,
Start-up circuit, control circuit, oscillator and electric charge pump module.Biasing circuit on the one hand to oscillator module provide bias current and
Reference voltage, on the other hand limit charge pump output voltage, only it is allowed to work when supply voltage is relatively low, to output voltage into
Row biasing；Start-up circuit makes circuit allow charge pump to work normally when supply voltage is relatively low, it is prevented to be absorbed in degeneracy point；Control
It is that thus circuit is generated or directly provided by external circuit that circuit, which can control output voltage,.Oscillator structure is charge pump
Core supplementary module；Charge pump circuit makes when supply voltage is relatively low, its voltage is lifted by charge pump construction so that output
Voltage keeps stablizing.
The biasing circuit includes：3 NMOS tubes, 2 Zener diodes, 6 resistance, 1 capacitance；The upper ends resistance R6
It is connected with the VC nodes in charge pump construction, lower end is connected with Zener diode ZD4 negative terminals；The upper ends resistance R9, R10, R11 are equal
It is connected with the source of NMOS tube M7, is denoted as node V0, the lower ends resistance R9 is connected with Zener diode ZD3 negative terminals；ZD3's and ZD4
The drain terminal for the NMOS tube M8 that anode connects with source and drain jointly is connected, the grid end of the NMOS pipes M17 in the grid end and start-up circuit of M8
It is connected, is provided for start-up circuit and compare electric current；The lower ends resistance R10 are connected with the upper ends resistance R12, are divided to voltage V0, point
Pressure node is denoted as V4, is connected with the grid end of the NMOS tube M23 in oscillator module, and reference voltage is provided to oscillator；Resistance R11
The drain terminal for the NMOS tube M9 that lower end is connect with diode is connected, and bias current is provided for oscillator module；The grid end of NMOS tube M9
It is connected with the grid end of the NMOS tube M24 in oscillator module, bias current is provided for it；NMOS pipes M7 is that breadth length ratio is prodigious
Switching tube is adjusted, drain terminal meets supply voltage VIN, the left end of grid end connecting resistance R7, the right end of resistance R7 and the lower end of resistance R6,
The negative terminal of Zener diode ZD4 is connected so that the working condition of M7 pipes changes with VC node voltages；Diode connection type
The source of NMOS tube M8 and M9 are grounded with the lower end of resistance R12；The top crown of capacitance C5 is connected with the upper end of R11, lower termination
Ground.
The start-up circuit part includes 1 pair of cascode current mirror, 1 pair of current mirror, 2 NMOS tubes and a resistance, electricity
The resistance upper ends R13 are connected with supply voltage VIN, and lower end is connected with the drain terminal of NMOS tube M10, eliminate the electricity with NMOS tube M13 drain terminals
Pressure difference；NMOS tube M10, M11, M12, M13 connect into cascode current-mirror structures, mirroring ratios 8:1, it is defeated from the drain terminal of M13
Go out electric current；The drain terminal for the NMOS tube M10 that grid leak connects is connected with the lower end of resistance R13, and the grid end of M10 is connected with the grid end of M13,
The drain terminal of M10 is connected with the drain terminal for the M11 that grid leak connects；The grid end of NMOS tube M11 is connected with the grid end of M12, NMOS tube M11
It is grounded with the source of M12；The drain terminal of M12 pipes is connected with the source of M13 pipes；The source of M13 pipes is connected with the drain terminal of M14 pipes；
NMOS tube M14 and M15 connects into current mirror form, mirroring ratios 8:1, from the drain terminal output current of M14 pipes；NMOS tube M14
Connect with M13 drain terminals, is denoted as and node V6；The source of NMOS tube M14 and M15 connect the grid end and grid leak of supply voltage VIN, M14
The grid end of the M15 to connect is connected；The grid end of NOMS pipes M16 is connected with the grid end for the NMOS tube M10 that grid leak connects, drain terminal and M15
Drain terminal be connected, source is connected with the drain terminal of M17, have enable effect；M8 pipes in the grid end and biasing circuit of NMOS tube M17
Grid end be connected, the source of M17 ground connection, with mirror image bias current.
The oscillator circuit portion includes an operational amplifier, 1 resistance, 1 capacitance and 4 phase inverters.NMOS
Pipe M18, M21, M22, M26 source is connected with supply voltage VIN, the leakage for the NMOS tube M19 that the drain terminal of M18 connects with grid leak
End is connected, and the grid end for the NMOS tube M22 that grid end connects with grid leak connects；The grid end and NMOS tube for the NMOS tube M19 that grid leak connects
The grid end of M20 is connected, and the source of M19 and M20 are grounded；The drain terminal of M20 is connected with the drain terminal of M21；The grid end of M21 and grid leak phase
The grid end of the NMOS tube M26 connect is connected；The M26 pipes that grid leak connects are connected with the drain terminal of NMOS tube M25；The M22 pipes that grid leak connects
It is connected with the drain terminal of NMOS tube M23；The grid end of M23 is connected with the V4 nodes in biasing circuit, the grid end and oscillator of M25 pipes
Middle V4 ' nodes are connected, and M23 is connected with the drain terminal of M24 pipes with M25 sources, the source ground connection of NMOS tube M24；M21's and M22
Drain terminal is connected with the anode of phase inverter INV1, and the negative terminal of phase inverter INV1 and the anode of phase inverter INV2, phase inverter INV4 are just
End is connected, and is denoted as nodes X；The negative terminal of phase inverter INV2 is connected with the left end of the anode of phase inverter INV3, resistance R14, is denoted as section
Point Y；The negative terminal of phase inverter INV3 is connected with the lower step of capacitance C5, is denoted as node Z, the upper step of capacitance C5 is with resistance R14's
Right end is connected, and is denoted as node V4 '；The negative terminal output clock signal I4_CLK of INV4.
The charge pump circuit includes 1 NMOS tube, 2 transistors, 3 capacitances and 3 resistance.NMOS tube M6 is width
Long to be managed than prodigious adjustment, source meets supply voltage VIN, and grid end connects with the V6 nodes in start-up circuit, drain terminal and biased electrical
V0 nodes in road connect；Transistor Q6 is that diode is connect with Q7, and the base stage of Q7 connects with collector, collector and biasing
Node V0 in circuit connects, and the collector for the transistor Q6 that emitter connects with base collector connects, and is denoted as node V2, Q6
Emitter be connected with the left end of resistance R8；V2 nodes are connected with the upper step of capacitance C4, and the lower step of C4 is upper with resistance R4's
End is connected, and the lower end of R4 is connected with the negative terminal of the INV4 in oscillator, input clock signal I4_CLK；The right end of resistance R8 and electricity
The left end for hindering R5 is connected, and is denoted as node VC, and the upper step of capacitance C2 is connected with node VC, and the right end of resistance R5 is upper with capacitance C1's
Step is connected, and is denoted as node VA, the lower step of capacitance C1, C2 are grounded.
The control circuit includes a phase inverter and a LS latch.The anode of enable signal from phase inverter INV are defeated
Enter, the negative terminal of phase inverter INV is connected with the ends A of LS latch, and the ends AN of LS latch are connected with the anode of INV, receives input
Signal；The ends the Y1 ports output control signal CONT1, the Y2 output control signal CONT2 of LS latch.
Description of the drawings
Fig. 1 is the voltage regulator circuit structure schematic diagram based on charge pump construction in the present invention；
Fig. 2 is the physical circuit schematic diagram of start-up circuit in the present invention, biasing circuit, oscillator and charge pump construction；
Fig. 3 is the schematic diagram of control circuit in the present invention；
Fig. 4 (a) is that for circuit under different input voltages, the Transient of output voltage, Fig. 4 (b) is this hair in the present invention
Bright middle output voltage and input voltage relational graph；
Note：Name is managed with the transistor that N starts for NMOS (N-Metal-Oxide-Semiconductor)；Name is with R
The device of beginning is resistance；The device that name is started using C is capacitance；The device that name is started using INV is phase inverter；Name is with Q
The device of beginning is triode；The device that name is started using DZ is Zener diode；Cascode current-mirror structures are cascade
Current-mirror structure.
Specific implementation mode
The invention will be further elaborated with specific embodiment below in conjunction with the accompanying drawings.
Fig. 1 is the electrical block diagram of the present invention, including：Biasing circuit, start-up circuit, control circuit, oscillator and
Electric charge pump module.Circuit voltage exports port VG thus, and port VGG is input voltage pin, and shelves need in external power supply conduct
When portion's secondary power voltage, an external stabilization voltage just is introduced from the pin, is powered to internal module.VGG_DIS is internal
Power supply enable port can be that this regulator circuit generates or outside is provided according to this port controlling output voltage.Work as needs
When being used as internal secondary power using external power supply, VGG and VGG_DIS is connected on external power supply can simultaneously.If making
When with internal voltage regulator, VGG_DIS is connected with ground.At this time output voltage by zener diode ZD1 burning voltage voltage and crystalline substance
The VBE of body pipe Q3 is formed.When using internal voltage regulator, VGG_DIS is low, and exports two control signals by control module
CONT1 and CONT2, two signals are low, ensure that internal voltage regulator can work normally.Output voltage mainly has two pole of Zener
Pipe ZD2 and the transistor Q3 of diode connection type are determined.
VG=UZ+VBE (1)
UZ refers to the burning voltage of zener diode, and VBE is transistor Q3 base-emitter voltages.Zener diode stablizes electricity
At all according to its stable voltage difference, temperature coefficient is different.When the burning voltage of Zener diode is excessive, reversed voltage stabilizing mechanism
It is dominated by avalanche breakdown, therefore burning voltage has positive temperature coefficient at this time.Equally when its burning voltage is too small, reversed voltage stabilizing
Mechanism is dominated by tunnel breakdown, and burning voltage has negative temperature coefficient at this time.The temperature electricity for the Zener diode that this circuit uses
Pressure is positive temperature coefficient, so the voltage VBE of a negative temperature coefficient is in addition added on it, to improve the temperature of output voltage
Characteristic.
M1 is power switch tube in Fig. 1, can effectively adjust output current according to load variation, be used for responsive load and become
Change.The bias voltage of power tube M1 is provided by two circuits.When supply voltage VIN is relatively high, bias voltage by M5, Q2,
The biasing circuit 1 of ZD2, Q1 and R1 composition provides.VA voltages are at this time
VA=VGS5+VBE2+Uc (2)
VGS5 and VBE2 sizes are related with the electric current I0 for flowing through them, and VGS5 and I0 is subduplicate relationship, and VBE2 and I0 is pair
Several relationships.So VGS5 and VBE2 is weak related to electric current.When supply voltage is very big, I0 expression formulas are
By formula (3) as it can be seen that I0 and the approximately linear relationships of VIN.Therefore VGS5 and VBE2 is weak related to VIN, VA also with VIN
Weak correlation.The VA high VGS of voltage ratio VG voltages simultaneously can make M1 work so only needing rationally to adjust the breadth length ratio of M5
In saturation region.In conclusion when supply voltage is relatively high, the bias voltage VA being made of ZD2, Q2 and M5 can be provided to M1
One good static point so that VG is more stable.
When supply voltage is lower so that so that Q1, M5, Q2 all cisco unity malfunction when, supply voltage is at this time
VINmin=VBE1+VTH5+VBE2+UC (4)
When VIN is less than VINmin, Q1, M5, Q2 are not turned on, therefore VA voltages are equal to Q1, M5, Q2 and ZD2 equiva lent impedances are formed
Resistance to VIN divide.Because of (RZD2+RQ2+RM5)>>RQ2, so at this time
VA≈VIN (5)
VG=VIN-VGS1 (6)
VG voltages are easily by load effect.So in the case of low supply voltage, biasing circuit 1 cannot provide effective biased electrical
Pressure.It is provided in a high control source to node A with charge pump [92] circuit at this time, effectively to be biased to M1 so that
M1 is operated in linear zone, and VG is equal to VIN.
As shown in Fig. 2, V0 is divided by resistance R10 and R12 in biasing circuit, reference voltage is provided to oscillator.Together
When in R11 and M9 branches generate bias current, current value is about
When supply voltage is relatively low, because VC voltages are elevated, M7 is operated in linear zone, and V0 voltages are approximately supply voltage
VIN.When VIN increases, V0 can be with increase, to raise VC current potentials by charge pump.But VC current potentials are finally saved by VA
Point clamped effect and stablize, M7 is operated in saturation region at this time, so
V0=VC-VGS7 (8)
Therefore VC limits V0 with the increased trend of supply voltage.
Start-up circuit only works when supply voltage is relatively low.When supply voltage is relatively low, VC and V0 voltages all can
Relatively low, M8 is not turned on, and I2 electric currents are zero.Start-up circuit be by electric current I1 by cascade mirror image pipes be mirrored to V6 nodes with
The image current of I2 is compared.If the former is big, V6 outputs are zero, and otherwise V6 outputs are high level.The mirror of I1
To reduce 8 times, the mirror of I2 is to increase 8 times, so when V6 is overturn, the threshold value of I2 is I2 (TH)=I1/64.I1 electric currents
For
R13 values are close to 1M Ω in formula (10), therefore the threshold value of electric current I2 is the value of a very little.In conclusion the proportional current of I1
Comparison between the proportional current of I2, which approximate can be found out, judges whether M8 is connected.As VC and V0 all smaller, Wu Farang
When charge pump startup, M8 is not turned at this time so that V6 outputs are low level.M6 is connected, and V0 voltages are supply voltage, and charge pump is opened
Begin to start, raises VC current potentials.
Oscillator module in Fig. 2 is the indispensable module of charge pump.The supply voltage of the pierce circuit is V0.
M18~M26 forms comparator.Bias current and reference voltage carry out auto bias circuit.Assuming that starting stage V4 ' voltage is 0,
Because V4 is more than V4 ', phase inverter INV1 outputs x is 0, and node y and node z are respectively 1 and 0.Therefore phase inverter INV2 is logical
It crosses R14 to charge to capacitance C3, V4 ' voltages are increasing.When V4 ' is slightly larger than V4, output voltage overturning, node x, y and z are electric at this time
Pressure is respectively 1,0,1.Therefore supply voltage is V0, so V4 ' current potentials can get higher with z and raise V0, then the voltage of V4 ' is
(V0+V4).Again because y current potentials are discharged for 0, V4 ' by resistance R14.When V4 ' is slightly smaller than V4, output is turned over again
Turn, node x, y and z voltage is respectively 0,1,0.The voltage of V4 ' is (V4-V0) at this time, while phase inverter INV2 is to passing through resistance
R14 capacitances C3 charges again；Repeatedly.Therefore I4_CLK exports a clock signal, high level V0.Clock cycle is
T=2R14C3 (11)
As electric charge pump module is biased node VA in Fig. 2.When supply voltage is relatively low, because M8 is not turned on, institute
Using V6 as low level, so that M6 is connected, V0 voltages are equal to VIN.The Q7 and Q6 that diode connects in circuit only can positive guides
It is logical, while I4_CLK is clock signal, high level V0.So circuit can constantly raise V2 current potentials by capacitance C4.When
When I4_CLK is low level, V0 is charged by the Q7 that diode connects to capacitance C4, while providing output current, until V2 current potentials
For (V0-Vbe).When I4_CLK is high level, C4 lower plates current potential can be raised to V0, therefore V2 current potentials can be elevated about
For (2V0-Vbe)；Because Q7 is reverse-biased, Q6 forward bias, so V2 only gives output to provide electric current.V2 is when providing electric current simultaneously
It is about ioutT/ (2C4) that some pressure drop sizes, which can be lost,.Voltage is on VC at this time
When I4_CLK becomes low level again, V0 charges to C4 again by Q7, while the voltage that supplement loses.Most
Output voltage afterwards exports a stable bias voltage VA by two-stage low-pass filter a R8, C2, R5 and C1.
Wherein f is the frequency of oscillator.By formula (13), the frequency of oscillator is higher, and voltage loss is with regard to smaller, but frequency is higher
Power consumption is bigger.
Control circuit generates two control signal CONT_1 and CONT_2 to control voltage stabilizing electricity by input signal VGG_DIS
Road.When VGG_DIS is low level, CONT1 outputs at this time are high level, and CONT2 outputs are low level, select internal voltage stabilizing electricity
Road output voltage, VGG=VG-Vth (MOS body diodes forward conduction voltage drop).When VGG_DIS is high level, at this time
CONT1 outputs are low level, and CONT2 outputs are high level, and external circuit is selected to provide output voltage, VGG=VG.
Fig. 4 (a) is the transient process analogous diagram of output voltage under different electrical power voltage condition.Fig. 4 (b) is output electricity
The relational graph of pressure and supply voltage.As shown in Fig. 4 (a), internal secondary power generation circuit can normally start.Such as Fig. 4 (b)
It is shown, when supply voltage is relatively low because supply voltage be less than (UZ+VBE), output voltage almost with supply voltage phase
Together, error derives from the pressure drop at M1 pipe source and drain end.When supply voltage is bigger, output voltage is almost stablized at (UZ+VBE).
The above described is only a preferred embodiment of the present invention, being not intended to limit the present invention in any form.Appoint
What those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the side of the disclosure above
Method and technology contents make many possible changes and modifications to technical solution of the present invention, or are revised as the equivalent reality of equivalent variations
Apply example.Therefore, every content without departing from technical solution of the present invention, according to the technical essence of the invention does above example
Any simple modifications, equivalents, and modifications, still fall within technical solution of the present invention protection in the range of.
Claims (6)
1. a kind of regulator circuit based on charge pump construction, including：Biasing circuit, start-up circuit, control circuit, oscillator and electricity
Lotus pump module.On the one hand biasing circuit provides bias current and reference voltage to oscillator module, on the other hand limit charge pump
Output voltage, only it is allowed to work when supply voltage is relatively low, output voltage is biased；Start-up circuit makes circuit in electricity
Source voltage allows charge pump to work normally when relatively low, it is prevented to be absorbed in degeneracy point；Thus it is that control circuit, which can control output voltage,
Circuit generation is still directly provided by external circuit.Oscillator structure is the core supplementary module of charge pump；Charge pump circuit makes
When proper supply voltage is relatively low, its voltage is lifted by charge pump construction so that output voltage keeps stablizing.
2. a kind of regulator circuit based on charge pump construction according to claim 1, which is characterized in that the biasing circuit
Including：3 NMOS tubes, 2 Zener diodes, 6 resistance, 1 capacitance；The upper ends resistance R6 and the VC nodes in charge pump construction
It is connected, lower end is connected with Zener diode ZD4 negative terminals；The upper ends resistance R9, R10, R11 are connected with the source of NMOS tube M7, note
For node V0, the lower ends resistance R9 are connected with Zener diode ZD3 negative terminals；The NMOS that ZD3 connects with source and drain jointly with the anode of ZD4
The drain terminal of pipe M8 is connected, and the grid end of M8 is connected with the grid end of the NMOS tube M17 in start-up circuit, and it is electric to provide comparison for start-up circuit
Stream；The lower ends resistance R10 are connected with the upper ends resistance R12, are divided to voltage V0, and divider node is denoted as V4, with oscillator module
In NMOS tube M23 grid end be connected, give oscillator provide reference voltage；The NMOS tube that the lower ends resistance R11 are connect with diode
The drain terminal of M9 is connected, and bias current is provided for oscillator module；NMOS tube M24 in the grid end and oscillator module of NMOS tube M9
Grid end be connected, provide bias current for it；NMOS tube M7 is the prodigious adjustment switching tube of breadth length ratio, and drain terminal connects supply voltage
The right end of VIN, the left end of grid end connecting resistance R7, resistance R7 are connected with the negative terminal of the lower end of resistance R6, Zener diode ZD4, make
The working condition of M7 pipes is obtained as VC node voltages change；The source and resistance of the NMOS tube M8 and M9 of diode connection type
The lower end of R12 is grounded；The top crown of capacitance C5 is connected with the upper end of R11, lower end ground connection.
3. start-up circuit according to claim 1, which is characterized in that the circuit part includes 1 pair of cascode electric current
Mirror, 1 pair of current mirror, 2 NMOS tubes and a resistance, the upper ends resistance R13 are connected with supply voltage VIN, lower end and NMOS tube M10
Drain terminal be connected, eliminate and the voltage differences of NMOS tube M13 drain terminals；NMOS tube M10, M11, M12, M13 connect into cascode electric currents
Mirror structure, mirroring ratios 8:1, from the drain terminal output current of M13；The drain terminal for the NMOS tube M10 that grid leak connects is with resistance R13's
Lower end is connected, and the grid end of M10 is connected with the grid end of M13, and the drain terminal for the M11 that drain terminal and the grid leak of M10 connect is connected；NMOS tube
The grid end of M11 is connected with the grid end of M12, and the source of NMOS tube M11 and M12 are grounded；The source of the drain terminal and M13 pipes of M12 pipes
It is connected；The source of M13 pipes is connected with the drain terminal of M14 pipes；NMOS tube M14 and M15 connects into current mirror form, mirroring ratios 8:
1, from the drain terminal output current of M14 pipes；NMOS tube M14 connects with M13 drain terminals, is denoted as and node V6；NMOS tube M14's and M15
The grid end for the M15 that source connects the grid end of supply voltage VIN, M14 and grid leak connects is connected；The grid end of NOMS pipes M16 and grid leak phase
The grid end of the NMOS tube M10 connect is connected, and drain terminal is connected with the drain terminal of M15, and source is connected with the drain terminal of M17, has enabled effect；
The grid end of NMOS tube M17 is connected with the grid end of the M8 pipes in biasing circuit, the source ground connection of M17, with mirror image bias current.
4. pierce circuit according to claim 1, which is characterized in that the circuit part includes an operation amplifier
Device, 1 resistance, 1 capacitance and 4 phase inverters.NMOS tube M18, M21, M22, M26 source is connected with supply voltage VIN,
The drain terminal of M18 is connected with the drain terminal for the NMOS tube M19 that grid leak connects, and the grid end for the NMOS tube M22 that grid end connects with grid leak connects；
The grid end for the NMOS tube M19 that grid leak connects is connected with the grid end of NMOS tube M20, and the source of M19 and M20 are grounded；The drain terminal of M20
It is connected with the drain terminal of M21；The grid end of M21 is connected with the grid end for the NMOS tube M26 that grid leak connects；M26 that grid leak connects pipe with
The drain terminal of NMOS tube M25 is connected；The M22 pipes that grid leak connects are connected with the drain terminal of NMOS tube M23；The grid end and biasing circuit of M23
In V4 nodes be connected, the grid end of M25 pipes is connected with V4 ' nodes in oscillator, M23 and M25 sources with the drain terminal phase of M24 pipes
Even, the source ground connection of NMOS tube M24；The drain terminal of M21 and M22 is connected with the anode of phase inverter INV1, the negative terminal of phase inverter INV1
It is connected with the anode of the anode of phase inverter INV2, phase inverter INV4, is denoted as nodes X；The negative terminal and phase inverter of phase inverter INV2
The anode of INV3, the left end of resistance R14 are connected, and are denoted as node Y；The negative terminal of phase inverter INV3 is connected with the lower step of capacitance C5,
It is denoted as node Z, the upper step of capacitance C5 is connected with the right end of resistance R14, is denoted as node V4 '；The negative terminal output clock letter of INV4
Number I4_CLK.
5. electric charge pump module according to claim 1, which is characterized in that the circuit includes 1 NMOS tube, 2 crystal
Pipe, 3 capacitances and 3 resistance.NMOS tube M6 is the prodigious adjustment pipe of breadth length ratio, and source connects supply voltage VIN, grid end and startup
V6 nodes in circuit connect, and drain terminal connects with the V0 nodes in biasing circuit；Transistor Q6 is that diode is connect with Q7, Q7
Base stage connect with collector, collector connects with the node V0 in biasing circuit, the crystalline substance that emitter connects with base collector
The collector of body pipe Q6 connects, and the emitter for being denoted as node V2, Q6 is connected with the left end of resistance R8；V2 nodes are upper with capacitance C4's
Step is connected, and the lower step of C4 is connected with the upper end of resistance R4, and the lower end of R4 is connected with the negative terminal of the INV4 in oscillator, input
Clock signal I4_CLK；The right end of resistance R8 is connected with the left end of resistance R5, is denoted as node VC, the upper step and node of capacitance C2
VC is connected, and the right end of resistance R5 is connected with the upper step of capacitance C1, is denoted as node VA, and the lower step of capacitance C1, C2 are grounded.
6. control circuit according to claim 1, which is characterized in that the circuit includes a phase inverter and a LS lock
Storage.Enable signal is inputted from the anode of phase inverter INV, and the negative terminal of phase inverter INV is connected with the ends A of LS latch, and LS is latched
The ends AN of device are connected with the anode of INV, receive input signal；The ends the Y1 ports output control signal CONT1, Y2 of LS latch are defeated
Go out to control signal CONT2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810365621.8A CN108448891A (en) | 2018-04-23 | 2018-04-23 | A kind of regulator circuit based on charge pump construction |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810365621.8A CN108448891A (en) | 2018-04-23 | 2018-04-23 | A kind of regulator circuit based on charge pump construction |
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| CN108448891A true CN108448891A (en) | 2018-08-24 |
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| CN201810365621.8A Pending CN108448891A (en) | 2018-04-23 | 2018-04-23 | A kind of regulator circuit based on charge pump construction |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224586A (en) * | 2019-06-28 | 2019-09-10 | 西安微电子技术研究所 | A kind of high-voltage driving circuit based on charge pump |
| CN114137294A (en) * | 2020-09-04 | 2022-03-04 | 长鑫存储技术有限公司 | Voltage detection circuit and charge pump circuit |
| CN114257084A (en) * | 2021-12-24 | 2022-03-29 | 恒烁半导体(合肥)股份有限公司 | Charge pump circuit with quick start function and application thereof |
| CN115129102A (en) * | 2022-05-27 | 2022-09-30 | 深圳市泰德半导体有限公司 | Low dropout regulator circuit and power management chip |
| US11703527B2 (en) | 2020-09-04 | 2023-07-18 | Changxin Memory Technologies, Inc. | Voltage detection circuit and charge pump circuit |
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| US20010046165A1 (en) * | 2000-03-29 | 2001-11-29 | Paolo Rolandi | Low-consumption charge pump for a nonvolatile memory |
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| CN107357351A (en) * | 2017-08-15 | 2017-11-17 | 电子科技大学 | A kind of NMOS LDO based on self-powered charge pump architecture |
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| CN106685415A (en) * | 2017-02-07 | 2017-05-17 | 深圳市华讯方舟微电子科技有限公司 | Charge pump circuit and phase-locked loop |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224586A (en) * | 2019-06-28 | 2019-09-10 | 西安微电子技术研究所 | A kind of high-voltage driving circuit based on charge pump |
| CN114137294A (en) * | 2020-09-04 | 2022-03-04 | 长鑫存储技术有限公司 | Voltage detection circuit and charge pump circuit |
| US11703527B2 (en) | 2020-09-04 | 2023-07-18 | Changxin Memory Technologies, Inc. | Voltage detection circuit and charge pump circuit |
| CN114257084A (en) * | 2021-12-24 | 2022-03-29 | 恒烁半导体(合肥)股份有限公司 | Charge pump circuit with quick start function and application thereof |
| CN114257084B (en) * | 2021-12-24 | 2023-07-18 | 恒烁半导体(合肥)股份有限公司 | Charge pump circuit with quick start function and application thereof |
| CN115129102A (en) * | 2022-05-27 | 2022-09-30 | 深圳市泰德半导体有限公司 | Low dropout regulator circuit and power management chip |
| CN115129102B (en) * | 2022-05-27 | 2023-11-17 | 深圳市泰德半导体有限公司 | Low-dropout linear voltage regulator circuit and power management chip |
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