CN108390549B - A kind of gate drive circuit reducing dead time - Google Patents

A kind of gate drive circuit reducing dead time Download PDF

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Publication number
CN108390549B
CN108390549B CN201810344114.6A CN201810344114A CN108390549B CN 108390549 B CN108390549 B CN 108390549B CN 201810344114 A CN201810344114 A CN 201810344114A CN 108390549 B CN108390549 B CN 108390549B
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output end
connect
input terminal
module
nmos tube
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CN108390549A (en
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李泽宏
熊涵风
赵念
罗仕麟
张成发
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/084—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A kind of gate drive circuit reducing dead time, belongs to electronic circuit technology.Including first voltage detection module, second voltage detection module, logic module, drive module and driving resistance, first voltage detection module is used to detect the reverse-biased of the parasitic diode of external target transistors, second voltage detection module is used to detect the positively biased state of the parasitic diode of target transistors, when the conducting of the parasitic diode positively biased of target power pipe, logic module exports high level, and drive module opens target power pipe；When the parasitic diode of target power pipe is suddenly from when being just biased to reverse-biased, logic module exports low level, and drive module closes target power pipe；For logic module for controlling whether target transistors are connected, drive module is used to drive the grid of target transistors.The present invention reduces diode current flow loss by shortening dead time, and has overcurrent protection function when target power pipe is opened, and prevents short-circuit generation, keeps the circuit more safe and reliable.

Description

A kind of gate drive circuit reducing dead time
Technical field
The invention belongs to electronic circuit technology, a kind of subtracting for inverter or DC-DC converter is particularly related to The gate drive circuit of small dead time.
Background technique
In inverter or DC-DC converter, power MOSFET is often used as switching device.Upper and lower two power MOSFET is controlled by pulse modulation technology (Pulse width modulation, PWM), in order to avoid upper and lower two power Dead time usually is added in upper and lower two power tubes control signal, two power tubes in dead time in MOSFET break-through It is not turned on, electric current carries out afterflow by power MOSFET body diode.However, the presence of dead time causes many problems, Such as the too long distortion that will cause output current wave of dead time, and cause body diode conduction loss to become larger, therefore lead Efficiency decline is caused.
As shown in Figure 1, the left side is boost chopper, the right is three-phase inverting circuit.The two circuits are all made of optocoupler Isolation drive power MOSFET, as shown in Fig. 2, what the grid of power MOSFET was generated by field programmable gate array FPGA Pwm signal IN1 and IN2 control can have a dead time t between the pwm signal IN1 and IN2 of FPGA generationDT, work as high side When MOSFET and downside MOSFET in an off state, electric current can be flowed from the body diode of power MOSFET tube, body diode Conducting, i.e., the t in Fig. 2DCT1And tDCT2Diode current flow generates loss within time.
Summary of the invention
For existing dead time during current driving it is too long caused by the above problem, the present invention proposes a kind of reduction The gate drive circuit of dead time can be used for inverter or DC-DC converter.
Technical solution of the present invention:
A kind of gate drive circuit reducing dead time, for driving target transistors MSH, including first voltage detection mould Block, second voltage detection module, logic module, drive module and driving resistance Rg,
The first voltage detection module includes first voltage comparator Comp1, first resistor R1, the first current source I1With First NDMOS pipe MN1, the first NDMOS pipe MN1Grid connect supply voltage VDD, drain electrode is as first voltage detection The first input end of module simultaneously connects the target transistors MSHDrain electrode, source electrode connects first voltage comparator Comp1 Non-inverting input terminal；First current source I1Forward end connect supply voltage VDD, negative end connection first voltage comparator Comp1 Inverting input terminal and first resistor R1One end, first resistor R1The other end as the first voltage detection module Two input terminals simultaneously connect the target transistors MSHSource electrode；The output end of first voltage comparator Comp1 is as described first The output end of voltage detection module；
The second voltage detection module includes second voltage comparator Comp2, second resistance R2, the second current source I2With 2nd NDMOS pipe MN2, the 2nd NDMOS pipe MN2Grid connect supply voltage VDD, drain electrode is as second voltage detection The first input end of module simultaneously connects the target transistors MSHDrain electrode, source electrode connect second resistance R2One end；Second The non-inverting input terminal of voltage comparator Comp2 connects second resistance R2The other end and the second current source I2Negative end, reverse phase Input terminal as the second voltage detection module the second input terminal and connect the target transistors MSHSource electrode, output Hold the output end as the second voltage detection module；Second current source I2Forward end connect supply voltage VDD；
The logic module includes the first trigger, the second trigger, the first phase inverter G1, the second phase inverter G2, first or Door G3, first with door G4, second with door G5, time delay module and monostable trigger module,
The data input pin of first trigger connects supply voltage VDD, the input end of clock connection second voltage detection The output end of module, reset terminal connect the first input signal INL, the input terminal of output end Q connection monostable trigger module；
The data input pin of second trigger connects supply voltage VDD, the input end of clock connection first voltage detection The output end of module, reset terminal connect the first input signal INL, the input terminal of the disconnected time delay module of output end Q and the Two and door G5First input end；
Second and door G5The second input terminal connection time delay module output end, output end connection first and the of door G4 One input terminal；
First phase inverter G1Input terminal connection monostable trigger module output end, output end connect the second phase inverter G2Input terminal；
First or door G3First input end connect the second phase inverter G2Output end, the connection of the second input terminal is second defeated Enter signal INH, the second input terminal of output end connection first and door G4；
The output end of the input terminal connection first and door G4 of the drive module, output end connect the driving resistance Rg One end, the driving resistance RgThe other end connect the target transistors M as the output end of the gate drive circuitSH's Grid.
Specifically, first trigger and the second trigger are d type flip flop.
Specifically, the monostable trigger module includes third phase inverter G6, the 4th phase inverter G7, the 5th phase inverter G8With First nor gate G9,
Third phase inverter G6Input terminal connect the first nor gate G9First input end and as the monostable trigger mould The input terminal of block, output end connect the 4th phase inverter G7Input terminal；
5th phase inverter G8Input terminal connect the 4th phase inverter G7Output end, output end connect the first nor gate G9 The second input terminal, the first nor gate G9Output end of the output end as the monostable trigger module.
Specifically, the time delay module includes the first PMOS tube M1, the first NMOS tube M2, the second PMOS tube M3, the 2nd NMOS Pipe M4, third PMOS tube M5, third NMOS tube M6, the 4th PMOS tube M7, the 4th NMOS tube M8, 3rd resistor R3And first capacitor C1,
First PMOS tube M1Grid connect the first NMOS tube M2Grid and input terminal as the time delay module, The first NMOS tube M of drain electrode connection2Drain electrode and the second PMOS tube M3With the second NMOS tube M4Grid, source electrode connection second PMOS tube M3, third PMOS tube M5With the 4th PMOS tube M7Source electrode and connect supply voltage VDD；
Third NMOS tube M6Grid connect third PMOS tube M5Grid and the second NMOS tube M4Drain electrode, drain electrode connect Meet third PMOS tube M5Drain electrode and the 4th PMOS tube M7With the 4th NMOS tube M8Grid, source electrode connect the first NMOS tube M2, the second NMOS tube M4With the 4th NMOS tube M8Source electrode；
3rd resistor R3It connects in the second PMOS tube M3With the second NMOS tube M4Drain electrode between, first capacitor C1It connects second NMOS tube M4Drain electrode and source electrode between；
4th PMOS tube M7Drain electrode connect the 4th NMOS tube M8Drain electrode and output end as the time delay module.
Specifically, the drive module includes the cascade phase inverter of even number.
Specifically, the target transistors MSHFor power MOSFET or IGBT.
The invention has the benefit that gate drive circuit proposed by the present invention, can be used for inverter or DC-DC converter, Not additional freewheeling diode, using the parasitic diode of target power pipe as freewheeling diode；It can by reducing dead time The body diode conduction loss for reducing target power pipe, effectively improves efficiency；And there is overcurrent when target power pipe is opened Defencive function prevents short-circuit generation, keeps the circuit more safe and reliable.
Detailed description of the invention
Fig. 1 is inverter and DC-DC converter structural schematic diagram.
Fig. 2 is the circuit diagram and timing diagram using light-coupled isolation driving power MOSFET.
Fig. 3 is a kind of structural schematic diagram of gate drive circuit for reducing dead time provided by the invention.
Fig. 4 is a kind of driver' s timing figure of gate drive circuit for reducing dead time provided by the invention.
Fig. 5 is the structural schematic diagram of monostable trigger module in embodiment.
Fig. 6 is the structural schematic diagram of time delay module in embodiment.
Fig. 7 is the structural schematic diagram of drive module in embodiment.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the technical schemes of the invention are described in detail.
A kind of gate drive circuit reducing dead time proposed by the present invention, is applicable to inverter or DC-DC converter, For driving power MOSFET or IGBT, as shown in figure 3, a kind of gate drive circuit for reducing dead time provided by the invention, For driving target transistors MSH, including first voltage detection module, second voltage detection module, logic module, drive module With driving resistance Rg, first voltage detection module includes first voltage comparator Comp1, first resistor R1, the first current source I1With First NDMOS pipe MN1, the first NDMOS pipe MN1Grid connect supply voltage VDD, drain electrode is as first voltage detection module First input end and linking objective transistor MSHDrain electrode, source electrode connect first voltage comparator Comp1 homophase input End；First current source I1Forward end connect supply voltage VDD, negative end connect first voltage comparator Comp1 reverse phase it is defeated Enter end and first resistor R1One end, first resistor R1Second input terminal and company of the other end as first voltage detection module Meet target transistors MSHSource electrode；Output end of the output end of first voltage comparator Comp1 as first voltage detection module； Second voltage detection module includes second voltage comparator Comp2, second resistance R2, the second current source I2It is managed with the 2nd NDMOS MN2, the 2nd NDMOS pipe MN2Grid connect supply voltage VDD, first input end of the drain electrode as second voltage detection module And linking objective transistor MSHDrain electrode, source electrode connect second resistance R2One end；The same phase of second voltage comparator Comp2 Input terminal connects second resistance R2The other end and the second current source I2Negative end, inverting input terminal as second voltage examine Survey the second input terminal and linking objective transistor M of moduleSHSource electrode, output of the output end as second voltage detection module End；Second current source I2Forward end connect supply voltage VDD.First NDMOS pipe MN1With the 2nd NDMOS pipe MN2Effect be electricity Press clamper tube.
Two input terminals of first voltage detection module connect external target transistors MSHDrain electrode and source electrode, for examining Survey external target transistors MSHParasitic diode reverse-biased, detect whether reverse-biased conducting, the value of threshold voltage can Pass through first resistor R1With the first current source I1It adjusts, i.e. VTH2=I1×R1.Two input terminals of second voltage detection module connect Meet external target transistors MSHDrain electrode and source electrode, for detecting external target transistors MSHParasitic diode just Inclined state detects whether that positively biased is connected, and the value of threshold voltage can pass through second resistance R2With the second current source I2It adjusts, i.e. VTH1 =I2×R2.As target power pipe MSHBody diode positively biased conducting when, logic module export high level, drive module open mesh Mark power tube MSH；As target power pipe MSHBody diode suddenly from when being just biased to reverse-biased, logic module exports low level, drives Dynamic model block closes target power pipe MSH。
Logic module includes the first trigger, the second trigger, the first phase inverter G1, the second phase inverter G2, first or door G3, first with door G4, second with door G5, time delay module and monostable trigger module, the data input pin of the first trigger connects electricity Source voltage VDD, the output end of input end of clock connection second voltage detection module, reset terminal the first input signal of connection INL, the input terminal of output end Q connection monostable trigger module；The data input pin of second trigger connects supply voltage VDD, Its input end of clock connects the output end of first voltage detection module, and reset terminal connects the first input signal INL, output end The input terminal of the disconnected time delay module of Q and second and door G5First input end；Second and door G5The second input terminal connect delay The output end of module, the first input end of output end connection first and door G4；First phase inverter G1Input terminal connection it is monostable The output end of state trigger module, output end connect the second phase inverter G2Input terminal；First or door G3First input end connection Second phase inverter G2Output end, the second input terminal connects the second input signal INH, and output end connection first is with door G4 Second input terminal；The output end of the input terminal connection first and door G4 of drive module, output end connection driving resistance RgOne End drives resistance RgOutput end linking objective transistor M of the other end as gate drive circuitSHGrid.Drive resistance Rg It can prevent target transistors MSHResonance occurs for grid when driving.First input signal INL and the second input signal INH be all by Externally input pulse width modulation (PWM) signal, and the first input signal INL and the second input signal INH can not be simultaneously High level.
First trigger and the second trigger can be d type flip flop, JK flip-flop or any other trigger, the present embodiment It is middle to use d type flip flop.Logic module is for controlling external target transistors MSHWhether be connected, drive module is external for driving Target transistors MSHGrid.
It is illustrated in figure 5 a kind of realization circuit structure of monostable trigger module, including third phase inverter G6, the 4th reverse phase Device G7, the 5th phase inverter G8With the first nor gate G9, third phase inverter G6Input terminal connect the first nor gate G9First input It holds and the input terminal as monostable trigger module, output end connects the 4th phase inverter G7Input terminal；5th phase inverter G8's Input terminal connects the 4th phase inverter G7Output end, output end connect the first nor gate G9The second input terminal, the first nor gate G9Output end of the output end as monostable trigger module.
It is illustrated in figure 6 a kind of realization circuit structure of time delay module, including the first PMOS tube M1, the first NMOS tube M2, Two PMOS tube M3, the second NMOS tube M4, third PMOS tube M5, third NMOS tube M6, the 4th PMOS tube M7, the 4th NMOS tube M8, Three resistance R3With first capacitor C1, the first PMOS tube M1Grid connect the first NMOS tube M2Grid and as time delay module Input terminal, the first NMOS tube M of drain electrode connection2Drain electrode and the second PMOS tube M3With the second NMOS tube M4Grid, source electrode Connect the second PMOS tube M3, third PMOS tube M5With the 4th PMOS tube M7Source electrode and connect supply voltage VDD；Third NMOS tube M6 Grid connect third PMOS tube M5Grid and the second NMOS tube M4Drain electrode, drain electrode connection third PMOS tube M5Drain electrode And the 4th PMOS tube M7With the 4th NMOS tube M8Grid, source electrode connect the first NMOS tube M2, the second NMOS tube M4With the 4th NMOS tube M8Source electrode；3rd resistor R3It connects in the second PMOS tube M3With the second NMOS tube M4Drain electrode between, first capacitor C1It connects In the second NMOS tube M4Drain electrode and source electrode between；4th PMOS tube M7Drain electrode connect the 4th NMOS tube M8Drain electrode and conduct The output end of time delay module.
Drive module can be cascaded by even number of inverters and be formed, and be illustrated in figure 7 a kind of way of realization of drive module, by Four phase inverters cascade to be formed, and a phase inverter includes a NMOS tube and a PMOS tube.
The specific working principle of the present embodiment: first voltage detection module is described in detail by taking driving power MOSFET as an example Pressure difference between the drain electrode of power MOSFET body diode and source electrode is detected, when pressure difference is greater than between power MOSFET drain electrode and source electrode VTH2When, there is short circuit current in horse back switch-off power MOSFET when power MOSFET tube being prevented to be connected, protect power MOSFET.Such as Timing diagram shown on the right of Fig. 4, when pressure difference is greater than V between the drain electrode of external power tube and source electrodeTH2, first voltage comparator Comp1 High level is exported, the output end Q of the second trigger is non-to be lower from height, by delay Dely module and second and door G5It is connected to One and door G4Input terminal, first with door G4Output low level, drive module close power MOSFET.Wherein adjust VTH2Size It can be by adjusting first resistor R1With the first current source I1It realizes, expression formula are as follows: VTH2=I1×R1。
Second voltage detection module detect external power MOSFET body diode whether positively biased be connected, such as the left side Fig. 4 institute The timing diagram shown, when pressure difference is less than V between the drain electrode of external power MOSFET tube and source electrodeTH1When it is believed that power MOSFET body Diode has been connected, and second voltage comparator Comp2 exports high level, and the first trigger output end Q is got higher from low, monostable touching It is t that hair 1-shot module, which can generate a width,DTHigh impulse, be connected to after being handled by logic module drive module input. Drive module is connected to the grid of external power MOSFET, and power MOSFET is opened.When by tDTTurn-on time after, power Whether MOSFET continues conducting is determined by the second input signal INH.Wherein adjust VTH1Size can be by adjusting second resistance R2With Second current source I2It realizes, expression formula are as follows: VTH1=-I2×R2。
To sum up, the invention proposes a kind of suitable for inverter or the gate drive circuit of DC-DC converter, dead by reducing Area's time cpable of lowering power MOSFET body diode conduction loss, effectively improves efficiency；And had when MOSFET is opened Defencive function is flowed, short-circuit generation is prevented, keeps the circuit more safe and reliable.
It is understood that the present invention is not limited to the accurate configuration being illustrated above and components.Claims are not being departed from Protection scope on the basis of, can be to method and structure above the step of sequence, details and operation make various modifications, change and Optimization.

Claims (6)

1. a kind of gate drive circuit for reducing dead time, for driving target transistors (MSH), which is characterized in that including first Voltage detection module, second voltage detection module, logic module, drive module and driving resistance (Rg),
The first voltage detection module includes first voltage comparator (Comp1), first resistor (R1), the first current source (I1) (MN is managed with the first NDMOS1), the first NDMOS manages (MN1) grid connect supply voltage (VDD), drain electrode is used as described first The first input end of voltage detection module simultaneously connects the target transistors (MSH) drain electrode, source electrode connection first voltage compare The non-inverting input terminal of device (Comp1)；First current source (I1) forward end connect supply voltage (VDD), negative end connection first The inverting input terminal and first resistor (R of voltage comparator (Comp1)1) one end, first resistor (R1) the other end be used as described in Second input terminal of first voltage detection module simultaneously connects the target transistors (MSH) source electrode；First voltage comparator (Comp1) output end of the output end as the first voltage detection module；
The second voltage detection module includes second voltage comparator (Comp2), second resistance (R2), the second current source (I2) (MN is managed with the 2nd NDMOS2), the 2nd NDMOS manages (MN2) grid connect supply voltage (VDD), drain electrode is used as described second The first input end of voltage detection module simultaneously connects the target transistors (MSH) drain electrode, source electrode connect second resistance (R2) One end；The non-inverting input terminal of second voltage comparator (Comp2) connects second resistance (R2) the other end and the second current source (I2) negative end, inverting input terminal as the second voltage detection module the second input terminal and to connect the target brilliant Body pipe (MSH) source electrode, output end of the output end as the second voltage detection module；Second current source (I2) forward direction End connection supply voltage (VDD)；
The logic module includes the first trigger, the second trigger, the first phase inverter (G1), the second phase inverter (G2), first or Door (G3), first with door (G4), second with door (G5), time delay module and monostable trigger module,
The data input pin of first trigger connects supply voltage (VDD), input end of clock connects the second voltage and detects mould The output end of block, reset terminal connect the first input signal (INL), the input terminal of output end Q connection monostable trigger module；
The data input pin of second trigger connects supply voltage (VDD), input end of clock connects the first voltage and detects mould The output end of block, reset terminal connect the first input signal (INL), the input terminal of the disconnected time delay module of output end Q and the Two and door (G5) first input end；
Second and door (G5) the second input terminal connection time delay module output end, the of output end connection first and door (G4) One input terminal；
First phase inverter (G1) input terminal connection monostable trigger module output end, output end connect the second phase inverter (G2) input terminal；
First or door (G3) first input end connect the second phase inverter (G2) output end, the connection of the second input terminal is second defeated Enter signal (INH), the second input terminal of output end connection first and door (G4)；
The input terminal connection first of the drive module and the output end of door (G4), output end connect the driving resistance (Rg) One end, the driving resistance (Rg) the other end connect the target transistors as the output end of the gate drive circuit (MSH) grid.
2. it is according to claim 1 reduce dead time gate drive circuit, which is characterized in that first trigger and Second trigger is d type flip flop.
3. the gate drive circuit according to claim 1 for reducing dead time, which is characterized in that the monostable trigger mould Block includes third phase inverter (G6), the 4th phase inverter (G7), the 5th phase inverter (G8) and the first nor gate (G9),
Third phase inverter (G6) input terminal connect the first nor gate (G9) first input end and as the monostable trigger mould The input terminal of block, output end connect the 4th phase inverter (G7) input terminal；
5th phase inverter (G8) input terminal connect the 4th phase inverter (G7) output end, output end connect the first nor gate (G9) the second input terminal, the first nor gate (G9) output end of the output end as the monostable trigger module.
4. the gate drive circuit according to claim 1 for reducing dead time, which is characterized in that the time delay module includes First PMOS tube (M1), the first NMOS tube (M2), the second PMOS tube (M3), the second NMOS tube (M4), third PMOS tube (M5), third NMOS tube (M6), the 4th PMOS tube (M7), the 4th NMOS tube (M8), 3rd resistor (R3) and first capacitor (C1),
First PMOS tube (M1) grid connect the first NMOS tube (M2) grid and input terminal as the time delay module, The first NMOS tube (M of drain electrode connection2) drain electrode and the second PMOS tube (M3) and the second NMOS tube (M4) grid, source electrode connect Meet the second PMOS tube (M3), third PMOS tube (M5) and the 4th PMOS tube (M7) source electrode and connect supply voltage (VDD)；
Third NMOS tube (M6) grid connect third PMOS tube (M5) grid and the second NMOS tube (M4) drain electrode, drain electrode Connect third PMOS tube (M5) drain electrode and the 4th PMOS tube (M7) and the 4th NMOS tube (M8) grid, source electrode connection the One NMOS tube (M2), the second NMOS tube (M4) and the 4th NMOS tube (M8) source electrode；
3rd resistor (R3) connect in the second PMOS tube (M3) and the second NMOS tube (M4) drain electrode between, first capacitor (C1) connect Two NMOS tube (M4) drain electrode and source electrode between；
4th PMOS tube (M7) drain electrode connect the 4th NMOS tube (M8) drain electrode and output end as the time delay module.
5. the gate drive circuit according to claim 1 for reducing dead time, which is characterized in that the drive module includes The cascade phase inverter of even number.
6. the gate drive circuit according to any one of claims 1-5 for reducing dead time, which is characterized in that the mesh Mark transistor (MSH) it is power MOSFET or IGBT.
CN201810344114.6A 2018-04-17 2018-04-17 A kind of gate drive circuit reducing dead time Expired - Fee Related CN108390549B (en)

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