CN108362995A - A kind of application method of the FPGA of innovation - Google Patents
A kind of application method of the FPGA of innovation Download PDFInfo
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- CN108362995A CN108362995A CN201810094424.7A CN201810094424A CN108362995A CN 108362995 A CN108362995 A CN 108362995A CN 201810094424 A CN201810094424 A CN 201810094424A CN 108362995 A CN108362995 A CN 108362995A
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Abstract
The invention discloses a kind of application methods of the FPGA of innovation, innovatively corresponding test device are designed using FPGA circuitry and the adjustability of output input standard and pattern, instead of existing measuring apparatus respective electronics.It not only greatly improves performance while also greatly reducing circuit power consumption, the physical size and cost of key Design.In addition, the high speed data transfer performance of FPGA is also innovatively used in a large amount of test data high-speed transfers to the device directly being connect with detected element, will to solve one of key Design micromation bottleneck.Further, the interlock circuit that direct current and low-speed performance are surveyed to formula is kept completely separate with high speed testing, just connect with detected element two circuits is made to be independent of each other when implementing each self-test, and can also be connected together needing to be commonly connected together the when of doing corresponding test.Therefore power consumption, physical size and cost are greatly reduced, there is good marketing application prospect.
Description
Technical field
The present invention relates to Electronic Testing Technology fields, more particularly, to a kind of application method of the FPGA of innovation.
Background technology
Integrated circuit test device includes for driving detected element and receiving the circuit of detected element output signal.It is existing
It is to be realized with the special electronic device specially designed in technology.It has the disadvantages that：
1, because being for specially design and the manufacture of this purposes, dosage is less, therefore is designed and manufactured as high；
2, because its driving and receiving voltage are continuously controllably to adjust, so to reach very difficult at a high speed, and very due to power consumption
Greatly, to be miniaturized because of heat dissipation problem.
In addition, in the prior art to do the splitting element for adjusting the controlled delay circuit of each channel sequential and being, this
But also micromation cannot achieve.Moreover, in the prior art, not obtaining efficiently separating making between high speed and low speed test circuit
It obtains low-speed circuits to have aggravated the driving of high speed circuit and received load, this is also to reduce power and the significant bottleneck of micromation.It is existing
Have in technology, in order to reach high speed test, store test data is to use the SRAM of extremely high speed, but the disadvantage is that price is extremely high
Expensive and capacity is small.
In view of this, the prior art has much room for improvement and improves.
Invention content
In view of the deficiencies in the prior art, present invention aims at provide a kind of test device based on FPGA.It aims to solve the problem that
The problems such as power is excessive existing for the integrated circuit test device of the prior art, and micromation is difficult, manufacturing cost is high.
Technical scheme is as follows：
A kind of test device based on FPGA, is tested for the electronic component performance to detected element, FPGA (Field-
Programmable Gate Array), i.e. the current application of field programmable gate array is fixed with fixed circuit devcie
Connection goes to complete a kind of required function, rather than a variety of different to go test to be attached thereto from the connection of different circuit devcies
Circuit devcie.
FPGA for testing device described here is by interconvertible attachment device at any time and different circuit devcies
Connect and according to the circuit of measured element and input and output standard, the corresponding change FPGA circuitry of delay and pattern etc. and
Input and output standard, delay and pattern etc. coordinate to achieve the purpose that circuit devcie that test is attached thereto.
The test device based on FPGA, wherein the FPGA circuitry further includes one by FPGA input and output institute band
Adjustable delay circuit.
The test device based on FPGA, wherein the FPGA circuitry is directly connected to detected element.
The test device based on FPGA, wherein the FPGA circuitry is with Test System Controller and using in DDR
The test data Memory linkage deposited, the test data memory are reached test data by high speed SERDES transmission modes described
FPGA circuitry is for testing detected element.The high speed high power capacity and low cost of DDR memories are solved using conventional high rate SRAM
Deficiency.As long as and the limitation for DDR memories per secondary reading multibyte considers to look after this when generating test data
Point just can avoid being affected.
The test device based on FPGA, wherein the FPGA circuitry produces system with XILINX and ALTERA companies
Other producer's elements of FPGA can also use.
The test device based on FPGA, which is characterized in that it is by 20 that the FPGA circuitry, which receives test data,
A rate up to the SERDES of 4 to 25G (ranging up to 25G) from 1 receive, and be divided into multiple and different rates channel and each by
FIFO does data time sequence synchronization, then send the port to different input and output standards and pattern respectively, to do driving data or
Do the correction data for receiving data.
The test device based on FPGA, which is characterized in that the FPGA circuitry is according to the circuit for being measured element
And input and output standard, time delay and pattern change FPGA circuitry, circuit delay and input and output standard, time at any time
Delay and pattern come coordinate circuit-under-test device with achieve the purpose that test circuit-under-test device.
The test device based on FPGA, wherein further include high speed test circuit or low speed measurement circuit；The height
Fast measurement circuit is connected to detected element line with low speed measurement circuit by testing needle and special attachment device respectively different time
So that high speed test circuit is connect in different time respectively with low speed measurement circuit with detected element on the contact point of road plate
It carries out high speed test and low speed test is kept completely separate with reaching respective circuit.
The test device based on FPGA, wherein further include high speed test circuit and low speed measurement circuit；Low speed is surveyed
The testing needle of examination circuit is connected on the contact point of detected element wiring board, and the testing needle of high speed test circuit is connected to low speed p-wire
On the contact point at the back side of the mainboard on road, so that low speed measurement circuit is connect simultaneously with high speed test circuit and detected element
Test needed for carrying out.
The test device based on FPGA of the present invention innovatively uses FPGA circuitry and output input standard, time
The adjustability of delay and pattern designs corresponding test device, instead of existing measuring apparatus respective electronics.Not only pole
It improves performance and integrated level greatly while also greatly reducing circuit power consumption, the physical size and cost of key Design.In addition,
Also innovatively use FPGA high speed data transfer performance by a large amount of test data high-speed transfers to directly with detected element company
On the device connect, one of bottleneck is miniaturized to solve key Design.
The present invention creatively devises the circuit and input and output mark that FPGA just can be changed at any time without artificial compiling
Accurate and pattern control method, the method directly will according to tested element circuitry and required input and output standard and pattern
Corresponding data makes required numerical value into the setting data of FPGA, then with this setting data is reset FPGA to keep FPGA electric
Road and input and output standard and pattern quickly change to the desirable value to match with detected element.
The interlock circuit that direct current and low-speed performance are innovatively surveyed formula by the present invention is kept completely separate with high speed testing,
The test method for making two circuits be independent of each other that just connects with detected element when implementing each self-test makes high speed test load substantially
Degree reduces, and can also be connected together needing to be commonly connected together the when of doing corresponding test.Therefore work(is greatly reduced
Consumption, physical size and cost have good marketing application prospect.
Description of the drawings
Fig. 1 is the test schematic diagram of the first embodiment of test device of the present invention.
Fig. 2 be test device of the present invention first embodiment in the test device based on FPGA schematic diagram.
Fig. 3 is that the embodiment high speed measurement circuit connection of the test device based on FPGA of the present invention carries out high speed test
Schematic diagram.
Fig. 4 carries out low speed test for low speed measurement circuit connection in the embodiment of the test device based on FPGA of the present invention
Schematic diagram.
Fig. 5 is the embodiment high speed measurement circuit and low speed measurement circuit group of the test device based on FPGA of the present invention
Close the schematic diagram used.
Specific implementation mode
The present invention provides a kind of test device based on FPGA, to make the purpose of the present invention, technical solution and effect more
Clear, clear, the present invention is described in more detail below.It should be appreciated that specific embodiment described herein is only used to
It explains the present invention, is not intended to limit the present invention.
The normal use of FPGA (Field-Programmable Gate Array field programmable gate arrays) is by it
Mounted on fixed wiring board, it is fixed with the circuit element that it connects.The input and output standard and pattern of FPGA
According to the element function standard setting to connect with it, do not need to change at any time.
It can be changed according to the demand of different detected elements present invention utilizes FPGA its circuit and its circuit, input are defeated
Go out all standard, time delays and pattern can be set to the existing integrated circuits used of the overwhelming majority corresponding all standard and
This feature of pattern, for testing various integrated circuits.It is disclosed by the invention first according to being measured based on the test device of FPGA
The circuit and input and output standard of part, time delay and pattern change the circuit and input and output standard of FPGA at any time, when
Between be delayed and pattern (the adjustable delay circuit for including FPGA input and output institute band) coordinates to achieve the purpose that test.Because of mesh
It is preceding without user so use FPGA, so FPGA production firms be not provided at any time change FPGA input and output standard and
The related software of pattern is supplied to user.Therefore, the present invention is creatively devised just can be changed at any time without artificial compiling
The circuit of FPGA and the control method of input and output standard and pattern, the method is according to tested element circuitry and required
Input and output standard and pattern directly make corresponding data in the setting data of FPGA into required numerical value, then will with this setting data
FPGA resets that FPGA circuitry and input and output standard and pattern is made quickly to change to the institute to match with detected element
It needs to be worth.It uses FPGA that can design in this way and tests electronic circuit accordingly used in the current test equipment of circuitry instead.Tool
Body method is the advance method for comparing different circuits setting files, by the circuit of institute's change in need (including other performances ginseng
Any other change of number etc.) corresponding delta data is found out and database A is caused to achieve in correlation setting file, in reality
In the system operation of border, with one " control processor by the associated change data of the circuit for needing to change at that time (or other changes) from
It is sought out in database A and imports this delta data and FPGA is set with the setting file that this is changed again using setting file at present
Changed (or other changes) with reaching required circuit.
Referring to Fig. 1, its test schematic diagram for the first embodiment of the test device based on FPGA of the present invention.Its
In, the test device 200 based on FPGA is separately connected Test System Controller and test data memory 100, user interface
PC 400 and detected element 300, wherein the test data memory in described 100 use DDR memories as test data memory with
Achieve the effect that high speed high power capacity and low cost, system controller is to control setting for test system various functions in described 100
It sets operation and test data is provided and pass through pre-line (using FPGA) test detected element to pre-line.Test data is transmitted
It is to be sent to based on FPGA's by the SERDES (being indicated with 20of 4G SERDES in figure) of 20 4G rates (25G can be reached)
Test device simultaneously directly tests detected element by the test device based on FPGA, this is one of the key point of invention.In figure
User interface PC 400 is connect by the interfaces PCIE with 100 and is connect with 200 to reach user to the total of system by USB interface
Control and test data control the reading and download of data and test result data etc..
Also referring to Fig. 2, in the first embodiment of the test device based on FPGA of the present invention based on FPGA's
FPGA (XILINX model XC7K325T) schematic diagram of test device.It is the emphasis of the present invention, is to use in the present embodiment
The FPGA of XILINX.Test data is received up to the SERDES of 4G from 100 with 20 rates, and multiple and different rates are then divided into
Channel and do data time sequence each by FIFO and synchronize and send port to different input and output standards and pattern respectively again, to
It does driving data or does the correction data for receiving data, such as the XOR in figure to compare, output C1 to C6 is comparing result,
1 such as will be generated with reception data comparison difference, then output to Test System Controller makes it stop testing and reading after OR
Dependence test is returned not by data, address and C1 occur for such as mistake to C6 values.Test system pre-line is not fixed while
It can be changed according to different detected elements, such as if in detected element DUT being DDR2, test system pre-line figure
In DDR3 controllers will be configured to DDR2 controllers, and so on.
STM32MCU is to change XC7K325T internal wirings etc. to quickly current setting XC7K325T to reach current.
STM32MCU is to carry out high speed setting to XC7K325T by the parallel set-up modes of LOCAL BUS.STM32MCU passes through simultaneously
SPI4 Interface Controls XC7K325T simultaneously reads the test result data in XC7K325T.
FLASH MEM (flash memory) in figure are the database and related data for storing that XC7K325T is arranged.
DATA GENERATOR in figure are test data generator to according to particular element is tested, (such as type of memory is first
Part etc.) demand at runtime now generate needed for test data.
ADDR GENERATOR in figure are address generator to according to tested particular element (such as type of memory element
Deng) demand at runtime now generate needed for address.
An important application of the above DATA GENERATOR and ADDR GENERATOR is used in implementation measurement of near distance
Method.This is that a kind of test method of innovation of the present invention is surveyed based on the innovation with the theoretical entirely different present invention of traditional test
Examination is theoretical.The form that the innovation theory of testing, which is the mode of production based on existing most of element, to be occurred with production flaw with it is general
Rate, key theory be based on probability short-circuit between each conducting wire and its from each other nearest physical distance at the geometry order of magnitude
Inverse ratio, it is simple understand be exactly mutually distance it is remote just without being mutually measured, in this way can with geometric progression compression verification data.Mesh
The mode of production of preceding major part element especially integrated circuit component is the method for layered plane wiring, low coverage according to the present invention
It is exactly every line and interlayer accident from test method (both closest approach had not just had to test every other line or every one layer between conducting wire).
Here the structure and function of DATA GERERATOR and ADDR GENERATOR be according to detected element and change to reach
The test data of generation and address can meet the requirement of measurement of near distance method.This is especially great to test memory element meaning.
It is connected directly based on the test device of FPGA and detected element (DUT), the internal MOD of the detected element (DUT)
Circuit can be any circuit, because detected element can be the element of various different performances.
Referring to Fig. 3, showing with high speed test circuit in its embodiment for the test device based on FPGA of the present invention
It is intended to.As shown, DUT indicates that detected element, DUT Board indicate the circuit board of detected element, Tester FEMB tables in figure
Show that the test device based on FPGA, HSCKT indicate that high speed test circuit, downward arrow indicate testing needle, it will with motor machine
High speed test wiring board pushes up, and the contact point on high speed test wiring board is made to be connected to the test on the preposition mainboard of test system
Needle, so that high speed test circuit is connect with detected element carries out high speed test.
Please continue to refer to Fig. 4, for band low speed measurement circuit in the embodiment of the test device based on FPGA of the present invention
Schematic diagram.As shown, DUT indicates that detected element, DUT Board indicate the circuit board of detected element in figure,
TesterFEMB indicates that the test device (also referred to as testing the testing advanced mainboard of system) based on FPGA, LSCKT indicate low speed test
Circuit, downward arrow indicate testing needle.High speed test wiring board is pushed down on motor machine and concedes space, then low speed is surveyed
Examination wiring board, which is shifted to the right appropriate location onto and rethought, to be pushed away, and the contact point on plate is made to be connected to the test on the preposition mainboard of test system
Needle, so that low speed measurement circuit is connect with detected element carries out low speed test.
Please continue to refer to Fig. 5, for the test device based on FPGA of the present invention embodiment high speed measurement circuit and
The schematic diagram that low speed measurement circuit is applied in combination.High speed test wiring board is pushed down on motor machine and concedes space by it, then will
Low speed measurement circuit plate, which is shifted to the right appropriate location onto and rethought, to be pushed away, and the contact point on plate is made to be connected on the preposition mainboard of test system
Testing needle, then high speed test wiring board is pushed up, make the testing needle that the contact point on plate is connected in low speed test back from
And low speed measurement circuit is made to connect the test needed for carrying out with high speed test plate and detected element.
Present invention utilizes the newest Highspeed Data Transmission Technology " SERDES " in FPGA by mass data high speed pass to it is small
So that measuring head is miniaturizated to possibility on the FPGA elements of size multiplex roles.In addition design of the invention can be by direct current and low speed
The interlock circuit of performance test is kept completely separate with high speed testing, and just connecting with detected element when implementing each self-test makes two
Circuit does not influence mutually, and can also be connected together needing to be commonly connected together the when of doing corresponding test.
In conclusion the test device based on FPGA of the present invention, innovatively uses FPGA circuitry and output input
The test device that the adjustability of standard, time delay and pattern is designed, instead of and surmounted existing measuring apparatus.Not only greatly
It improves performance while also greatly reducing circuit power consumption, the physical size and cost of key Design.In addition, also innovatively
Using the high speed data transfer performance of FPGA by a large amount of test data high-speed transfers to the device directly being connect with detected element,
Solves one of key Design micromation bottleneck.In addition also use DDR memories as test data memory to reach high at high speed
The effect of capacity and low cost.Further, the interlock circuit and high speed testing of direct current and low-speed performance survey formula is complete
Separation, just connecting with detected element when implementing each self-test makes two circuits be independent of each other, and is needing to be commonly connected together
It can also be connected together when doing corresponding test..Therefore power consumption, physical size and cost are greatly reduced, had good
Marketing application prospect.
It should be understood that the application of the present invention is not limited to the above for those of ordinary skills can
With improvement or transformation based on the above description, all these modifications and variations should all belong to the guarantor of appended claims of the present invention
Protect range.
Claims (2)
1. a kind of application method of the FPGA of innovation, for the current FPGA circuitry that quickly changes without being subjected to artificial compiling and phase
Close operation；It is preserved it is characterized in that, will need the circuit changed that corresponding delta data in file is arranged in correlation, in practical system
This delta data is arranged with being used at present with importing in file from taking-up in preservation again in running now for system, then is changed with this
Setting file setting FPGA changed with reaching required circuit.
2. the application method of the FPGA of innovation according to claim 1 a kind of, which is characterized in that in advance with the different electricity of comparison
The method that file is arranged in road, by circuit (include other performance parameters etc. any other the change) correlation of institute's change in need
Corresponding delta data is found out and database A is caused to achieve in setting file, in real system operation, with one " control process
The associated change data for needing the circuit changed at that time are sought out from database A and import this delta data and used at present by device
The setting file setting FPGA that file is changed with this again is arranged to reach required circuit to change.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810094424.7A CN108362995A (en) | 2013-10-12 | 2013-10-12 | A kind of application method of the FPGA of innovation |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810094424.7A CN108362995A (en) | 2013-10-12 | 2013-10-12 | A kind of application method of the FPGA of innovation |
| CN201310475616.XA CN104569780A (en) | 2013-10-12 | 2013-10-12 | Testing device based on FPGA (field programmable gate array) |
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| CN201310475616.XA Division CN104569780A (en) | 2013-10-12 | 2013-10-12 | Testing device based on FPGA (field programmable gate array) |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810094424.7A Pending CN108362995A (en) | 2013-10-12 | 2013-10-12 | A kind of application method of the FPGA of innovation |
| CN201810094509.5A Pending CN108362996A (en) | 2013-10-12 | 2013-10-12 | A kind of " measurement of near distance " theory and method |
| CN201310475616.XA Pending CN104569780A (en) | 2013-10-12 | 2013-10-12 | Testing device based on FPGA (field programmable gate array) |
| CN201810094067.4A Pending CN108362994A (en) | 2013-10-12 | 2013-10-12 | A kind of test device based on the test separation of high low speed |
| CN202210197171.2A Pending CN114660435A (en) | 2013-10-12 | 2013-10-12 | FPGA-based testing device |
| CN201810094030.1A Pending CN108333500A (en) | 2013-10-12 | 2013-10-12 | A kind of test device based on DDR |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810094509.5A Pending CN108362996A (en) | 2013-10-12 | 2013-10-12 | A kind of " measurement of near distance " theory and method |
| CN201310475616.XA Pending CN104569780A (en) | 2013-10-12 | 2013-10-12 | Testing device based on FPGA (field programmable gate array) |
| CN201810094067.4A Pending CN108362994A (en) | 2013-10-12 | 2013-10-12 | A kind of test device based on the test separation of high low speed |
| CN202210197171.2A Pending CN114660435A (en) | 2013-10-12 | 2013-10-12 | FPGA-based testing device |
| CN201810094030.1A Pending CN108333500A (en) | 2013-10-12 | 2013-10-12 | A kind of test device based on DDR |
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| CN113821019A (en) * | 2021-11-22 | 2021-12-21 | 成都市卫莱科技有限公司 | FPGA high-speed transceiver and dynamic control method thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108362996A (en) | 2018-08-03 |
| CN104569780A (en) | 2015-04-29 |
| CN108362994A (en) | 2018-08-03 |
| CN108333500A (en) | 2018-07-27 |
| CN114660435A (en) | 2022-06-24 |
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