CN102098698A - Method and system for testing error rate - Google Patents
Method and system for testing error rate Download PDFInfo
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- CN102098698A CN102098698A CN2010105715500A CN201010571550A CN102098698A CN 102098698 A CN102098698 A CN 102098698A CN 2010105715500 A CN2010105715500 A CN 2010105715500A CN 201010571550 A CN201010571550 A CN 201010571550A CN 102098698 A CN102098698 A CN 102098698A
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Abstract
The invention provides a method and system for testing error rate. Through a succinct and convenient test scheme, the data sent by a radio-frequency unit are received by a data acquisition module, and are transmitted to a personal computer; file transfer protocol (FTP) service is started after the personal computer responses to the information fed back by the data acquisition module to download the received data from a data acquisition card; and the downloaded data are processed and the error rate BER (bit error rate) is calculated.
Description
Technical field
The present invention relates to the intelligence test technical field, relate in particular to a kind of test method for bit error rate and system.
Background technology
The radio frequency testing of WCDMA base station is the key link in research and development and the production.Radio frequency testing is divided into transmitter test, receiver test, performance test in strict accordance with the 3GPP25.141 standard.Wherein receiver and performance testing index mainly contain the receptivity under reference sensitivity, dynamic range, obstruction, intermodulation, AWGN and the multipath channel, above index all be with the test error rate (BER) be means.
The base station comprises radio frequency unit (RRU) and Base Band Unit (BBU), and base station design has two kinds of different frameworks, and a kind of is that radio frequency and base band integrate big module of formation, and a kind of is the mode that radio frequency separates with base band.Wherein utilize optical fiber interface (CPRI) that radio frequency is zoomed out and separate the main stream approach that radio frequency and base band become present base station design.
Present radio frequency BER method of testing mainly contains following several:
(1) utilize the base station baseband hardware cell to calculate the error rate (BER)
The method adopts the WCDMA upward signal of VSA modulation standard, form with radiofrequency signal sends to the base station, utilize the radio demodulating module of RRU to be reduced to baseband signal, the baseband signal after the demodulation is delivered to baseband processing unit decoding back calculate the error rate.The advantage of the method is that computational speed is very fast.
(2) utilize the radio frequency Bit Error Rate Analyzer loop fuction test error rate (BER)
The base station testing instrument had both served as signal generator and had also played signal analyzer in the method, and tester sends the up radiofrequency signal of WCDMA to the base station, and the base station utilizes the Uu interface features that base band data is returned Bit Error Rate Analyzer, analyzed thereby carry out BER.The rf signal analysis instrument serves as the instrument that calculates the error rate in this method.The advantage of the method is that method of testing is fairly simple.
But, in existing two kinds of method of testings, there is following problem:
(1) utilizes the base station baseband hardware cell to calculate the method for BER, need the radio frequency unit and the Base Band Unit synchronous working of base station, in the process of research and development RRU, need the support of BBU.For new projects, general RRU and BBU research and develop simultaneously, therefore, are to utilize this method to detect the radio-frequency performance of receiver of RRU on ongoing most times in project.
(2) utilize the method for radio frequency Bit Error Rate Analyzer loop fuction test b ER, test under the situation that requires the RNC of core net to exist.Therefore, the method need be simulated RNC, and radio frequency error rate instrument price is more expensive, present stage utilance not high.
Therefore, design a kind of succinctly, method of testing and system are very necessary easily, are one of intelligence test technical field problems anxious to be solved at present.
Summary of the invention
The embodiment of the invention provides a kind of test method for bit error rate and system, by adopt a kind of succinctly, testing scheme easily, the data that data acquisition module sends by the received RF unit, and be sent to personal computer, start the FTP service behind the personal computer response data acquisition module feedback message, the data that receive are downloaded from data collecting card, data download is handled and carried out error rate BER and calculate.
The embodiment of the invention provides following technical scheme:
A kind of test method for bit error rate comprises step:
S1, transmitting control commands initialization radio frequency unit are with data collecting card and set up network and be connected.
S2, send data request command to data collecting card, data collecting card reception data request command responds and asks data behind the radio frequency unit receiving demodulation.
S3, receive data and be stored in the DDR memory, and the feedback information of transmitting and receiving data success is to PC.
S4, startup FTP service download to PC with the data that receive from data collecting card.
S5, data downloaded is carried out format conversion, synchronously and channel estimation process.
S6, carry out decoding processing and error rate calculation.
Preferably, in the above-mentioned steps one, it is to set up network by Ethernet to connect that network connects.
Preferably, in the above-mentioned steps two, data request command sends to the FPGA module in the data collecting card.
Preferably, before the above-mentioned steps three, further comprise:
Microprocessor in the data collecting card sets reading mode and receiving register.
Preferably, in the above-mentioned steps three, feedback information comprises the capacity and the memory address of data.
Preferably, in the above-mentioned steps two, data collecting card includes but not limited to microprocessor unit, power module, FPGA module and DDR memory.
A kind of error code testing system comprises personal computer, radio frequency unit, it is characterized in that, comprises data acquisition module, format converting module, synchronously and channel estimation module, decoding and computing module,
Above-mentioned personal computer is used for transmitting control commands initialization radio frequency unit and data acquisition module; Be used for starting the FTP service behind the response data acquisition module feedback message, the data that receive are downloaded from data collecting card;
Above-mentioned radio frequency unit is used to send data to data acquisition module;
Above-mentioned data acquisition module is used for the data that the received RF unit sends, and is sent to personal computer;
Above-mentioned format converting module is used for the data that download to personal computer are carried out format conversion;
Above-mentioned synchronous and channel estimation module is used for the data of format conversion are carried out synchronously and channel estimation process;
Above-mentioned decoding and computing module are used for the data of finishing synchronous and channel estimation process are decoded and computing.
Preferably, above-mentioned data acquisition module further comprises microprocessor unit, power module, FPGA module and DDR memory.
Preferably, above-mentioned test macro further comprises the vector signal source module, is used to generate up test vector.
Preferably, above-mentioned vector signal source module is that loop cycle sends test vector with 40ms.
Preferably, above-mentioned format converting module is calculated according to following formula,
Preferably, above-mentioned decoding and computing module are decoded data importing ADS module and error rate BER calculating.
Preferably, above-mentioned ADS module includes but not limited to CDMA2000, LTE-FDD, LTE-TDD module.
A kind of test method for bit error rate provided by the invention and system, by adopt a kind of succinctly, testing scheme easily, the data that data acquisition module sends by the received RF unit, and be sent to personal computer, start the FTP service behind the personal computer response data acquisition module feedback message, the data that receive are downloaded from data collecting card, data download is handled and carried out error rate BER and calculate.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below.Apparently, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the method for testing flow chart that the embodiment of the invention provides;
Fig. 2 is the test macro schematic diagram that the embodiment of the invention provides;
Fig. 3 is the structural representation of the test macro that provides of the embodiment of the invention;
Fig. 4 is the data collecting card internal structure schematic diagram that the embodiment of the invention provides.
Embodiment
A kind of test method for bit error rate and system that the embodiment of the invention provides, by adopt a kind of succinctly, testing scheme easily, the data that data acquisition module sends by the received RF unit, and be sent to personal computer, start the FTP service behind the personal computer response data acquisition module feedback message, the data that receive are downloaded from data collecting card, data download is handled and carried out error rate BER and calculate.
For making purpose of the present invention, technical scheme and advantage clearer, the embodiment that develops simultaneously with reference to the accompanying drawings, the present invention is described in more detail.
The embodiment of the invention provides a kind of test method for bit error rate, and as shown in Figure 1, concrete steps comprise:
S1, transmitting control commands initialization radio frequency unit are with data collecting card and set up network and be connected.
S2, send data request command to data collecting card, data collecting card reception data request command responds and asks data behind the radio frequency unit receiving demodulation.
S3, receive data and be stored in the DDR memory, and the feedback information of transmitting and receiving data success is to PC.
S4, startup FTP service download to PC with the data that receive from data collecting card.
S5, data downloaded is carried out format conversion, synchronously and channel estimation process.
S6, carry out decoding processing and error rate calculation.
Particularly, in step S1, PC is transmitting control commands initialization radio frequency unit RRU and data collecting card at first, and sets up the Socket connection by Ethernet, and radio frequency unit RRU initialization finishes and equipment is set up as shown in Figure 3.
Particularly, in step S2, PC sends the P3 port of the FPGA module of IQ data request command in the data collecting card, and the CPRI in the data collecting card obtains the IQ data behind the request radio frequency unit RRU receiving demodulation behind the corresponding command.
Particularly, in step S3, microprocessor in the data collecting card sets reading mode and relevant receiving register, with the storage that receives in the DDR memory, the feedback information of transmitting and receiving data success is to PC simultaneously, and this feedback information comprises the capacity and the memory address of IQ data simultaneously.
Particularly, in step S4, PC starts the FTP service after responding this feedback message, and the IQ data that receive are downloaded to from data collecting card in the background PC computer, finishes data acquisition.
Particularly, in step S5, the IQ data that download to PC are data of 9e2 form, need carry out format conversion according to following formula:
In addition, signal produces path delay and signal amplitude variation after receiving link, therefore need carry out synchronously and channel estimation process the IQ data after the conversion.Compare the synchronous and channel estimating under multipath and the awgn channel, because each module directly is to adopt the mode of cable to transmit data in the platform, noise is less.Under the precondition that satisfies the sensitivity requirement, adopt to receive data and known transmission data in the algorithm and do relevant carrying out synchronously, test result shows that a frame synchronization position that obtains under the situation of received signal intensity for-125.8dBm is quite obvious.Simultaneously the range value of received signal being done normalized comes analog channel to estimate.
Particularly, in step S6, finish synchronously and channel estimating after data need carry out decoding processing.The embodiment of the invention has adopted ADS software in the generation of the up test vector of WCDMA, therefore, will finish synchronously and the data importing ADS after the channel estimating, carries out error rate BER and calculates.
In the specific embodiment of the invention, adopt ADS software to produce a standard and survey up WCDMA test vector, the Toolkit instrument by Agilent downloads in the vector signal source, and this signal source can be E4438C or MXG N5182A.Because the WCDMA upstream data frame period is 10ms, take into account Back end data synchronously and the consideration of channel latency, the WCDMA signal length of Chan Shenging is 40ms herein, signal source is that loop cycle sends test vector with 40ms, the data vector that the vector signal source sends is sent to the rf inputs of RRU by the RF cable, arrive the CPRI port behind the duplexer of process RRU inside, low noise amplifier, frequency mixer, filter, amplifier, the analog to digital converter, hold to BBU by the CPRI reflector transmission CPRI data of RRU.
Particularly, the embodiment of the invention also provides a data collecting card, and purpose is that data are sent to PC after the CPRI port receives.Because the data collecting card function is comparatively simple, does an integrated circuit board separately and also can.In order to save cost, can adopt the useless plate of RRU to carry out obtaining data collecting card after the part exploitation, FPGA module and DDR memory that microprocessor unit, power module, the CPRI rate-matched of this data card reservation RRU used.The data collecting card internal module as shown in Figure 4, DDR controller and CPRI transceiver module are finished by FPGA.The DDR controller has 4 ports:
1. port one directly connects the transceiver module of CPRI, and port one can and store into the DDR memory from CPRI module reception data, also can obtain data from the DDR memory and send to the CPRI module;
2. port 2 is connected to the transmit port in the CPRI module, and the IQ data in the DDR memory send to the CPRI module by port 2;
3. port 3 is connected to the receiving port in the CPRI module, and the IQ data in the CPRI module receive the DDR memory by port 2;
4. port 4 connects microprocessor, and processor sends to PC to the IQ data in the DDR memory by Ethernet card.Same microprocessor also can download to the IQ data among the PC in the DDR memory in the data collecting card by Ethernet.
The embodiment of the invention provides a kind of error rate test system, as shown in Figure 2, comprises personal computer 1, data acquisition module 2, radio frequency unit 3, format converting module 4, synchronous and channel estimation module 5, decoding and computing module 6.
Personal computer 1: be used for transmitting control commands initialization radio frequency unit RRU and data acquisition module; Be used for starting the FTP service behind the response data acquisition module feedback message, the data that receive are downloaded from data collecting card.
Particularly, PC is transmitting control commands initialization radio frequency unit RRU and data acquisition module at first, and sets up the Socket connection by Ethernet, and radio frequency unit RRU initialization finishes and equipment is set up as shown in Figure 3.
Particularly, PC sends the P3 port of the FPGA module of IQ data request command in the data collecting card, and the CPRI in the data collecting card obtains the IQ data behind the request radio frequency unit RRU receiving demodulation behind the corresponding command.Microprocessor in the data collecting card sets reading mode and relevant receiving register, with the storage that receives in the DDR memory, the feedback information of transmitting and receiving data success is to PC simultaneously, and this feedback information comprises the capacity and the memory address of IQ data simultaneously.PC starts the FTP service after responding this feedback message, and the IQ data that receive are downloaded to from data collecting card in the background PC computer, finishes data acquisition.
Radio frequency unit 2: be used to send data to data acquisition module.
Particularly, in embodiments of the present invention, further comprise a vector signal source module, adopt ADS software to produce a standard and survey up WCDMA test vector, Toolkit instrument by Agilent downloads in the vector signal source, and this signal source can be E4438C or MXG N5182A.Because the WCDMA upstream data frame period is 10ms, take into account Back end data synchronously and the consideration of channel latency, the WCDMA signal length of Chan Shenging is 40ms herein, signal source is that loop cycle sends test vector with 40ms, the data vector that the vector signal source sends is sent to the rf inputs of RRU radio frequency unit by the RF cable, arrive the CPRI port behind the duplexer of process RRU radio frequency unit inside, low noise amplifier, frequency mixer, filter, amplifier, the analog to digital converter, by the CPRI reflector transmission CPRI data to data acquisition module of RRU radio frequency unit.
Data acquisition module 3: be used for the data that the received RF unit sends, and be sent to personal computer.
Particularly, in embodiments of the present invention, the data that data acquisition module is used for receiving from the CPRI port are sent to computer (PC).Because the data collecting card function is comparatively simple, does an integrated circuit board separately and also can.In order to save cost, can adopt the useless plate of RRU to carry out obtaining data collecting card after the part exploitation, FPGA module and DDR memory that microprocessor unit, power module, the CPRI rate-matched of this data card reservation RRU used.The data collecting card internal module as shown in Figure 4, DDR controller and CPRI transceiver module are finished by FPGA.The DDR controller has 4 ports:
1. port one directly connects the transceiver module of CPRI, and port one can and store into the DDR memory from CPRI module reception data, also can obtain data from the DDR memory and send to the CPRI module;
2. port 2 is connected to the transmit port in the CPRI module, and the IQ data in the DDR memory send to the CPRI module by port 2;
3. port 3 is connected to the receiving port in the CPRI module, and the IQ data in the CPRI module receive the DDR memory by port 2;
4. port 4 connects microprocessor, and processor sends to PC to the IQ data in the DDR memory by Ethernet card.Same microprocessor also can download to the IQ data among the PC in the DDR memory in the data collecting card by Ethernet.
Format converting module 4: be used for the data that download to personal computer are carried out format conversion.
Particularly, the IQ data that download to PC are data of 9e2 form, need carry out format conversion according to following formula:
Synchronously and channel estimation module 5: be used for the data of format conversion are carried out synchronous and channel estimation process.
Particularly, signal produces path delay and signal amplitude variation after receiving link, therefore need carry out synchronously and channel estimation process the IQ data after the conversion.Compare the synchronous and channel estimating under multipath and the awgn channel, because each module directly is to adopt the mode of cable to transmit data in the platform, noise is less.Under the precondition that satisfies the sensitivity requirement, adopt to receive data and known transmission data in the algorithm and do relevant carrying out synchronously, test result shows that a frame synchronization position that obtains under the situation of received signal intensity for-125.8dBm is quite obvious.Simultaneously the range value of received signal being done normalized comes analog channel to estimate.
Decoding and computing module 6: be used for the data of finishing synchronous and channel estimation process are decoded and computing.
Particularly, finish synchronously and channel estimating after data need carry out decoding processing.The embodiment of the invention has adopted the ADS module software in the generation of the up test vector of WCDMA, therefore, will finish synchronously and the data importing ADS after the channel estimating, carries out error rate BER and calculates.
One of ordinary skill in the art will appreciate that and realize that all or part of step that the foregoing description method is carried is to instruct relevant hardware to finish by program, described program can be stored in a kind of computer-readable recording medium, this program comprises one of step or its combination of method embodiment when carrying out.
In addition, each functional unit in each embodiment of the present invention can be integrated in the processing module, also can be that the independent physics in each unit exists, and also can be integrated in the module two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, also can adopt the form of software function module to realize.If described integrated module realizes with the form of software function module and during as independently production marketing or use, also can be stored in the computer read/write memory medium.
In sum, this paper provides the embodiment of the invention that a kind of test method for bit error rate and system are provided, by adopt a kind of succinctly, testing scheme easily, the data that data acquisition module sends by the received RF unit, and be sent to personal computer, start the FTP service behind the personal computer response data acquisition module feedback message, the data that receive are downloaded from data collecting card, data download is handled and carried out error rate BER and calculate.
More than a kind of test method for bit error rate provided by the present invention and system are described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand the solution of the present invention; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (13)
1. a test method for bit error rate is characterized in that, described method of testing comprises step:
S1, transmitting control commands initialization radio frequency unit are with data collecting card and set up network and be connected.
S2, send data request command to data collecting card, data collecting card reception data request command responds and asks data behind the radio frequency unit receiving demodulation.
S3, receive data and be stored in the DDR memory, and the feedback information of transmitting and receiving data success is to PC.
S4, startup FTP service download to PC with the data that receive from data collecting card.
S5, data downloaded is carried out format conversion, synchronously and channel estimation process.
S6, carry out decoding processing and error rate calculation.
2. method of testing according to claim 1 is characterized in that, in described step 1, it is to set up network by Ethernet to connect that network connects.
3. method of testing according to claim 1 is characterized in that, in described step 2, data request command sends to the FPGA module in the data collecting card.
4. method of testing according to claim 1 is characterized in that, before described step 3, further comprises:
Microprocessor in the data collecting card sets reading mode and receiving register.
5. method of testing according to claim 1 is characterized in that, in described step 3, feedback information comprises the capacity and the memory address of data.
6. method of testing according to claim 1 is characterized in that, in described step 2, data collecting card includes but not limited to microprocessor unit, power module, FPGA module and DDR memory.
7. an error code testing system comprises personal computer, radio frequency unit, it is characterized in that, comprises data acquisition module, format converting module, synchronous and channel estimation module, decoding and computing module,
Described personal computer is used for transmitting control commands initialization radio frequency unit and data acquisition module; Be used for starting the FTP service behind the response data acquisition module feedback message, the data that receive are downloaded from data collecting card;
Described radio frequency unit is used to send data to data acquisition module;
Described data acquisition module is used for the data that the received RF unit sends, and is sent to personal computer;
Described format converting module is used for the data that download to personal computer are carried out format conversion;
Described synchronous and channel estimation module is used for the data of format conversion are carried out synchronously and channel estimation process;
Described decoding and computing module are used for the data of finishing synchronous and channel estimation process are decoded and computing.
8. test macro according to claim 7 is characterized in that, described data acquisition module further comprises microprocessor unit, power module, FPGA module and DDR memory.
9. test macro according to claim 7 is characterized in that described test macro further comprises the vector signal source module, is used to generate up test vector.
10. test macro according to claim 9 is characterized in that, described vector signal source module is that loop cycle sends test vector with 40ms.
11. test macro according to claim 7 is characterized in that, described format converting module is calculated according to following formula,
12. test macro according to claim 7 is characterized in that, described decoding and computing module are decoded data importing ADS module and error rate BER calculating.
13. test macro according to claim 12 is characterized in that, described ADS module includes but not limited to CDMA2000, LTE-FDD, LTE-TDD module.
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Application publication date: 20110615 |