CN116209002A

CN116209002A - Test data interaction method, test data interaction device and electronic equipment

Info

Publication number: CN116209002A
Application number: CN202310181890.XA
Authority: CN
Inventors: 岳青
Original assignee: Sichuan Hengwan Technology Co Ltd
Current assignee: Sichuan Hengwan Technology Co Ltd
Priority date: 2023-02-28
Filing date: 2023-02-28
Publication date: 2023-06-02

Abstract

The embodiment of the invention discloses a test data interaction method, a test data interaction device and electronic equipment. After a first control signal sent by an application side is received by a processing side, determining a target test data acquisition channel in a plurality of candidate test data acquisition channels arranged in a communication link according to the first control signal, then acquiring first target test data from a corresponding test data acquisition node in the communication link through the target test data acquisition channel, and further sending the first target test data to the application side in a burst transmission mode. Therefore, real-time, timing and fixed-point test data interaction can be realized, so that various test data interaction requirements are met, and test data interaction efficiency and universality are improved.

Description

Test data interaction method, test data interaction device and electronic equipment

Technical Field

The present invention relates to the field of data interaction technologies, and in particular, to a test data interaction method, a test data interaction device, and an electronic device.

Background

With the rapid development of mobile communication technology, the transmission rate of communication data is continuously increased from 1G (1 th generat ion mobi l enetworks, first generation mobile communication network) to 5G (5 th generat ion mobi l enetworks, fifth generation mobile communication network), and the transmission level of communication data is increased from kbps to Gbps. This also places higher demands on the communication data transmission, so the 5G radio access network evolves from a BBU (Baseband Unit) -RRU (Remote Rad io Unit ) two-stage structure of 4G/LTE (Long Term Evo l ut ion ) to a three-stage structure of CU (Centra l i zed Unit ), DU (Di str ibuted Unit, distributed Unit), RU (Rad io Unit ). In the development process of RU functions, various complex tests and verification are required, and data acquisition, data injection, data excitation, data monitoring, data analysis and the like are performed in the test and verification process, so that RU function software is debugged according to test data, and therefore, higher requirements are put on test data interaction efficiency, universality and the like in the test and verification process.

In the prior art, test data interaction can be performed in a simulation mode of a tester. Test data interaction may also be performed through the JTAG (Joi nt Test Act ion Group), joint test action group, debug mode (i.e., JTAG debug). Specifically, a TAP (Test Access Port) is defined in each node to be tested in the communication link, and each node to be tested is connected in series through a JTAG interface to obtain a JTAG chain, so that Test data are collected and injected to each node to be tested through the JTAG chain.

On the one hand, in the prior art, a simulation mode of a tester or a debugging mode of JTAG cannot comprehensively cover the scenes of RU function test and verification; on the other hand, if a large amount of test data needs to be comprehensively processed and analyzed, in the prior art, a TAP is defined in each node to be tested, so that a large amount of resources are occupied, and the resource waste and the limitation are large.

Disclosure of Invention

Therefore, an object of the embodiments of the present invention is to provide a test data interaction method, a test data interaction device, and an electronic device, which can implement real-time, timing and fixed-point test data interaction, so as to meet various test data interaction requirements, and improve test data interaction efficiency and universality.

In a first aspect, an embodiment of the present invention provides a test data interaction method, where the method includes:

receiving a first control signal sent by an application side;

determining a target test data acquisition channel corresponding to the first control signal;

acquiring first target test data from a corresponding test data acquisition node in a communication link through the target test data acquisition channel; and

and sending the first target test data to the application side in a burst transmission mode.

In some embodiments, the method further comprises:

setting a plurality of candidate test data acquisition channels according to a plurality of test data acquisition nodes in the communication link;

the determining the target test data acquisition channel corresponding to the first control signal includes:

and determining the target test data acquisition channel from a plurality of candidate test data acquisition channels according to the first control signal.

In some embodiments, the method further comprises:

determining a current test data acquisition channel; and

and switching the current test data acquisition channel into the target test data acquisition channel.

In some embodiments, the sending the first target test data to the application side by means of burst transmission includes:

Determining one or more first burst data segments according to the first target test data; and

and sending the one or more first burst data segments to the application side.

In some embodiments, the sending the one or more first burst data segments to the application side includes:

and transmitting the one or more first burst data segments to the application side in a direct storage access mode.

In some embodiments, the method further comprises:

receiving a second control signal sent by an application side;

determining a target test data injection channel corresponding to the second control signal; and

and in response to receiving second target test data sent by an application side, sending the second target test data to a test data injection node corresponding to the communication link of the target test data injection channel in a burst transmission mode.

In some embodiments, the method further comprises:

setting a plurality of candidate test data injection channels according to a plurality of test data injection nodes in the communication link;

the determining the target test data injection channel corresponding to the second control signal includes:

And determining the target test data injection channel from a plurality of candidate test data injection channels according to the second control signal.

In some embodiments, the sending the second target test data to the test data injection node corresponding to the communication link by the target test data injection channel through burst transmission includes:

determining one or more second burst data segments according to the second target test data;

and sending the one or more second burst data segments to a test data injection node corresponding to the target test data injection channel in the communication link.

In a second aspect, an embodiment of the present invention provides a communication apparatus, the apparatus including:

the first control signal receiving unit is used for receiving a first control signal sent by the application side;

the target test data acquisition channel determining unit is used for determining a target test data acquisition channel corresponding to the first control signal;

the first target test data acquisition unit is used for acquiring first target test data from the corresponding test data acquisition nodes in the communication link through the target test data acquisition channel;

and the first target test data transmitting unit is used for transmitting the first target test data to the application side in a burst transmission mode.

In a third aspect, an embodiment of the present invention provides an electronic device, including:

a memory for storing one or more computer program instructions;

a processor, the one or more computer program instructions being executed by the processor to implement the method as described in the first aspect.

After a first control signal sent by an application side is received by a processing side, determining a target test data acquisition channel in a plurality of candidate test data acquisition channels arranged in a communication link according to the first control signal, then acquiring first target test data from a corresponding test data acquisition node in the communication link through the target test data acquisition channel, and further sending the first target test data to the application side in a burst transmission mode. Therefore, real-time, timing and fixed-point test data interaction can be realized, so that various test data interaction requirements are met, and test data interaction efficiency and universality are improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a flow chart of a test data interaction method of an embodiment of the present invention;

FIG. 2 is a schematic diagram of an electronic device in an embodiment of the invention;

FIG. 3 is a flow chart of a test data interaction method of an embodiment of the present invention;

FIG. 4 is a schematic diagram of a communication link in an embodiment of the invention;

FIG. 5 is a schematic diagram of an FPGA chip architecture in an embodiment of the invention;

FIG. 6 is a flowchart of transmitting first target test data to an application side by burst transmission in an embodiment of the present invention;

FIG. 7 is a flow chart of a test data interaction method of an embodiment of the present invention;

FIG. 8 is a schematic diagram of an FPGA chip architecture in an embodiment of the invention;

FIG. 9 is a flow chart of a method for transmitting second target test data to a test data injection node corresponding to a communication link of a target test data injection channel by burst transmission in an embodiment of the present invention;

FIG. 10 is a flow chart of a test data interaction device according to an embodiment of the present invention.

Detailed Description

The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.

Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.

Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like in the description are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

In the description of the present invention, it should be understood that the terms "first," "second," and the like are merely configured for descriptive purposes and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the following description, test data interaction during development of functions of a Low PHY (physical i cal, physical layer) +def unit (Di gita l Front End ) in a Macro base station (MS) radio frequency end RU under the 5G standard is taken as an example. The Low PHY belongs to a baseband processing part of the RU of the radio frequency end, and is used for coding communication data, physical layer HARQ (Hybr i d Automat i c Repeat Request ) processing, modulation, multi-antenna processing, mapping of signals on corresponding time-frequency resources, and the like. DEF is used for dc signal cancellation, I Q imbalance cancellation, out-of-band noise filtering, frame detection, etc. Further, the macro base station may employ a RAN radio access network architecture (Rad i o Access Network ), and the macro base station may include a DU, a CU, and a radio frequency side RU. The DUs, CUs and RUs are used to implement part of the functionality of the macro base station, e.g. a CU may implement the functionality of radio resource control (Rad i oResource Contro l, RRC), packet data convergence layer protocol (Packet Data Convergence Protoco l, PDCP) layer, etc. The DUs may implement radio link control (rad i o l i nk contro l, RLC), medium access control (med i a access contro l, MAC), etc. The radio frequency end RU is used for transmitting and receiving communication signals and other functions. It should be understood that the test data interaction method of the embodiment of the invention can also be applied to various scenes and network devices needing data interaction. The scenario of data interaction is, for example, data interaction in the process of developing DU and CU functions. Network devices such as radio network controllers (Rad i o Network Contro l l er, RNC), home base stations (e.g., home Evo l ved NodeB, home NodeB, etc.), micro base stations (M i cro Site, MS), pico base stations (Pi co Site, PS), etc.

FIG. 1 is a flow chart of a test data interaction method according to an embodiment of the present invention. As shown in fig. 1, the test data interaction process of the present embodiment includes the following steps:

step S100, a first control signal sent by an application side is received, and a target test data acquisition channel corresponding to the first control signal is determined.

In this embodiment, a plurality of corresponding candidate test data acquisition channels may be preset according to the test data acquisition node in the communication link, and after receiving the first control signal sent by the application side, the processing side may determine the target test data acquisition channel from the plurality of candidate test data acquisition channels according to the first control signal. The macro base station can be configured with a controller, and the controller is an electronic device with functions of data transmission, data processing, information storage and the like, so that test data interaction is realized. In particular, reference may be made to fig. 2.

Fig. 2 is a schematic diagram of an electronic device in an embodiment of the invention. The electronic device shown in fig. 2 may be a general-purpose data processing chip or apparatus, which may be implemented by an MCU (Mi crocontro l l er Un it, micro control unit), a PLC (Programmab l e Logi C Contro l l er ), an FPGA chip (Fi e l d-Programmab l e Gate Array, field programmable gate array), a single chip microcomputer, a DSP (Di gita l Si gna l Processor ) or an AS ic (App l I cat I on Spec I f I C I ntegrated Ci rcu it, application specific integrated circuit), or the like. The data processing chip or device comprises a general purpose computer hardware structure including at least a processor 421 and a memory 422. The processor 421 and the memory 422 are connected by a bus 423. The memory 422 is adapted to store instructions or programs executable by the processor 421. The processor 421 may be a separate microprocessor or a collection of one or more microprocessors. Thus, the processor 421 performs the process flow of the embodiment of the present invention described above to realize the processing of data and the control of other devices by executing the instructions stored in the memory 422. Bus 423 connects the above-described components together, while connecting the above-described components to display controller 424 and to display devices and input/output (I/O) devices 425. Input/output (I/O) devices 425 may be mice, keyboards, modems, network interfaces, touch input devices, somatosensory input devices, printers, and other devices which are well known in the art. Typically, input/output devices 425 are connected to the system through input/output (I/O) controllers 426.

It will be appreciated by those skilled in the art that embodiments of the invention may be provided as a method, an electronic device, or a computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may employ a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations of methods, electronic devices, and computer program products according to embodiments of the application. It will be understood that each of the flows in the flowchart may be implemented by computer program instructions.

These computer program instructions may be stored in a computer-readable memory that can direct a computer or other programmable data processing chip or apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows.

These computer program instructions may also be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing chip or apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing chip or apparatus, create means for implementing the functions specified in the flowchart flow or flows.

In this embodiment, the controller includes a processing side and an application side. The processing side and the application side are used for realizing different functions, and may be processing units arranged on different hardware computing platforms, or may be a plurality of software programs or interfaces for providing services arranged on a unified hardware platform or a cloud platform. In the following description, a controller, that is, an FPGA chip, and a processing side and an application side are described as an example of software programs written according to the test data interaction process described below, which are arranged on a unified hardware platform (that is, an FPGA chip). The FPGA chip may be a multi-core heterogeneous SOC (System on chip) based on Xi l nx, such as SOC model Zynq.

Step 200, acquiring first target test data from a corresponding test data acquisition node in a communication link through the target test data acquisition channel.

In this embodiment, after determining the corresponding target test data acquisition channel according to the first control signal, the processing side of the FPGA chip may acquire the first target test data from the corresponding test data acquisition node in the communication link through the target test data acquisition channel. That is, a first target test data stream is collected from a test data collection node through a target test data collection channel.

Step 300, sending the first target test data to the application side in a burst transmission mode.

In this embodiment, the Burst transmission mode, i.e. Burst transmission, belongs to a mode of continuously performing data transmission between adjacent memories. Because Burst transmission has universality, and only one address needs to be sent in the test data transmission process, each test data does not need to be sent correspondingly, and therefore the test data interaction efficiency is improved. That is, the processing side of the FPGA chip transmits the first target test data collected by the test data collection node to the application side through Burst. The storage may be a register, a cache, a memory, etc. Therefore, test data interaction can be realized, and test data interaction efficiency and universality are improved.

FIG. 3 is a flow chart of a test data interaction method according to an embodiment of the present invention. As shown in fig. 3, the test data interaction process of the present embodiment includes the following steps:

step S110, setting a plurality of candidate test data acquisition channels according to a plurality of test data acquisition nodes in the communication link.

In this embodiment, because the simulation or JTAG debugging mode of the tester in the prior art cannot fully cover the RU function test and verification scene, aiming at the situation, the embodiment of the invention can set a plurality of candidate test data acquisition channels corresponding to a plurality of test data acquisition nodes in the communication link in advance, further select a target test data acquisition channel from the plurality of candidate test data acquisition channels according to the test requirement, and then perform test data acquisition. Therefore, real-time, timing and fixed-point test data interaction can be realized, so that various test data interaction requirements are met, and the method is not limited by resources in an FPGA chip.

In this embodiment, the communication link is provided in the FPGA chip. That is, the communication link may be a circuit preset in the FPGA chip by a tester according to the need. In particular, a schematic diagram of a communication link may be referred to in fig. 4.

Fig. 4 is a schematic diagram of a communication link in an embodiment of the invention. As shown in fig. 4, the communication link of the present embodiment includes a data transmission link a, a data reception link b, and an eCPRI (Enhanced Common Pub l i c Rad i o I nterface, enhanced common radio interface) interface c. Among other things, the eCPRI interface c is an evolved form of the CPRI protocol (Common Pub l i c Rad i o I nterface, public radio interface) that defines specifications for connection between nodes over a forwarding network (Fronthua lTransport Network, FTN). Such as the rec node and eRE node. Further, the eCPRI interface c supports 5G communication, and can realize efficient and flexible radio data transmission based on a front-end transmission network (such as i p or Ethernet) of the data packet.

In the present embodiment, the data transmission link a includes an I FFT (I nverse Fast Four I er Transform ) a1, DUC (Di gita l Up Converter, digital up-conversion) a2, CFR (Crest Factor Reduct I on ) a3, DPD (Di gita l Pre-Di gart I on, digital predistortion) a4, VCA (Vo l tage Contro l l ed ga I nAmp l I f I er ) a5, RF Soc TX (Rad I o Frequency Soc Transport, radio frequency transmission chip) a6, and RF Soc TOR (Rad I o Frequency Soc TOR, radio frequency router) a7. Wherein, I FFTa1 is used to convert the communication signal from a frequency domain signal to a time domain signal. Specifically, the frequency domain communication data may be subjected to conjugate complex processing (i.e., the imaginary part is inverted), and then the communication data after the conjugate complex processing is subjected to FFT to obtain the time domain signal. The DUCa2 is configured to convert a digital signal into an analog signal in the data transmission link a, and then mix the analog signal to obtain a desired rf center frequency higher than that of the original signal, and then amplify the mixed analog signal (i.e., amplify the mixed analog signal to an appropriate power level), and then limit the bandwidth of the amplified analog signal for transmission via the antenna. CRFa3 is used for peak clipping, that is, to cancel a communication signal above the peak clipping threshold value to achieve dynamic peak clipping, so as to avoid spectrum overflow caused by peak-to-average ratio and improve channel quality. The DPDa4 is used for performing predistortion processing on the communication signal at the baseband, and then performing power amplification on the communication signal after the predistortion processing to ensure the linear output of the signal. VCAa5 is used to regulate and control communication signals. RF Soc TXa6 is used to transmit communication signals. The RF Soc TORa7 is used for a relay node in the transmission process of communication signals.

In this embodiment, the data receiving link b includes FFT (Fast Four i er Transform ) b1, DDC (Di g ita l Down Converters, digital down conversion) b2, and RF Soc RX (Rad i o Frequency Soc Rece i ve, radio frequency receiving chip) b3. Wherein FFTb1 is used to convert a communication signal from a time domain signal to a frequency domain signal. DDCb2 is used to spectrally down-convert an intermediate frequency (I F) digital signal to a baseband signal by a digital mixing process, and then post-filter to recover the original signal. In digital down-conversion, the down-conversion may be achieved by digital signal processing techniques including digital filtering, quadrature transformation, sampling, decimation, and the like. The RF Soc RXb3 is used to receive communication signals.

In this embodiment, in order to enable real-time, timing and fixed-point test data interaction to meet various test data interaction requirements, in this embodiment, in a process of developing a function of a Low phy+def unit of a radio frequency end RU, a probe is adopted to embed the Low phy+def unit of the radio frequency end RU to implement test data interaction. Wherein the probe comprises a test data acquisition probe TAP (Test Access Poi nt ) corresponding to the candidate test data acquisition channel (e.g. 9b1 in data receiving link b) and a test data injection probe I NP (I njected Po I nt, injection point) corresponding to the candidate test data injection channel (e.g. 5b1 in data receiving link b). Specifically, a plurality of test data acquisition nodes (for example, the region 9b2 in the data receiving link b) and test data injection nodes (for example, the region 5b2 in the data receiving link b) are set in the communication link in advance, and then a plurality of test data acquisition probes TAP and a plurality of test data injection probes iinp are correspondingly set in a data bypass mode according to the plurality of test data acquisition nodes and the test data injection nodes. Therefore, the test data can be acquired through the candidate test data acquisition channel corresponding to the test data acquisition probe TAP, and the test data can be injected through the candidate test data injection channel corresponding to the test data injection probe I NP. Therefore, a plurality of candidate test data acquisition channels and a plurality of candidate test data injection channels can be correspondingly arranged according to a plurality of test data acquisition nodes in the communication link.

In this embodiment, the plurality of test data acquisition probes TAP includes TAP1, TAP2, TAP3, TAP4, TAP5, TAP6, TAP7, TAP8, and TAP9, and the plurality of test data injection probes I NP includes I NP0, I NP1, I NP2, I NP3, I NP4, and I NP5. Specifically, for the data transmission link a, a test data acquisition probe TAP1 and a test data injection probe I NP0 may be provided between the eCPRI interface c and I FFTa 1. A test data acquisition probe TAP2 and a test data injection probe I NP1 are arranged between I FFTa1 and DUCa 2. A test data acquisition probe TAP3 and a test data injection probe I NP2 are arranged between the DUCa2 and CRFa 3. A test data acquisition probe TAP4 is arranged between CRFa3 and DPDa 4. A test data acquisition probe TAP5 and a test data injection probe I NP3 are arranged between VCAa5 and RF Soc TXa 6. Test data acquisition probe TAP6 was set at DPDa4 and RF Soc TORa 7. For the data receiving link b, a test data acquisition probe TAP7 may be arranged between the eCPRI interface c and FFTb 1. A test data acquisition probe TAP8 and a test data injection probe I NP4 are provided between FFTb1 and DDCb 2. A test data acquisition probe TAP9 and a test data injection probe I NP5 are provided between DDCb2 and RF Soc RXb 3. Therefore, real-time, timing and fixed-point test data interaction can be realized.

In this embodiment, a plurality of test data acquisition probes TAP including TAP1, TAP2, TAP3, TAP4, TAP5, TAP6, TAP7, TAP8 and TAP9, and a plurality of test data injection probes I NP including I NP0, I NP1, I NP2, I NP3, I NP4 and I NP5 are exemplified. It should be understood that the number of the set test data acquisition probes TAP and the number of the set test data injection probes I NP are not limited in the embodiment of the present invention, and a tester may set different numbers of the set test data acquisition probes TAP and the set test data injection probes I NP according to the test requirements. Correspondingly, a tester can set different numbers of test data acquisition nodes and test data injection nodes according to test requirements.

Step S120, a first control signal sent by an application side is received, and a target test data acquisition channel corresponding to the first control signal is determined.

In this embodiment, the first control signal may be a test data acquisition instruction. Specifically, the processing side receives a test data acquisition instruction sent by the application side, and determines a corresponding target test data acquisition channel according to the test data acquisition instruction. Further, a schematic diagram of the FPGA chip architecture in this embodiment may refer to fig. 5.

FIG. 5 is a schematic diagram of an FPGA chip architecture in an embodiment of the invention. As shown in fig. 5, the FPGA chip of the present embodiment includes a processing side 1, an application side 2, and a memory 3. Wherein the processing side 1 comprises a first channel controller 11 and a first test data transmitter 12. The first data transmitter 12 includes a first buffer 121, a first burst transfer controller 122, and an FB DMA (Free Burst Di rect Memory Access, direct memory access) interface 123.

In this embodiment, the processing side 1 may be PL (Progarmmab l e Logi c, programmable logic), which is a part related to the FPGA. The application side 2 may be part of a PS (Process i ng System ), i.e. an SOC of an ARM (Advanced RI SC Mach i nes, microprocessor) independent of the FPGA.

Alternatively, the application side 2 may be an APP (APP i cat i on, application program), such as a browser or various other types of application programs, etc.

In this embodiment, because the debug mode of the tester simulation or JTAG in the prior art cannot fully cover the scenario of RU functional test and verification, for this case, in the embodiment of the present invention, a plurality of test data acquisition nodes and test data injection nodes are set in advance in the PFGA chip communication link, and then, according to the plurality of test data acquisition nodes and test data injection nodes, a plurality of test data acquisition probes TAP and a plurality of test data injection probes I NP are correspondingly set in a data bypass mode. The tester can control the processing side 1 (namely PL) through the application side 2 (namely PS) to select the corresponding test data acquisition channel and the corresponding test data injection channel according to the set test data acquisition probe TAP and the set test data injection probe I NP so as to realize test data interaction in the communication link. That is, PL is used as a part related to the FPGA, and test data interaction is performed by the PL in a circuit of the FPGA chip by means of probes. Therefore, real-time, timing and fixed-point test data interaction can be realized, and the method is not limited by resources in an FPGA chip.

In this embodiment, the test data interaction mode including test data acquisition and test data injection will be described as an example. It should be understood that the embodiment of the present invention does not limit the form of test data interaction, and the form of test data interaction may also include test data excitation, test data monitoring, test data analysis, and the like.

Alternatively, the communication between the processing side 1 and the application side 2 (i.e., PL and PS) may be implemented through bus interfaces such as AX I4 (Advanced eXtens I b l e I nterface ), AXI-Lite, AXI-Stream, and the like. AXI4 is used for high-performance address mapping communication, belongs to an interface facing address mapping, and allows maximum 256 rounds of burst data transmission. The AXI4-Lite is a lightweight address mapping single transmission interface, has the characteristic of occupying less logic units, and is suitable for address mapping communication buses with smaller throughput. AX I-Stream is used for high-speed Stream data transmission, which allows unlimited burst data transmission sizes.

In this embodiment, the first channel controller 11 may be a MUX control l, which belongs to a custom test data acquisition channel control logic, and is used for channel switching. The first channel controller 11 may be disposed outside the first test data transmitter 12.

Alternatively, the first channel controller 11 may also be arranged inside the first test data transmitter 12. The first channel controller 11 may also be disposed in a Low phy+def unit of the radio frequency end RU, that is, the first channel controller 11 is disposed in developed functional software of the radio frequency end RU, so that channel switching may be directly performed to obtain required test data from the communication link. Therefore, universality of test data interaction is improved.

In this embodiment, the first test data transmitter 12 may be an RTS (Request To Send) for the first target test data transmission.

In this embodiment, the first buffer 121 may be FB DMA wfi FO (Free Burst Di rect Memory Access wr ite F I rst I nput Fi rst Output, direct access memory) for buffering collected test data.

In this embodiment, the first burst transmission controller 122 may be a wBurst controller, which belongs to the custom burst data control logic.

In this embodiment, the FB DMA interface 123 is used for test data transmission by way of direct memory access.

Alternatively, the memory 3 may be a DDR memory (Doub l e Data Rate, double rate synchronous dynamic random access memory).

In the following description, MUX control i.e., first channel controller 11, rts i.e., first data transmitter 12,FB DMA wF I FO, and first buffer 121,wBurst Contro l, i.e., first burst transmission controller 122.

In this embodiment, the tester may send the first control signal to the MUX control l in the processing side 1 through the application side 2, and then the MUX control l may determine the target test data acquisition channel from the plurality of test data acquisition channels corresponding to the plurality of test data acquisition probes TAP according to the first control signal.

In an alternative embodiment, the first control signal may include a target test data acquisition channel number and/or a test data acquisition probe TAP identifier, and the MUX control l may determine a target test data acquisition channel from a plurality of candidate test data acquisition channels corresponding to the plurality of test data acquisition probe TAPs according to the first control signal.

In another alternative embodiment, the first control signal may also comprise a plurality of target test data acquisition channel numbers and/or a plurality of test data acquisition probe TAP identifications. The MUX Contro l may determine a plurality of target test data acquisition channels from a plurality of candidate test data acquisition channels corresponding to the plurality of test data acquisition probes TAPs according to the first control signal.

Step S130, determining a current test data acquisition channel.

In this embodiment, the MUX control determines one or more current test data acquisition channels after receiving the first control signal sent by the application side 1.

In the present embodiment, step S120 and step S130 may be performed in the current order. Step S120 and step S130 may also be performed simultaneously. Step S130 may also be performed before step S120.

And step 140, switching the current test data acquisition channel into a target test data acquisition channel.

In an alternative embodiment, if the current test data acquisition channel is different from the target test data acquisition channel, MUX Contro l switches the current test data acquisition channel to the target test data acquisition channel. For example, if the current test data acquisition channel is the test data acquisition channel corresponding to the test data acquisition probe TAP0 and the target test data acquisition channel is the test data acquisition channel corresponding to the test data acquisition probe TAP1, the MUX control l switches the test data acquisition channel corresponding to the test data acquisition probe TAP0 to the test data acquisition channel corresponding to the test data acquisition probe TAP 1.

In another alternative embodiment, if the current test data acquisition channel is the same as the target test data acquisition channel, MUX Contro l does not need to perform a data acquisition channel switch.

Step S150, acquiring first target test data from a corresponding test data acquisition node in the communication link through a target test data acquisition channel.

Optionally, the first control signal may further include a length of the first target test data. The tester can set the length of the first target test data to be collected through the application side 2, and the MUX control l can obtain the first target test data with the corresponding length according to the first control signal. For example, test data of one radio frame, i.e., 10ms of test data, can be acquired in units of time.

In an alternative embodiment, the MUX conten acquires the target test data at a corresponding one of the test data acquisition nodes in the communication link according to the test data acquisition probe TAP corresponding to the one of the target test data acquisition channels.

In another alternative embodiment, the MUX conten acquires a plurality of first target test data at a corresponding plurality of test data acquisition nodes in the communication link according to a plurality of test data acquisition probes TAP corresponding to the plurality of target test data acquisition channels.

In this embodiment, MUX Contro l bypasses the first target test data to FB DMA wF I FO in RTS after acquiring the first target test data.

Step S160, the first target test data is sent to the application side in a burst transmission mode.

In the present embodiment, step S160 includes steps S161 to S163. In particular, reference may be made to fig. 6.

Fig. 6 is a flowchart of sending first target test data to an application side by means of burst transmission in an embodiment of the present invention. As shown in fig. 6, the process of sending the first target test data to the application side by means of burst transmission in this embodiment includes the following steps:

step S161, determining one or more first burst data segments according to the first target test data.

In this embodiment, the tester may send a first communication signal to the wBurst Contro l through the processing side 1, where the first communication signal includes a first target test data length to indicate the wBurst Contro l first target test data length. And then the wrset Contro l calculates the number of times of Burst transmission according to the length of the first target test data to be transmitted. If the wBurst Contro l detects that the FB DMA wF I FO is not null, i.e., that the FB DMA wF I FO is present with the first targeted test data, the wBurst Contro l sends a request signal to the FB DMA interface 123. The request signal may be an FB DMA WREQ pulse signal, which is used to request a Burst transfer from the FB DMA interface 123. Further, FB DMA WREADY is set high after FB DMA interface 123 receives the request signal to indicate that wBurst contenro is currently idle and complete the handshake. The wrset Contro l then reads the first targeted test data from the FB DMA wrF I FO and determines one or more first burst data segments based on the first targeted test data. That is, the wBurst Contro l converts the first targeted test data stored in the FB DMA wF I FO into one or more first burst data segments. Wherein the burst data segment characterizes the bit width, i.e. the data length, of each transmission data, e.g. 1 byte, 2 bytes, 4 bytes and 8 bytes, each byte having a value in the range 0-0xff (16 in system). The data length can be set by a tester or can be automatically set by the wBurst controller.

Alternatively, the burst data segment may include a plurality of data of a set bit width.

Optionally, FB DMA WREADY may be set low to indicate that wBurst control is currently busy by FB DMA interface 123 receiving a request signal sent by wBurst control. The wrurst Contro l may send a request signal to the wrurst Contro l by means of a poll so that the handshake has finally been completed for the first target test data transfer.

Optionally, if the request signal includes a Burst transfer number, the FB DMA interface 123 may determine the Burst transfer number (i.e., wBURST I ME) according to the request signal.

Step S163, one or more first burst data segments are sent to the application side.

In this embodiment, the FB DMA interface 123 may send one or more first burst data segments stored in the FB DMA wF FO through the AXI bus interface to the application side through the wBurst Contro l by means of direct memory access.

In this embodiment, after the FB DMA interface 123 completes one BURST transmission (i.e. the FB DMA interface 123 sends all the first BURST data segments of the current BURST transmission to the application side 2), the FB DMA wrady is set to a low level, and wramt I ME is increased by 1, waiting for the wramContro l to send a request signal next time, and BURST transmission is performed again.

Optionally, after receiving the one or more first burst data segments sent by the FB DMA interface 123, the application side 2 writes the one or more first burst data segments into the memory 3. Further, the application side 2 converts one or more first burst data segments stored in the memory 3 into test data in a predetermined format, and stores the test data in the predetermined format under a preset path of the application side 2, and waits for a tester to subsequently call and collect the test data.

Optionally, the wpurst controller may perform slice framing according to the first target test data stored in the FB DMA wF FO after the FB DMA interface 123 completes the handshake. Then, the FB DMA interface 123 sends the first target test data after framing the slice stored in the FB DMA wF I FO to the application side 2 through the wpurst Contro l in a direct memory access manner, the application side 2 writes the first target test data after framing the slice into the memory 3, further changes the first target test data after framing the slice stored in the memory 3 into test data with a predetermined format, and stores the test data with the predetermined format in a preset path of the application side 2, waiting for a tester to subsequently call, and completing the test data acquisition.

Alternatively, the test data in the predetermined format may be txt text format data.

FIG. 7 is a flow chart of a test data interaction method according to an embodiment of the present invention. As shown in fig. 7, the process of the test data interaction method of the present embodiment includes the following steps:

step S210, setting a plurality of candidate test data injection channels according to a plurality of test data injection nodes in the communication link.

In this embodiment, because the simulation or JTAG debugging mode of the tester in the prior art cannot fully cover the RU function test and verification scenario, in this case, the embodiment of the present invention can set a plurality of candidate test data injection channels corresponding to a plurality of test data injection nodes in the communication link in advance, and then the processing side selects a target test data injection channel from the plurality of candidate test data injection channels according to the test requirement, and then performs test data injection. Therefore, real-time, timing and fixed-point test data interaction can be realized, and various test data interaction requirements can be met. The multiple test data can be injected into a Low PHY+DEF unit of which the probe I NP is embedded into the radio frequency end RU so as to realize test data interaction. That is, a plurality of test data injection nodes are set in the communication link in advance, and then a plurality of test data injection probes I NP are set correspondingly according to the data bypass mode of the plurality of test data injection nodes, and each test data injection probe I NP corresponds to a candidate test data injection channel.

Step S220, a second control signal sent by the application side is received, and a target test data injection channel corresponding to the second control signal is determined.

In this embodiment, the second control signal may be a test data injection instruction. Specifically, the processing side receives a test data injection instruction sent by the application side, and determines a corresponding target test data injection channel according to the test data injection instruction. Further, a schematic diagram of the FPGA chip architecture in this embodiment may refer to fig. 8.

FIG. 8 is a schematic diagram of an FPGA chip architecture in an embodiment of the invention. As shown in fig. 8, the FPGA chip of the present embodiment includes a processing side 4, an application side 5, and a memory 6. Wherein the processing side 4 comprises a second test data transmitter 41 and a Low phy+def unit 42. The second test data transmitter 41 includes an FB DMA interface 411, a second burst transmission controller 412 and a second buffer 413. The Low phy+def unit 42 includes a second channel controller 421.

In this embodiment, the processing side 4 may be PL, and the application side 5 may be PS. The communication between the processing side 4 and the application side 5 may be implemented through bus interfaces such as AX I4, AX I-Lite, AXI-Stream, and the like. The specific real-time manner is similar to the embodiment shown in fig. 5, and the present invention will not be described herein.

Alternatively, the application side 5 may be APP.

In this embodiment, because the debug mode of the tester simulation or JTAG in the prior art cannot fully cover the scenario of RU functional test and verification, for this case, in the embodiment of the present invention, the application side 5 (i.e., PS) controls the processing side 4 (i.e., PL) to select the corresponding test data acquisition channel and test data injection channel according to the set test data acquisition probe TAP and test data injection probe I NP, so as to implement test data interaction in the communication link. That is, the processing side 4 (i.e., PL) is used as a part related to the FPGA, and the processing side 4 performs test data interaction by using a probe in a circuit of the FPGA chip. Therefore, real-time, timing and fixed-point test data interaction can be realized, and the method is not limited by resources in the FPGA chip. And the cyclic test data injection and collection processes can be realized.

In the present embodiment, the second channel controller 421 is disposed in the Low phy+def unit 42, that is, the second channel controller 421 is disposed in the developed functional software of the radio frequency end RU, so that channel switching can be directly performed to inject test data. Therefore, universality of test data interaction is improved. The second channel controller 421 may be a Switch controller, which belongs to a custom test data injection channel control logic and is used for channel switching.

Optionally, the second channel controller 421 may be further disposed outside the Low phy+def unit 42 and the second test data transmitter 41. The second channel controller 421 may also be provided in the second test data transmitter 41.

In this embodiment, the second test data transmitter 41 may be an RTS for the second target test data transmission.

In this embodiment, the FB DMA interface 411 is used for performing test data transmission by way of direct memory access.

In this embodiment, the second burst transmission controller 412 may be rBurst control l, which belongs to the custom burst data control logic.

In this embodiment, the second buffer 413 may be FB DMA rffo, similar to the FB DMA wF FO shown in fig. 5, for buffering test data to be injected.

Alternatively, the memory 6 may be a DDR memory.

In the following description, switch control l is the second channel controller 421,rBurst Contro l, the second burst transfer controller 412,FB DMA rFI FO, and the second buffer 413.

In this embodiment, the tester may send the second control signal to the Switch control l in the Low phy+def unit 42 of the processing side 4 through the application side 5, and the Switch control l may determine the target test data injection channel from a plurality of test data injection channels corresponding to the plurality of test data injection probes I NP according to the second control signal.

In an alternative embodiment, the second control signal may include a target test data injection channel number and/or a test data injection probe iinp identifier, and the Switch controller may determine a target test data injection channel from a plurality of candidate test data injection channels corresponding to the plurality of test data injection probes iinp according to the second control signal.

In another alternative embodiment, the second control signal may also include a plurality of target test data injection channel numbers and/or a plurality of test data injection probe iinp identifications. The Switch controller may determine a plurality of target test data injection channels from among a plurality of candidate test data injection channels corresponding to the plurality of test data injection probes I NP according to the second control signal.

Step S230, determining the current test data injection channel.

In this embodiment, the Switch control determines one or more current test data injection channels after receiving the second control signal sent by the application side 5.

In the present embodiment, step S220 and step S230 may be performed in the current order. Step S220 and step S230 may also be performed simultaneously. Step S230 may also be performed before step S220.

Step S240, switching the current test data injection channel to the target test data injection channel.

In an alternative embodiment, if the current test data injection channel is different from the target test data injection channel, switch control l switches the current test data injection channel to the target test data injection channel. For example, if the current test data injection channel is the test data injection channel corresponding to the test data injection probe I NP1 and the target test data injection channel is the test data injection channel corresponding to the test data injection probe I NP2, the Switch controller switches the test data injection channel corresponding to the test data injection probe I NP1 to the test data injection channel corresponding to the test data injection probe I NP 2.

In another alternative embodiment, if the current test data injection channel is the same as the target test data injection channel, then the Switch control does not need to perform a data injection channel Switch.

Step S250, receiving second target test data sent by the application side, and sending the second target test data to a test data injection node corresponding to the communication link of the target test data injection channel in a burst transmission mode.

In the present embodiment, step S250 includes step S251 and step S252. In particular, reference may be made to fig. 9.

Fig. 9 is a flowchart of sending second target test data to a test data injection node corresponding to a communication link of a target test data injection channel by burst transmission in an embodiment of the present invention. As shown in fig. 9, the process of sending the second target test data to the test data injection node corresponding to the communication link by the target test data injection channel through the burst transmission in this embodiment includes the following steps:

step S251, determining one or more second burst data segments according to the second target test data.

In this embodiment, the tester may store the second target test data to be injected under the preset path of the application side 5, and write the second target test data to be injected into the memory 6. Further, the application side 5 sends a second communication signal to the rBurst Contro l in the processing side 4, where the second communication signal includes a second target test data length to indicate the rBurst Contro l second target test data length. And then rBurst Contro l calculates the Burst transmission times according to the length of the second target test data to be transmitted. Meanwhile, rBurst Contro l sends a request signal to FB DMA interface 411. The request signal may be an FB DMA RREQ pulse signal that is used to request a Burst transfer from the FB DMA interface 411. Further, FB DMA interface 411, upon receiving the request signal, sets FB DMA RBUSY high to indicate rBurst control is currently idle and completes the handshake. Then rBurst Contro l obtains second target test data from the preset path of the application side 5 through the FB DMA interface 411, and determines one or more second burst data segments according to the second target test data.

In this embodiment, the FB DMA interface 411 may acquire the second target test data from the preset path of the application side 5 through the AX I bus interface in a direct memory access manner, and then send the second target test data to rBurst controller.

Optionally, the FB DMA interface 411 may set FB DMA RBUSY to a low level to indicate that rBurst Contro is currently busy when receiving a request signal sent by rBurst Contro. The rBurst Contro l may send a request signal to the rBurst Contro l by means of a poll so that the handshake is finally completed to achieve the second target test data transfer.

Optionally, if the request signal includes a Burst transfer number, the FB DMA interface 411 may determine the Burst transfer number (i.e. rBURST I ME) according to the request signal.

Step S252, one or more second burst data segments are sent to the test data injection nodes corresponding to the target test data injection channels in the communication link.

In this embodiment, rBurst Contro l may store one or more second burst data segments to FB DMA rFIFO. Further, the processing side 4 may further comprise a test data injection controller, which may be I njected Contro l, belonging to a kind of test data injection logic. If I njected Contro l detects that the FB DMA rFIFO is not null, I njected Contro l continuously reads one or more second burst data segments from the FB DMA rFIFO, and injects the one or more second burst data segments into the test data injection node corresponding to the target test data injection channel in the communication link through Switch control l, so that the test data injection is completed.

In this embodiment, after the FB DMA interface 411 completes one BURST transfer, FB DMA RVALI D is set to low level, and rBURST I ME is increased by 1, waiting for rBURST control l to send a request signal next time, and performing BURST transfer again.

After receiving a second control signal sent by an application side at a processing side, determining a target test data injection channel in a plurality of candidate test data injection channels arranged in a communication link according to the second control signal, and after receiving second target test data sent by the application side at the processing side, sending the second target test data to a test data injection node corresponding to the communication link by the target test data injection channel in a burst transmission mode. Therefore, real-time, timing and fixed-point test data interaction can be realized, so that various test data interaction requirements are met, and test data interaction efficiency and universality are improved.

FIG. 10 is a flow chart of a test data interaction device according to an embodiment of the present invention. In the embodiment shown in fig. 10, the test data interaction device of the present embodiment includes a first control signal receiving unit 411, a target test data acquisition channel determining unit 412, a first target test data acquiring unit 413, and a first target test data transmitting unit 414. The first control signal receiving unit 411 is configured to receive a first control signal sent by an application side. The target test data acquisition channel determining unit 412 is configured to determine a target test data acquisition channel corresponding to the first control signal. The first target test data obtaining unit 413 is configured to obtain first target test data from a corresponding test data collection node in the communication link through the target test data collection channel. The first target test data sending unit 414 is configured to send the first target test data to the application side by using a burst transmission manner.

In some embodiments, the test data interaction device further comprises:

the candidate test data acquisition channel setting unit is used for setting a plurality of corresponding candidate test data acquisition channels according to a plurality of test data acquisition nodes in the communication link;

the target test data acquisition channel determining unit 412 is further configured to determine the target test data acquisition channel from a plurality of candidate test data acquisition channels according to the first control signal.

In some embodiments, the test data interaction device further comprises:

the current test data acquisition channel determining unit is used for determining a current test data acquisition channel; and

and the channel switching unit is used for switching the current test data acquisition channel into the target test data acquisition channel.

In some embodiments, the first target test data sending unit 414 is further configured to:

and sending the one or more first burst data segments to the application side.

In some embodiments, the test data interaction device further comprises:

the second control signal receiving unit is used for receiving a second control signal sent by the application side;

the target test data injection channel determining unit is used for determining a target test data injection channel corresponding to the second control signal; and

and the second target test data transmitting unit is used for responding to the received second target test data transmitted by the application side and transmitting the second target test data to the test data injection node corresponding to the communication link of the target test data injection channel in a burst transmission mode.

In some embodiments, the test data interaction device further comprises:

a candidate test data injection channel setting unit, configured to set a plurality of corresponding candidate test data injection channels according to a plurality of test data injection nodes in the communication link;

the target test data injection channel determining unit is further configured to determine the target test data injection channel from a plurality of candidate test data injection channels according to the second control signal.

In some embodiments, the second target test data transmitting unit is further configured to:

The foregoing description of the preferred embodiment of the invention is not intended to be limiting, but rather, the invention is susceptible to various modifications and alternative forms as will occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of testing data interaction, the method comprising:

receiving a first control signal sent by an application side;

2. The test data interaction method of claim 1, wherein the method further comprises:

3. The test data interaction method of claim 1, wherein the method further comprises:

determining a current test data acquisition channel; and

4. The test data interaction method according to claim 1, wherein the transmitting the first target test data to the application side by means of burst transmission includes:

and sending the one or more first burst data segments to the application side.

5. The method of testing data interaction of claim 4, wherein the sending the one or more first burst data segments to the application side comprises:

6. The test data interaction method of claim 1, wherein the method further comprises:

receiving a second control signal sent by an application side;

7. The method of testing data interaction of claim 6, wherein the method further comprises:

8. The method of claim 6, wherein the sending the second target test data to the test data injection node corresponding to the communication link by means of burst transmission includes:

9. A test data interaction device, the device comprising:

10. An electronic device, the device comprising:

a memory for storing one or more computer program instructions;

a processor, the one or more computer program instructions being executed by the processor to implement the method of any of claims 1-8.