CN101286738A - Method, device and system for loading logic files based on equipment information - Google Patents
Method, device and system for loading logic files based on equipment information Download PDFInfo
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- CN101286738A CN101286738A CNA200810094196XA CN200810094196A CN101286738A CN 101286738 A CN101286738 A CN 101286738A CN A200810094196X A CNA200810094196X A CN A200810094196XA CN 200810094196 A CN200810094196 A CN 200810094196A CN 101286738 A CN101286738 A CN 101286738A
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Abstract
The embodiment of the invention discloses a method for loading a logic file according to equipment information. The method includes the steps that: the hardware information of equipment is obtained and corresponds to the storage address of the logic file; the storage address of the logic file is selected from a storage device according to the hardware information of the equipment; the logic file is read from the storage address and loaded to a programmable logic device. The embodiment of the invention also discloses a device for loading the logic file according to equipment information and a system thereof. By utilizing the embodiment of the invention, the purpose that the logic file after being read from the corresponding storage address of the equipment is then loaded to the programmable logic device according to the corresponding relation between the hardware information and the storage address of the logic file can be achieved on the basis that after the hardware information is acquired, according to the acquired hardware information of the equipment, the storage address of the logic file is selected from the storage device and then the logic file read from the storage address is loaded to the programmable logic device.
Description
Technical field
The present invention relates to the hardware configuration technical field, particularly relate to methods, devices and systems according to the facility information loading logic file.
Background technology
CPLD (Complex Programmable Logic Device, CPLD) structures shape after power down its configuration can not lose yet, in general design it can finish complicated, the logic function of higher speed, as interface conversion, total line traffic control etc.FPGA (Field Programmable GateArray, field programmable gate array) is the high performance programmable logical device that on the basis of CPLD, grows up, compare with CPLD, the integrated level of FPGA is very high, its density does not wait to tens million of system doors from tens thousand of system doors, can finish complicated sequential and combinational logic circuit function, be suitable for using at a high speed and in the highdensity circuit design.But because general FPGA commonly used does not have memory function, content after outage in the chip will disappear, so we generally its configuration file is left in the outer outage of sheet can the memory device of lost content yet in, as flash (be nonvolatile storage, can carry out erasable and programming again) to the memory cell block that is called piece.When powering on, read content among the flash by CPLD, dispose FPGA by configuration pin then and rework.
As a rule, the hardware information of the equipment that every cover is different need with fire configuration file corresponding with it, otherwise system just can't operate as normal.But, owing in process, need to select correct load document with the burned external devices of configuration file, and configuration device, this process all needs some minutes usually.
A kind of implementation method of the prior art is normally: externally in the memory device, as memory, the fpga logic file of burned a plurality of corresponding different hardware configurations is about to the different address fields of the burned memory external body of a plurality of logics; By stirring toggle switch, select the memory address of corresponding fpga logic file in flash; Promptly will load which logic to FPGA by toggle switch artificial selection; The logical file of reading external memory spare is come in the address that CPLD indicates according to toggle switch, and logical file loading in FPGA, has been reconfigured FPGA, and new function is come into force.
The inventor finds that there are the following problems at least in the prior art when realization is of the present invention:
Because prior art needs the manual operation toggle switch, this just needs the operator to understand the corresponding relation of logical versions and hardware in advance.If operating mistake will cause the FPGA configuration error, system's cisco unity malfunction will appear, even the situation of the system of damage.
Summary of the invention
The purpose of the one or more embodiment of the present invention is to provide a kind of methods, devices and systems according to the facility information loading logic file, to improve the efficient that loads.
For addressing the above problem, the embodiment of the invention provides a kind of method according to the facility information loading logic file, comprising:
Obtain the hardware information of equipment, described hardware information is corresponding to the memory address of logical file;
From memory device, select the memory address of logical file according to the hardware information of described equipment;
Read logical file from described memory address;
Described logical file loading is arrived programmable logic device.
A kind of device according to the facility information loading logic file also is provided, has comprised:
The hardware information acquiring unit is used to the hardware information of the equipment that obtains, and described hardware information is corresponding to the memory address of logical file;
The memory address selected cell is used for selecting from memory device according to the hardware information of described equipment the memory address of logical file;
The logical file loading unit, the logical file loading that is used for reading from described memory address is to programmable logic device.
The embodiment of the invention also provides a kind of system according to the facility information loading logic file, comprising:
The device of loading logic file, be used to obtain the hardware information of external equipment, described hardware information is corresponding to the memory address of logical file, selects the memory address of logical file according to the hardware information of described equipment from memory device, reads logical file from described memory address;
Programmable logic device is used to receive the logical file that the device of loading logic file loads, and carries out corresponding operating according to logical file.
Compared with prior art, the embodiment of the invention has the following advantages:
Utilize the embodiment of the invention, after can obtaining the hardware information of equipment, from memory device, select the memory address of logical file according to the hardware information of described equipment, the described logical file loading that will read from described memory address is to hardware again, corresponding relation according to the memory address of hardware information and logical file, be loaded in the programmable logic device after reading logical file on the memory address corresponding, thereby the embodiment of the invention has following beneficial effect with described equipment:
At first, improve the efficient that loads, need not select toggle switch, loaded moment to finish, saved the time.
Secondly, whole process does not need manual intervention, has avoided because the appearance of the mistake that the manual operation error causes, can upgrading hardware without the personnel that train yet.
Once more, prevented people's malice effectively or non-ly tampered toggle switch, thereby hardware has illegally been disposed or the situation of upgrading takes place through authorizing.
At last, owing to, externally find its logical file in the memory device, thereby can be configured multiple different programmable logic device neatly for multiple different equipment.
Description of drawings
Shown in Figure 1, be the flow chart of the embodiment one of method of the present invention;
Shown in Figure 2, be the flow chart of the embodiment two of method of the present invention;
Shown in Figure 3, be the flow chart of the embodiment three of method of the present invention;
Shown in Figure 4, be the block diagram of the embodiment of device of the present invention;
Shown in Figure 5, be the block diagram of the embodiment of system of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the invention is done further and to be elaborated.
With reference to shown in Figure 1, be the embodiment one of method of the present invention, comprise step:
Step 101, obtain the hardware information of equipment, described hardware information is corresponding to the memory address of logical file; Just can obtain hardware information by the I2C bus, perhaps other and the approach that hardware can be communicated by letter can obtain the hardware information of equipment;
Step 102, from memory device, select the memory address of logical file according to the hardware information of described equipment;
Step 103, read logical file from described memory address;
Step 104, with described logical file loading to programmable logic device, in practice, described programmable logic device can be various on-site programmable gate array FPGAs usually.
Utilize the embodiment of the invention, after can obtaining the hardware information of equipment, from memory device, select the memory address of logical file according to the hardware information of described equipment, the described logical file loading that will read from described memory address is to programmable logic device again, realized corresponding relation, be loaded in the programmable logic device after reading logical file on the memory address corresponding with described equipment according to the memory address of hardware information and logical file.
On the basis of above-mentioned effect, the embodiment of the invention also has the following advantages:
At first, improve the efficient that loads, saved the time.
Secondly, avoided the appearance of the mistake that causes because manual operation is slipped up.
Once more, prevented people's malice effectively or non-ly tampered toggle switch, thereby hardware has illegally been disposed or the situation of upgrading takes place through authorizing.
Wherein, in the above-described embodiments, the described hardware information that obtains equipment is specially:
CPLD directly obtains the hardware information of equipment; Perhaps
CPLD is loaded into described programmable logic device with the configuration file of storing in the described memory device, obtain the hardware information of equipment behind the described programmable logic device execution configuration file, the described hardware information that described programmable logic device will obtain sends to described CPLD.
Wherein, in the above-described embodiments, the described hardware information that described programmable logic device will obtain sends to the CPLD step and is specially:
The described hardware information that described programmable logic device will obtain sends to the CPLD register.
Wherein, in the above-described embodiments, after the described hardware information step of obtaining equipment, described hardware information according to described equipment is selected the memory address step of logical file from memory device before, can also comprise:
Judge according to the hardware information of described equipment whether corresponding equipment is legal;
If, the memory address step that then enters described selection logical file;
If not, then disregard.
Wherein, in the above-described embodiments, can also comprise:
According to the described hardware information that obtains, show and need reload logical file, then enter the described memory address step of from memory device, selecting logical file according to the hardware information of described equipment.
Wherein, in the above-described embodiments, described hardware information is specially:
SPD (the serial module exists detection, SERIAL PRESENCE DETECT) information; Or
Unit type.
Below, in conjunction with the accompanying drawings, introduce two kinds of concrete Application Examples of method of the present invention, with reference to shown in Figure 2, be method embodiment two of the present invention, comprise step:
The SPD information of step 201, CPLD fetch equipment or other available hardware are for information about;
Step 202, CPLD obtain the model of equipment according to described hardware information; In practice, can also judge whether described equipment is legitimate device, only is under the situation of legitimate device according to described hardware information or the unit type obtained, just loading logic file in FPGA;
Step 203, CPLD are according to the model of described equipment, and CPLD obtains logical file corresponding with described model and the memory address in FLASH thereof;
Step 204, CPLD read described logical file from the described memory address of FLASH;
Step 205, CPLD advance described FPGA with described logical file loading.
Utilize the embodiment of the invention, SPD or other relevant hardware informations have been realized by the CPLD fetch equipment, then according to hardware information, read corresponding logical file in the memory address corresponding in the FLASH with described hardware information, again with the logical file loading that reads in FPGA.
Embodiment two provides the execution mode that is obtained hardware information by CPLD.Different with embodiment two, less for Capacity Ratio, fail to lay down the CPLD of hardware information read module, the hardware information read module can be placed in the logic of FPGA.When powering on, earlier the hardware information fetch program is loaded into FPGA, come fetch equipment SPD information or other available hardware information by FPGA, make the whether legal judgement of hardware by FPGA then, again hardware information is sent to CPLD, by the CPLD logical file that selection will load according to hardware information, and with described logical file loading FPGA.Please refer to shown in Figure 3ly, is the flow chart of the embodiment three of method of the present invention, comprises step:
Step 301, CPLD read FLASH, load the configuration file that comprises the I2C bus control unit to FPGA;
Step 302, according to the data of returning by the I2C bus, the composition situation of FPGA analysis circuit obtaining the hardware information of equipment, and returns to CPLD with hardware information;
The hardware information that step 303, CPLD return according to FPGA judges which fpga logic file needs load, and corresponding memory address; In practice, CPLD can also judge whether to reload logical file, and only when needs reload logical file, just loading logic file is to FPGA, otherwise just do not load; Also can judge whether described equipment is legitimate device, only legitimate device be carried out the loading of logical file according to described hardware information, for illegal equipment, loading logic file not then, thus refuse the upgrading requirement of illegal hardware;
Step 304, CPLD read the logical file among the FLASH, and it is loaded among the FPGA, reconfigure FPGA, and new function is come into force.
Utilize embodiments of the invention, realized the hardware information acquisition module being loaded into FPGA by CPLD, then FPGA finishes the work of obtaining of hardware information, the described hardware information that obtains according to FPGA by CPLD again, automatically after reading the logical file of respective stored address in the outside FLASH, be loaded among the FPGA, realized configuration FPGA.The CPLD that has overcome low capacity can not carry out the deficiency that hardware information obtains, and has expanded method of the present invention greatly and has realized scope.
With reference to shown in Figure 4, be a kind of device that device embodiment of the present invention is provided according to the facility information loading logic file, comprising:
Hardware information acquiring unit 401 is used to the hardware information of the equipment that obtains, and described hardware information is corresponding to the memory address of logical file;
Memory address selected cell 402 is used for selecting from memory device according to the hardware information of described equipment the memory address of logical file;
Logical file loading unit 403, the logical file loading that is used for reading from described memory address is to programmable logic device.
Utilize the embodiment of the invention, after can obtaining the hardware information of equipment, from memory device, select the memory address of logical file according to the hardware information of described equipment, the described logical file loading that will read from described memory address is to programmable logic device again, realized corresponding relation according to the memory address of hardware information and logical file, be loaded in the programmable logic device after reading logical file on the memory address corresponding with described equipment, described programmable logic device can be FPGA usually in practice.
On the basis of above-mentioned effect, the embodiment of the invention has the following advantages:
At first, improve the efficient that loads, saved the time.
Secondly, avoided the appearance of the mistake that causes because manual operation is slipped up.
Once more, prevented people's malice effectively or non-ly tampered toggle switch, thereby hardware has illegally been disposed or the situation of upgrading takes place through authorizing.
Wherein, in the above-described embodiments, can also comprise:
The configuration file loading unit, be used for: the configuration file that described memory device is stored is loaded into described programmable logic device, to indicate described programmable logic device to carry out the hardware information of the equipment that obtains behind the configuration file, the described hardware information that described then programmable logic device will obtain sends to described hardware information acquiring unit.
Wherein, in the above-described embodiments, described hardware information acquiring unit can also comprise:
Register is used to receive the described hardware information that described programmable logic device sends.
Wherein, in the above-described embodiments, described hardware information is specially:
SPD information; Or
Unit type.
Wherein, in the above-described embodiments, can also comprise:
Load judging unit, be used for: according to the described hardware information that obtains, show and to reload logical file, then indicate the work of described memory address selected cell.
With reference to shown in Figure 5, be system embodiment of the present invention, present embodiment discloses a kind of system according to the facility information loading logic file, comprising:
The device 501 and the programmable logic device 502 of the disclosed loading logic file of each device embodiment of the present invention; Described programmable logic device 502 can be FPGA usually;
The device 501 of described loading logic file is used to obtain the hardware information of external equipment, described hardware information is corresponding to the memory address of logical file, from memory device, select the memory address of logical file according to the hardware information of described equipment, read logical file from described memory address;
Described programmable logic device 502 receives the logical file of device 501 loadings of loading logic file, carries out corresponding operating according to logical file.
The embodiment of the invention can improve loading efficiency, does not need manual intervention, prevents that effectively the someone from illegally disposing or illegally mandate.
Above-described embodiment of the present invention does not constitute the qualification to protection range of the present invention.Any modification of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, a kind of method according to the facility information loading logic file is characterized in that, comprising:
Obtain the hardware information of equipment, described hardware information is corresponding to the memory address of logical file;
From memory device, select the memory address of logical file according to the hardware information of described equipment;
Read logical file from described memory address;
Described logical file loading is arrived programmable logic device.
2, the method for claim 1 is characterized in that, the described hardware information that obtains equipment is specially:
CPLD obtains the hardware information of equipment; Or
CPLD is loaded into described programmable logic device with the configuration file of storing in the described memory device, obtain the hardware information of equipment behind the described programmable logic device execution configuration file, the described hardware information that described programmable logic device will obtain sends to described CPLD.
3, method as claimed in claim 2 is characterized in that, the described hardware information that described programmable logic device will obtain sends to the CPLD step and is specially:
The described hardware information that described programmable logic device will obtain sends to the CPLD register.
4, the method for claim 1 is characterized in that, after the described hardware information step of obtaining equipment, described hardware information according to described equipment is selected the memory address step of logical file from memory device before, also comprises:
Judge according to the hardware information of described equipment whether described equipment is legal;
If, the memory address step that then enters described selection logical file;
If not, then disregard.
5, require each described method of 1-4 as claim, it is characterized in that described programmable logic device is specially on-site programmable gate array FPGA.
6, a kind of device according to the facility information loading logic file is characterized in that, comprising:
The hardware information acquiring unit is used to the hardware information of the equipment that obtains, and described hardware information is corresponding to the memory address of logical file;
The memory address selected cell is used for selecting from memory device according to the hardware information of described equipment the memory address of logical file;
The logical file loading unit, the logical file loading that is used for reading from described memory address is to programmable logic device.
7, device as claimed in claim 6 is characterized in that, also comprises:
The configuration file loading unit, be used for the configuration file that described memory device is stored is loaded into described programmable logic device, to indicate described programmable logic device to carry out the hardware information of the equipment that obtains behind the configuration file, the described hardware information that described then programmable logic device will obtain sends to described hardware information acquiring unit.
8, device as claimed in claim 7 is characterized in that, described hardware information acquiring unit also comprises:
Register is used to receive the described hardware information that described programmable logic device sends.
9, a kind of system according to the facility information loading logic file is characterized in that, comprising:
The device of loading logic file, be used to obtain the hardware information of external equipment, described hardware information is corresponding to the memory address of logical file, selects the memory address of logical file according to the hardware information of described equipment from memory device, reads logical file from described memory address;
Programmable logic device is used to receive the logical file that the device of loading logic file loads, and carries out corresponding operating according to logical file.
10, device as claimed in claim 9 is characterized in that, the device of described loading logic file specifically comprises:
The hardware information acquiring unit is used to the hardware information of the equipment that obtains, and described hardware information is corresponding to the memory address of logical file;
The memory address selected cell is used for selecting from memory device according to the hardware information of described equipment the memory address of logical file;
The logical file loading unit, the logical file loading that is used for reading from described memory address is to programmable logic device.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA200810094196XA CN101286738A (en) | 2008-05-15 | 2008-05-15 | Method, device and system for loading logic files based on equipment information |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA200810094196XA CN101286738A (en) | 2008-05-15 | 2008-05-15 | Method, device and system for loading logic files based on equipment information |
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| CNA200810094196XA Pending CN101286738A (en) | 2008-05-15 | 2008-05-15 | Method, device and system for loading logic files based on equipment information |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102148754A (en) * | 2010-12-30 | 2011-08-10 | 杭州华三通信技术有限公司 | Loading method and device for FPGA (field programmable gate array) logic editions |
| CN102361451A (en) * | 2011-09-06 | 2012-02-22 | 北京时代民芯科技有限公司 | FPGA (Field Programmable Gate Array) configuration circuit structure |
| CN101706550B (en) * | 2009-11-19 | 2012-02-22 | 福建联迪商用设备有限公司 | Method for testing mainboard |
| CN103399758A (en) * | 2011-12-31 | 2013-11-20 | 华为数字技术（成都）有限公司 | Hardware accelerating method, device and system |
| CN108362995A (en) * | 2013-10-12 | 2018-08-03 | 深圳市爱德特科技有限公司 | A kind of application method of the FPGA of innovation |
| CN109271185A (en) * | 2018-08-30 | 2019-01-25 | 郑州云海信息技术有限公司 | A kind of CPLD method for updating edition, device, equipment and storage medium |
| CN110888834A (en) * | 2019-11-06 | 2020-03-17 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Method and system for dynamically reconstructing FPGA function in PCIE equipment |
| CN111857867A (en) * | 2020-06-30 | 2020-10-30 | 新华三技术有限公司 | Logic file loading method and device and network equipment |
| CN114035994A (en) * | 2021-11-17 | 2022-02-11 | 北京极光星通科技有限公司 | Data storage system, failure processing method, electronic device, and storage medium |
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2008
- 2008-05-15 CN CNA200810094196XA patent/CN101286738A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101706550B (en) * | 2009-11-19 | 2012-02-22 | 福建联迪商用设备有限公司 | Method for testing mainboard |
| CN102148754B (en) * | 2010-12-30 | 2013-12-11 | 杭州华三通信技术有限公司 | Loading method and device for FPGA (field programmable gate array) logic editions |
| CN102148754A (en) * | 2010-12-30 | 2011-08-10 | 杭州华三通信技术有限公司 | Loading method and device for FPGA (field programmable gate array) logic editions |
| CN102361451A (en) * | 2011-09-06 | 2012-02-22 | 北京时代民芯科技有限公司 | FPGA (Field Programmable Gate Array) configuration circuit structure |
| CN102361451B (en) * | 2011-09-06 | 2013-10-02 | 北京时代民芯科技有限公司 | FPGA (Field Programmable Gate Array) configuration circuit structure |
| CN103399758B (en) * | 2011-12-31 | 2016-11-23 | 华为数字技术（成都）有限公司 | Hardware-accelerated methods, devices and systems |
| CN103399758A (en) * | 2011-12-31 | 2013-11-20 | 华为数字技术（成都）有限公司 | Hardware accelerating method, device and system |
| CN108362995A (en) * | 2013-10-12 | 2018-08-03 | 深圳市爱德特科技有限公司 | A kind of application method of the FPGA of innovation |
| CN109271185A (en) * | 2018-08-30 | 2019-01-25 | 郑州云海信息技术有限公司 | A kind of CPLD method for updating edition, device, equipment and storage medium |
| CN110888834A (en) * | 2019-11-06 | 2020-03-17 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Method and system for dynamically reconstructing FPGA function in PCIE equipment |
| CN110888834B (en) * | 2019-11-06 | 2022-05-31 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Method and system for dynamically reconstructing FPGA function in PCIE equipment |
| CN111857867A (en) * | 2020-06-30 | 2020-10-30 | 新华三技术有限公司 | Logic file loading method and device and network equipment |
| CN111857867B (en) * | 2020-06-30 | 2024-03-08 | 新华三技术有限公司 | Logic file loading method and device and network equipment |
| CN114035994A (en) * | 2021-11-17 | 2022-02-11 | 北京极光星通科技有限公司 | Data storage system, failure processing method, electronic device, and storage medium |
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