CN108336092B - 晶体管阵列面板 - Google Patents

晶体管阵列面板 Download PDF

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Publication number
CN108336092B
CN108336092B CN201810053469.XA CN201810053469A CN108336092B CN 108336092 B CN108336092 B CN 108336092B CN 201810053469 A CN201810053469 A CN 201810053469A CN 108336092 B CN108336092 B CN 108336092B
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transistor
electrode
insulator
layer
array panel
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CN108336092A (zh
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具本龙
卢正训
金善光
金莲璟
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Abstract

提供了一种晶体管阵列面板。根据示例性实施例的晶体管阵列面板包括基底以及位于基底上的第一晶体管和第二晶体管。第一晶体管和第二晶体管中的每个包括：第一电极；第二电极，与第一电极叠置；间隔构件，位于第一电极和第二电极之间；半导体层，沿间隔构件的侧壁延伸；以及栅电极，与半导体层叠置。第一晶体管的间隔构件的厚度大于第二晶体管的间隔构件的厚度。

Description

晶体管阵列面板
本申请要求于2017年1月19日在韩国知识产权局提交的第10-2017-0009161号韩国专利申请的优先权和权益，该韩国专利申请的全部内容通过引用包含于此。
技术领域
本公开涉及一种晶体管阵列面板和一种该晶体管阵列面板的制造方法。
背景技术
包括在诸如显示装置的各种电子装置中的晶体管包括栅电极、源电极、漏电极和半导体层。晶体管用作显示装置中的开关元件和驱动元件等。晶体管中的晶体管阵列面板用作电路板，以驱动显示装置中的像素。晶体管阵列面板可以包括传输栅极信号的栅极线和传输与图像信号对应的数据电压的数据线，并且可以包括连接到晶体管的像素电极。
为了满足对高分辨率显示装置的需求，可以考虑减小晶体管的平面尺寸的方法。通常，显示装置中使用的晶体管具有形成为基本平行于基底平面表面的沟道区。此外，晶体管的源电极和漏电极形成为在平面上彼此不叠置或不与沟道区叠置。因此，在晶体管的平面上减小尺寸存在许多限制。
存在其中沟道区形成为基本垂直于基底的平面的垂直型晶体管。因为源电极和漏电极在垂直型晶体管中彼此叠置，使得与传统的晶体管相比平面尺寸可以减小，所以它可以用在高分辨率显示装置中。然而，当在一个基底上形成具有不同沟道长度的晶体管时，与传统的晶体管相比，垂直型晶体管会需要复杂的工艺。
在该背景技术部分中公开的以上信息仅为了增强对背景技术的理解，因此，它可以包含不形成对本领域的普通技术人员而言在本国中已知的现有技术的信息。
发明内容
示例性实施例提供了一种包括具有不同沟道长度的垂直型晶体管的晶体管阵列面板和一种该晶体管阵列面板的制造方法。
根据示例性实施例的晶体管阵列面板包括基底以及位于基底上的第一晶体管和第二晶体管。第一晶体管和第二晶体管中的每个包括：第一电极；第二电极，与第一电极叠置；间隔构件，位于第一电极和第二电极之间；半导体层，沿间隔构件的侧壁延伸；以及栅电极，与半导体层叠置。第一晶体管的间隔构件的厚度大于第二晶体管的间隔构件的厚度。
第一晶体管的间隔构件可以包括第一绝缘体、第二绝缘体以及位于第一绝缘体和第二绝缘体之间的浮置电极，第二晶体管的间隔构件可以包括第一绝缘体。
第一晶体管的第一绝缘体可以与第二晶体管的第一绝缘体位于同一层处，第一晶体管的浮置电极可以与第二晶体管的第二电极位于同一层处。
第一晶体管的半导体层可以与第二晶体管的半导体层位于同一层处。
第一晶体管的半导体层可以包括在平行于基底的平面表面的方向上分别与第一晶体管的第一电极和第二电极叠置的第一部分和第二部分以及位于第一晶体管的第一部分和第二部分之间的沟道区。第二晶体管的半导体层可以包括在平行于基底的平面表面的方向上分别与第二晶体管的第一电极和第二电极叠置的第一部分和第二部分以及位于第二晶体管的第一部分和第二部分之间的沟道区。第一晶体管的沟道区的长度可以大于第二晶体管的沟道区的长度。
第一晶体管的第一电极与第二电极之间的间隔可以大于第二晶体管的第一电极与第二电极之间的间隔。
晶体管阵列面板还可以包括位于基底与第一晶体管和第二晶体管之间的缓冲层。缓冲层可以包括与第一晶体管和第二晶体管的第一电极叠置并且具有第一厚度的第一区域以及不与第一晶体管和第二晶体管的第一电极叠置并且具有小于第一厚度的第二厚度的第二区域。
第一晶体管的第一绝缘体、浮置电极、第二绝缘体和第二电极可以具有基本相同的平面形状，第一晶体管的浮置电极、第二绝缘体和第二电极的边缘可以基本匹配。
第一晶体管的半导体层、栅极绝缘层和栅电极可以具有基本相同的平面形状，第一晶体管的半导体层、栅极绝缘层和栅电极的边缘可以基本匹配。第二晶体管的半导体层、栅极绝缘层和栅电极可以具有基本相同的平面形状，第二晶体管的半导体层、栅极绝缘层和栅电极的边缘可以基本匹配。
第一晶体管的浮置电极的边缘可以位于第一晶体管的第一绝缘体的边缘内部。第二晶体管的第二电极的边缘可以位于第二晶体管的第一绝缘体的边缘内部。
晶体管阵列面板还可以包括连接到第一晶体管的第二电极的像素电极。
根据示例性实施例的晶体管阵列面板的制造方法包括：在基底上形成第一导电层并使第一导电层图案化以形成第一晶体管的第一电极和第二晶体管的第一电极；顺序地形成覆盖第一电极的第一绝缘层、第二导电层、第二绝缘层和第三导电层；使第一绝缘层、第二导电层、第二绝缘层和第三导电层图案化，以形成第一晶体管的间隔构件和第二电极以及第二晶体管的间隔构件和第二电极，其中，第一晶体管的间隔构件比第二晶体管的间隔构件厚；以及形成第一晶体管的半导体层和栅电极以及第二晶体管的半导体层和栅电极。
第一晶体管的间隔构件可以包括由第一绝缘层形成的第一绝缘体、由第二导电层形成的浮置电极以及由第二绝缘层形成的第二绝缘体。第二晶体管的间隔构件可以包括由第一绝缘层形成的第一绝缘体。
第一晶体管的第二电极可以由第三导电层形成，第二晶体管的第二电极可以由第二导电层形成。
第一绝缘层、第二导电层、第二绝缘层和第三导电层的图案化可以包括以下步骤：在第二绝缘层上形成包括具有不同厚度的第一部分和第二部分的第一光敏膜图案；通过使用第一光敏膜图案作为掩模来蚀刻第三导电层，以形成第三导电层图案；通过使用第一光敏膜图案作为掩模来蚀刻第二绝缘层，以形成第二绝缘层图案；通过使用第一光敏膜图案作为掩膜来蚀刻第二导电层，以形成第一晶体管的浮置电极和第二晶体管的第二电极；以及通过使用第一光敏膜图案作为掩膜来蚀刻第一绝缘层，以形成第一晶体管的第一绝缘体和第二晶体管的第一绝缘体。
当蚀刻第三导电层、第二绝缘层和第一绝缘层时可以使用干法蚀刻，当蚀刻第二导电层时可以使用湿法蚀刻。
第一绝缘层、第二导电层、第二绝缘层和第三导电层的图案化还可以包括以下步骤：通过回蚀法使第一光敏膜图案图案化，以形成二次光敏膜图案；以及通过使用二次光敏膜图案作为掩模来蚀刻第三导电层图案和第二绝缘层图案，以形成第一晶体管的第二电极和第二绝缘体。
当蚀刻第三导电层图案和第二绝缘层图案时可以使用干法蚀刻。
第一晶体管和第二晶体管的半导体层和栅电极的形成可以包括以下步骤：顺序地沉积半导体层、第三绝缘层和第四导电层；蚀刻第四导电层，以形成第一晶体管和第二晶体管的栅电极；蚀刻第三绝缘层，以形成第一晶体管和第二晶体管的栅极绝缘层；以及蚀刻半导体层，以形成第一晶体管和第二晶体管的半导体层。
该方法还可以包括：形成覆盖第一晶体管和第二晶体管的平坦化层；以及形成连接到第一晶体管的第二电极的像素电极。
根据示例性实施例，可以提供包括具有不同沟道长度的垂直型晶体管的晶体管阵列面板。此外，可以通过使用一个掩模而使垂直型晶体管的沟道长度形成为不同。
附图说明
图1是根据示例性实施例的晶体管阵列面板的示意性俯视平面图。
图2是沿图1中的线II-II'截取的示意性剖视图。
图3、图4、图5、图6、图7和图8是根据示例性实施例的晶体管阵列面板的制造方法的工艺剖视图。
图9是根据示例性实施例的晶体管阵列面板的示意性剖视图。
图10是包括根据示例性实施例的晶体管阵列面板的显示装置的等效电路图。
图11是包括根据示例性实施例的晶体管阵列面板的显示装置的示意性剖视图。
具体实施方式
在下文中将参照示出发明的示例性实施例的附图更充分地描述本发明。如本领域的技术人员将理解的，在所有不脱离本发明的精神或范围的情况下，描述的实施例可以以各种不同的方式进行修改。
贯穿说明书，同样的附图标记表示同样的元件。在附图中，可以放大或减小各层和各区域的厚度或尺寸，以清楚地示出它们的布置和相对位置。
将理解的是，当诸如层、膜、区域或基底的元件被称作“在”另一元件“上”时，它可以直接在另一元件上，或者也可以存在中间元件。相反，当元件被称作“直接在”另一元件“上”时，不存在中间元件。
此外，除非明确描述为相反，否则词语“包括”及其变型将理解为暗指包括陈述的元件而不排除任何其它元件。
此外，在本说明书中，短语“在平面上”意为从顶部观察目标部分，短语“在截面上”意为从侧面观察通过垂直地切割目标部分形成的截面。
现在将参照附图详细描述根据本发明的示例性实施例的晶体管阵列面板。
图1是根据示例性实施例的晶体管阵列面板的示意性俯视平面图，图2是沿图1中的线II-II'截取的示意性剖视图。
参照图1和图2，晶体管阵列面板包括基底110以及形成在基底110上的第一晶体管T1和第二晶体管T2。第一晶体管T1具有第一沟道长度L1，第二晶体管T2具有比第一沟道长度L1短的第二沟道长度L2。虽然未示出，但是晶体管阵列面板可以包括连接到第一晶体管T1、第二晶体管T2或另一晶体管的像素电极。
第一晶体管T1包括第一电极173a、第二电极175a、栅电极124a和半导体层130a。第一绝缘体141a、浮置电极155a和第二绝缘体142a位于第一电极173a和第二电极175a之间。第一电极173a、第一绝缘体141a、浮置电极155a、第二绝缘体142a和第二电极175a顺序地沉积在基底110上。栅极绝缘层161a位于半导体层130a和栅电极124a之间。
第一电极173a和第二电极175a中的一个是源电极，另一个是漏电极。例如，第一电极173a可以是源电极，第二电极175a可以是漏电极，反之亦然。第一晶体管T1包括作为第一电极173a和第二电极175a之间的间隔构件的第一绝缘体141a、浮置电极155a和第二绝缘体142a。半导体层130a沿第一绝缘体141a、浮置电极155a和第二绝缘体142a的侧壁形成为(例如，沿垂直于由诸如图2中示出的方向D1和D2形成的平面表面的方向D3形成为)基本垂直于基底110的平面表面。半导体层130a包括第一部分133a、第二部分135a和沟道区131a，第一部分133a在平行于基底110的平面表面的方向D1上与第一电极173a叠置，第二部分135a与第二电极175a叠置，沟道区131a位于第一部分133a和第二部分135a之间。沟道区131a的长度与第一晶体管T1的沟道长度L1对应，并且可以与第一电极173a和第二电极175a之间的间隔大致相同。栅极绝缘层161a和栅电极124a顺序地沉积在半导体层130a上。
第二晶体管T2包括第一电极173b、第二电极155b、栅电极124b和半导体层130b。第一绝缘体141b位于第一电极173b和第二电极155b之间。第一电极173b、第一绝缘体141b和第二电极155b顺序地沉积在基底110上。第一电极173b和第二电极155b中的一个是源电极，另一个是漏电极。例如，第一电极173b可以是源电极，而第二电极155b可以是漏电极，反之亦然。第二晶体管T2包括作为第一电极173b和第二电极155b之间的间隔构件的第一绝缘体141b。半导体层130b沿第一绝缘体141b的侧壁形成为基本垂直于基底110的平面表面。半导体层130b包括第一部分133b和第二部分135b，其中，第一部分133b在平行于基底110的平面表面的方向D1上与第一电极173b叠置，第二部分135b与第二电极155b叠置，并且半导体层130b包括位于第一部分133b与第二部分135b之间的沟道区131b。沟道区131b的长度与第二晶体管T2的沟道长度L2对应，并且可以与第一电极173b和第二电极155b之间的间隔大致相同。栅极绝缘层161b和栅电极124b顺序地沉积在半导体层130b上。
虽然第二晶体管T2仅包括位于第一电极173b和第二电极155b之间的一个绝缘体141b，但是第一晶体管T1包括位于第一电极173a和第二电极175a之间的两个绝缘体141a和142a，并且还包括位于这些绝缘体141a和142a之间的浮置电极155a。因此，第一沟道长度L1可以比第二沟道长度L2长大约浮置电极155a和第二绝缘体142a的厚度。第二晶体管T2的第二电极155b可以直接位于第一绝缘体141b上。
在附图中，第一晶体管T1的沟道区131a和第二晶体管T2的沟道区131b垂直于基底110的平面表面；然而，其不限于此，沟道区131a和131b可以形成为相对于基底110的平面表面倾斜预定角度。第一晶体管T1和第二晶体管T2以及这些晶体管的构成元件为近似四边形；然而，它们可以具有诸如多边形、圆形、椭圆形等的各种平面形状。
第一晶体管T1的源电极和漏电极可以通过在向栅电极124a施加栅极导通电压时流过半导体层130a的沟道区131a的载流子的方向来确定，载流子从源电极流向漏电极。因此，在第一晶体管T1的操作期间，在n型晶体管中，电子从源电极流向漏电极，而在p型晶体管中，空穴从源电极流向漏电极。第二晶体管T2的源电极与漏电极的关系与第一晶体管T1的源电极与漏电极的关系相同。
接下来，将进一步详细描述构成晶体管阵列面板的构成元件和层。
基底110由诸如玻璃、塑料等的绝缘材料制成。基底110可以是光学透明的。
覆盖基底110的缓冲层111可以位于基底110上。缓冲层111可以包括诸如氧化硅(SiOx)、氮化硅(SiNx)、氧化铝(Al2O3)、氧化铪(HfO3)或氧化钇(Y2O3)的无机绝缘材料。缓冲层111可以是单层或多层。例如，当缓冲层111是双层时，缓冲层111的下层可以包括氮化硅，缓冲层111的上层可以包括氧化硅。缓冲层111可以用于防止使半导体的特性劣化的杂质扩散并且防止湿气渗透。缓冲层111可以在与第一电极173a和173b叠置的区域处具有第一厚度d1并且在不与第一电极173a和173b叠置的区域处具有第二厚度d2，第二厚度d2可以小于第一厚度d1。
第一晶体管T1的第一电极173a和第二晶体管T2的第一电极173b位于缓冲层111上。第一电极173a和第一电极173b可以位于同一层处，并且可以基本具有相同的厚度。这里，“同一层”可以意为在一个沉积工艺中由相同材料同时形成的层。第一电极173a和173b在平面上可以是近似四边形；然而，它们不限于此，并且例如可以是近似圆形。第一电极173a和173b可以包括诸如铜、铝、银、钼、铬、钽、钛、钨、镍的金属或它们的金属合金，并且可以是单层或多层。
第一晶体管T1的第一绝缘体141a位于第一电极173a上，第二晶体管T2的第一绝缘体141b位于第一电极173b上。第一绝缘体141a与第一绝缘体141b可以位于晶体管阵列面板中的同一层处，并且可以具有基本相同的厚度。第一绝缘体141a和第一绝缘体141b在平面上可以是近似四边形；然而，它们不限于此，并且例如可以是近似圆形。第一绝缘体141a的平面面积可以小于第一电极173a的平面面积，第一绝缘体141a的边缘可以位于第一电极173a的边缘内部。第一绝缘体141a和141b可以包括诸如氧化硅和氮化硅的无机绝缘材料，或者可以包括有机绝缘材料。
第一晶体管T1的浮置电极155a位于第一绝缘体141a上，第二晶体管T2的第二电极155b位于第一绝缘体141b上。浮置电极155a和第二电极155b可以位于晶体管阵列面板中的同一层处，并且可以具有基本相同的厚度。浮置电极155a的平面面积可以小于第一绝缘体141a的平面面积，浮置电极155a的边缘可以位于第一绝缘体141a的边缘内部。第二电极155b的平面面积可以小于第一绝缘体141b的平面面积，第二电极155b的边缘可以位于第一绝缘体141b的边缘内部。尽管未示出，但是在另一示例性实施例中，第二电极155b可以与第一绝缘体141b具有基本相同的平面形状，第二电极155b的边缘可以与第一绝缘体141b的边缘基本匹配。浮置电极155a和第二电极155b可以包括诸如铜、铝、银、钼、铬、钽、钛、钨、镍的金属或它们的金属合金，并且可以是单层或多层。浮置电极155a由与第二电极155b相似的导体形成，但处于电浮置状态(例如，与其它金属元件电隔离)。
第一晶体管T1的第二绝缘体142a和第二电极175a顺序地位于浮置电极155a上。第二绝缘体142a和第二电极175a可以与浮置电极155a具有基本相同的平面形状，第二绝缘体142a和第二电极175a的边缘可以与浮置电极155a的边缘基本匹配。第二绝缘体142a可以包括诸如氧化硅和氮化硅的无机绝缘材料，或者可以包括有机绝缘材料。第二电极175a可以包括诸如铜、铝、银、钼、铬、钽、钛、钨、镍的金属或它们的金属合金，并且可以是单层或多层。第二电极175a可以由与第一电极173a和/或浮置电极155a的材料不同的材料或者相同的材料形成。
第一晶体管T1的半导体层130a位于第二电极175a上，第二晶体管T2的半导体层130b位于第二电极155b上。半导体层130a沿作为间隔构件的第二绝缘体142a、浮置电极155a和第一绝缘体141a的侧壁向下延伸，半导体层130b沿作为间隔构件的第一绝缘体141b的侧壁向下延伸。半导体层130a的一端可以直接位于第二电极175a上，半导体层130a的另一端可以直接位于缓冲层111上。半导体层130b的一端可以直接位于第二电极155b上，半导体层130b的另一端可以直接位于缓冲层111上。
半导体层130a包括在平行于基底110的平面表面的方向D1上与第一绝缘体141a、浮置电极155a和第二绝缘体142a叠置的沟道区131a。半导体层130b包括在平行于基底110的平面表面的方向D1上与第一绝缘体141b叠置的沟道区131b。因此，第一晶体管T1的与沟道区131a的长度对应的沟道长度L1比第二晶体管T2的与沟道区131b的长度对应的沟道长度L2大与浮置电极155a和第二绝缘体142a的厚度对应的长度。半导体层130a包括沿方向D3分别位于沟道区131a下方和上方的第一部分133a和第二部分135a。第一部分133a与第一电极173a接触，第二部分135a与第二电极175a接触。半导体层130b包括沿方向D3分别位于沟道区131b下方和上方的第一部分133b和第二部分135b。第一部分133b可以与第一电极173b接触，第二部分135b可以与第二电极155b接触。
半导体层130a和130b可以包括金属氧化物、非晶硅、多晶硅等。例如，金属氧化物可以包括氧化锌(ZnO)、氧化锌锡(ZTO)、氧化锌铟(ZIO)、氧化铟(InO)、氧化钛(TiO)、氧化铟镓锌(IGZO)和氧化铟锌锡(IZTO)中的至少一种。
第一晶体管T1的栅极绝缘层161a和栅电极124a顺序地位于半导体层130a上。第二晶体管T2的栅极绝缘层161b和栅电极124b顺序地形成在半导体层130b上。栅极绝缘层161a和161b可以位于晶体管阵列面板中的彼此相同的层，栅电极124a和124b可以位于晶体管阵列面板中的彼此相同的层。栅极绝缘层161a、栅电极124a和半导体层130a可以具有基本相同的平面形状，栅极绝缘层161a、栅电极124a和半导体层130a的边缘可以基本匹配。栅极绝缘层161b、栅电极124b和半导体层130b可以具有基本相同的平面形状，栅极绝缘层161b、栅电极124b和半导体层130b的边缘可以基本匹配。栅极绝缘层161a和161b可以包括诸如氮化硅、氧化硅等的无机绝缘材料。栅电极124a和124b可以包括诸如钼、铝、铜、银、铬、钽、钛的金属或它们的金属合金，并且可以是单层或多层。
具有上述的结构的第一晶体管T1和第二晶体管T2可以分别用作例如有机发光器件的像素电路中的驱动晶体管和开关晶体管。对于开关晶体管，例如，为了快的驱动速度，沟道长度相对短是有利的。然而，对于驱动晶体管，例如为了减小由于栅极电压分布引起的亮度偏差，具有相对长的沟道长度会是有利的。
到目前为止，参照图1和图2描述了根据示例性实施例的晶体管阵列面板。接下来，将参照图3至图8描述制造该晶体管阵列面板的方法。
图3至图8是示出根据示例性实施例的晶体管阵列面板的制造方法的工艺剖视图。
参照图3，通过化学气相沉积(CVD)在基底110上沉积诸如氧化硅、氮化硅、氧化铝、氧化铪或氧化钇的无机绝缘材料，以形成缓冲层111。接下来，通过溅射在缓冲层111上沉积诸如金属的导电材料，以形成第一导电层(未示出)，并且通过使用由诸如光致抗蚀剂的光敏材料形成的光敏膜(未示出)和第一掩模(未示出)来使导电材料图案化，以形成第一晶体管T1的第一电极173a和第二晶体管T2的第一电极173b。
参照图4，在包括第一电极173a和173b的基底110上顺序地沉积第一绝缘层141、第二导电层150、第二绝缘层142和第三导电层170。可以通过沉积无机绝缘材料来分别形成第一绝缘层141和第二绝缘层142，可以通过沉积诸如金属的导电材料来分别形成第二导电层150和第三导电层170。第一绝缘层141和第二绝缘层142中的至少一个可以包括有机绝缘材料。
接下来，在第三导电层170上形成光敏膜(未示出)，并通过使用第二掩模M2使光敏膜(未示出)图案化，以形成第一光敏膜图案51。第一光敏膜图案51具有相对厚的第一部分51a和相对薄的第二部分51b。第一光敏膜图案51的厚度差可以通过使用第二掩模M2形成，第二掩模M2例如包括光完全穿过的透射区F、仅一部分光穿过的透反射区H和完全阻挡光的阻挡区B。在去除被光照射部分的具有正光敏性的光敏材料的情况下，第一光敏膜图案51的第一部分51a可以是与第二掩模M2的阻挡区B对应的部分，第二部分51b可以是通过与第二掩模M2的透反射区H对应而暴露的部分。当完全去除光敏材料时未形成第一光敏膜图案51的部分可以是与第二掩模M2的全部透射区F对应的暴露部分。在光敏材料具有负光敏性的情况下，与第一光敏膜图案51对应的第二掩模M2的透明度可以是相反的。第二掩模M2可以是半色调掩模。然而，也可以通过使用包括狭缝图案或格子图案的狭缝掩模以及半色调掩模来形成所示的第一光敏膜图案51。
参照图4和图5，使用第一光敏膜图案51作为掩模顺序地使第三导电层170、第二绝缘层142、第二导电层150和第一绝缘层141图案化。详细地，蚀刻第三导电层170以形成第三导电层图案170'，蚀刻第二绝缘层142以形成第二绝缘层图案142'，蚀刻第二导电层150以形成第一晶体管T1的浮置电极155a和第二晶体管T2的第二电极155b，蚀刻第一绝缘层141以形成第一晶体管T1的第一绝缘体141a和第二晶体管T2的第一绝缘体141b。可以在第三导电层170、第二绝缘层142和第一绝缘层141的蚀刻中使用干法蚀刻，可以在第二导电层150的蚀刻中使用湿法蚀刻。可选择地，当蚀刻第三导电层170、第二绝缘层142和/或第一绝缘层141时可以使用湿法蚀刻，当蚀刻第二导电层150时可以使用干法蚀刻。
虽然通过使用一个光敏膜图案(例如，第一光敏膜图案51)作为掩模来蚀刻四个层，但是通过干法蚀刻形成的第三导电层图案170'、第二绝缘层图案142'以及第一绝缘体141a和141b的边缘可以与第一光敏膜图案51的边缘基本匹配，而由于蚀刻剂的各向同性蚀刻特性通过湿法蚀刻形成的浮置电极155a和第二电极155b的边缘可以位于第一光敏膜图案51的边缘内部。例如，因为诸如铜的金属会相对较难于通过干法蚀刻进行蚀刻，所以第三导电层170可以包括诸如铝、钼或钛的金属而不是铜。相反，通过湿法蚀刻蚀刻的第二导电层150可以包括铜以及诸如铝、钼或钛的金属。
参照图6，通过回蚀工艺去除作为第一光敏膜图案51的薄部分的第二部分51b。在这种情况下，也可以蚀刻第一部分51a，使得减小第一部分51a的宽度和高度，从而形成二次光敏膜图案52。在比形成有第一光敏膜图案51的第一部分51a的区域A窄的区域A'中形成二次光敏膜图案52。
参照图6和图7，通过使用二次光敏膜图案52作为掩模来蚀刻第三导电层图案170'和第二绝缘层图案142'，以形成第一晶体管T1的第二电极175a和第二绝缘体142a。在第三导电层图案170'和第二绝缘层图案142'的蚀刻中可以使用干法蚀刻。当蚀刻第三导电层图案170'和第二绝缘层图案142'时，完全去除设置在第二晶体管T2的第二电极155b上的第三导电层图案170'和第二绝缘层图案142'。在这种情况下，第二电极155b可以具有阻挡层的功能。当蚀刻第二绝缘层图案142'时，可以蚀刻缓冲层111的未被第一电极173a和173b覆盖的区域的表面。因此，缓冲层111可以包括被第一电极173a和173b覆盖并具有第一厚度d1的区域以及未被第一电极173a和173b覆盖并且具有比第一厚度d1小的第二厚度d2的区域。
参照图8，在具有第二电极175a和155b的基底110上顺序地沉积半导体层130、第三绝缘层160和第四导电层120。半导体层130可以由包括金属氧化物、非晶硅和多晶硅等的半导体材料形成，第三绝缘层160可以由无机绝缘材料形成，第四导电层120可以由诸如金属等的导电材料形成。接下来，通过使用光敏膜(未示出)和第三掩模(未示出)来蚀刻第四导电层120、第三绝缘层160和半导体层130，以形成图2中示出的第一晶体管T1的栅电极124a、栅极绝缘层161a和半导体层130a，并且以形成第二晶体管T2的栅电极124b、栅极绝缘层161b和半导体层130b。详细地，蚀刻第四导电层120以形成栅电极124a和124b，蚀刻第三绝缘层160以形成栅极绝缘层161a和161b，蚀刻半导体层130以形成半导体层130a和130b。当使第四导电层120、第三绝缘层160和半导体层130中的每个图案化时，可以使用干法蚀刻或湿法蚀刻。因为使用一个掩模，所以第一晶体管T1的栅电极124a、栅极绝缘层161a和半导体层130a可以具有基本相同的平面形状，其边缘可以基本匹配。此外，第二晶体管T2的栅电极124b、栅极绝缘层161b和半导体层130b可以具有基本相同的平面形状，其边缘可以基本匹配。
根据本示例性实施例，当一起形成具有不同沟道长度L1和L2的两个晶体管T1和T2时，使用所有三个掩模。具体地，通过使用一个掩模(例如，第二掩模M2)来形成第一晶体管T1的第一绝缘体141a、浮置电极155a、第二绝缘体142a和第二电极175a以及第二晶体管T2的第一绝缘体141b和第二电极155b。因此，通过仅使用一个掩模(例如，第二掩模M2)，可以使第一晶体管T1的与第一绝缘体141a、浮置电极155a和第二绝缘体142a的厚度对应的沟道长度L1以及第二晶体管T2的与第一绝缘体141b的厚度对应的沟道长度L2不同。此外，因为通过使用一个掩模(例如，第二掩模M2)来形成位于两个晶体管T1和T2的不同的层处的几个构成元件，所以可以防止构成元件的对准误差，使得可以使沟道长度的变化最小化，并且可以减少工艺步骤和工艺分布。此外，因为可以忽略当使用多个掩模时将考虑的第一晶体管T1的构成元件与第二晶体管T2的构成元件之间的重叠裕度(overlay margin)，因此晶体管的更紧凑设计是可行的。
接下来，将参照图9描述根据本发明的另一示例性实施例的晶体管阵列面板和制造方法，同时聚焦于与上述的示例性实施例的差异。省略或简化了相同特性的描述。
图9是根据示例性实施例的晶体管阵列面板的示意性剖视图。
参照图9，第一电极173a的不与第一绝缘体141a叠置的边缘部分的厚度比第一电极173a的与第一绝缘体141a叠置的区域薄。相似地，第一电极173b的不与第一绝缘体141b叠置的边缘部分的厚度比第一电极173b的与第一绝缘体141b叠置的区域薄。即使通过利用与图2至图7中示出的制造方法基本相同的工艺步骤来制造晶体管阵列面板，也可以根据蚀刻环境或使用的导电层的材料来形成第一电极173a和173b的台阶式厚度(steppedthickness)。
例如，在图6和图7中示出的工艺中，根据针对第三导电层图案170'的材料以及第一电极173a和173b的材料蚀刻第三导电层图案170'时使用的气体(干法蚀刻)或蚀刻剂(湿法蚀刻)的蚀刻选择率，可以一起蚀刻或者可以不一起蚀刻第一电极173a和173b的分别未被第一绝缘体141a和141b覆盖的将暴露于外部的部分。图9的晶体管阵列面板可以与蚀刻剂的选择率适度高的情况对应，图2的晶体管阵列面板可以与选择率非常高的情况对应。当选择率非常低或不存在或者第三导电层图案170'以及第一电极173a和173b由相同的材料形成时，完全蚀刻第一电极173a和173b的不与第一绝缘体141a和141b叠置的边缘部分，使得第一电极173a和173b的边缘可以与第一绝缘体141a和141b的边缘基本匹配。
这里公开了一种包括具有彼此不同的沟道长度的晶体管的晶体管阵列面板和一种晶体管阵列面板的制造方法。接下来，将参照图10和图11描述包括上述的晶体管阵列面板的显示装置。
图10是包括根据示例性实施例的晶体管阵列面板的显示装置的等效电路图，图11是包括根据示例性实施例的晶体管阵列面板的显示装置的示意性剖视图。
参照图10，示出了有机发光器件的像素电路。显示装置包括信号线121、171和172以及连接到信号线121、171和172并以近似矩阵布置的像素PX。
信号线包括传输栅极信号(称为扫描信号)的栅极线121、传输数据信号的数据线171和传输驱动电压Vdd的驱动电压线172。栅极线121可以近似在行方向上延伸，数据线171和驱动电压线172可以近似在列方向上延伸。
每个像素PX包括开关晶体管Qs、驱动晶体管Qd、存储电容器Cst和作为有机发光二极管的发光器件LD。虽然未示出，但是像素PX还可以包括补偿提供给发光器件LD的电流的晶体管和/或电容器。此外，可以对晶体管Qs和Qd、存储电容器Cst以及发光器件LD的连接关系进行各种改变。
开关晶体管Qs的控制端子(栅电极)、输入端子(第一电极)和输出端子(第二电极)可以分别连接到栅极线121、数据线171和驱动晶体管Qd。开关晶体管Qs可以响应于从栅极线121接收的栅极信号而向驱动晶体管Qd传输从数据线171接收的数据电压。驱动晶体管Qd的控制端子(栅电极)、输入端子(第一电极)和输出端子(第二电极)分别连接到开关晶体管Qs、驱动电压线172和发光器件LD。可以根据驱动晶体管Qd的控制端子和输出端子之间的电压来控制流过驱动晶体管Qd的电流(ILD)。存储电容器Cst可以连接在驱动晶体管Qd的控制端子和输入端子之间。存储电容器Cst充入施加到驱动晶体管Qd的控制端子的数据电压并在开关晶体管Qs截止之后保持数据电压，从而保持发光器件LD的发光状态，直至施加下一数据电压。
发光器件LD具有连接到驱动晶体管Qd的输出端子的阳极和连接到接地电压或共电压Vss的阴极。发光器件LD可以根据驱动晶体管Qd的输出电流(ILD)通过改变光的强度来发光，从而显示图像。
参照图11，提供了图10中示出的发光器件LD连接到图2中示出的晶体管阵列面板的示例。如上所述，作为第一晶体管的驱动晶体管Qd和作为第二晶体管的开关晶体管Qs位于基底110上。具有相对长的沟道长度L1的第一晶体管可以用作驱动晶体管Qd，具有相对短的沟道长度L2的第二晶体管可以用作开关晶体管Qs。
绝缘层(也被称作钝化层)的平坦化层180形成在驱动晶体管Qd和开关晶体管Qs上。平坦化层180去除台阶并使台阶平坦化，并且增大将形成在其上的有机发光元件的发射效率。
像素电极191形成在平坦化层180上。像素电极191通过形成在平坦化层180中的接触孔连接到驱动晶体管Qd的第二电极175a。像素限定层250位于平坦化层180和像素电极191上。像素限定层250具有与像素电极191叠置的开口。像素限定层250可以包括诸如聚丙烯酸物和聚酰亚胺等的树脂或二氧化硅基无机材料。
发射层260位于像素限定层250的开口中的像素电极191上，共电极270位于发射层260上。像素电极191、发射层260和共电极270一起构成发光器件LD的有机发光二极管。像素电极191可以是有机发光二极管的阳极，共电极270可以是有机发光二极管的阴极。保护有机发光二极管的封装膜300可以位于共电极270上。
根据本发明的示例性实施例的晶体管阵列面板可以包括在各种显示装置中。
虽然已经结合目前认为是实际的示例性实施例描述了本发明，但是将理解的是，发明不限于公开的实施例。相反，它意图覆盖包括在权利要求的精神和范围内的各种修改和等同布置。

Claims (11)

1.一种晶体管阵列面板，所述晶体管阵列面板包括：
基底以及位于所述基底上的第一晶体管和第二晶体管，
其中，所述第一晶体管和所述第二晶体管中的每个包括：第一电极；第二电极，与所述第一电极叠置；间隔构件，位于所述第一电极和所述第二电极之间；半导体层，沿所述间隔构件的侧壁延伸；以及栅电极，与所述半导体层叠置，
其中，所述第一晶体管的所述间隔构件的厚度大于所述第二晶体管的所述间隔构件的厚度，
其中，所述第一晶体管的所述间隔构件包括第一绝缘体、第二绝缘体以及位于所述第一绝缘体和所述第二绝缘体之间的浮置电极。
2.根据权利要求1所述的晶体管阵列面板，其中：
所述第二晶体管的所述间隔构件包括第一绝缘体。
3.根据权利要求2所述的晶体管阵列面板，其中：
所述第一晶体管的所述第一绝缘体与所述第二晶体管的所述第一绝缘体位于同一层处；并且
所述第一晶体管的所述浮置电极与所述第二晶体管的所述第二电极位于同一层处。
4.根据权利要求2所述的晶体管阵列面板，其中：
所述第一晶体管的所述半导体层与所述第二晶体管的所述半导体层位于同一层处。
5.根据权利要求1所述的晶体管阵列面板，其中：
所述第一晶体管的所述半导体层包括在平行于所述基底的平面表面的方向上分别与所述第一晶体管的所述第一电极和所述第二电极叠置的第一部分和第二部分以及位于所述第一晶体管的所述第一部分和所述第二部分之间的沟道区；
所述第二晶体管的所述半导体层包括在平行于所述基底的所述平面表面的所述方向上分别与所述第二晶体管的所述第一电极和所述第二电极叠置的第一部分和第二部分以及位于所述第二晶体管的所述第一部分和所述第二部分之间的沟道区；并且
所述第一晶体管的所述沟道区的长度大于所述第二晶体管的所述沟道区的长度。
6.根据权利要求5所述的晶体管阵列面板，其中：
所述第一晶体管的所述第一电极与所述第二电极之间的间隔大于所述第二晶体管的所述第一电极与所述第二电极之间的间隔。
7.根据权利要求1所述的晶体管阵列面板，所述晶体管阵列面板还包括：
缓冲层，位于所述基底与所述第一晶体管和所述第二晶体管之间，并且
所述缓冲层包括与所述第一晶体管和所述第二晶体管的所述第一电极叠置并且具有第一厚度的第一区域以及不与所述第一晶体管和所述第二晶体管的所述第一电极叠置并且具有小于所述第一厚度的第二厚度的第二区域。
8.根据权利要求2所述的晶体管阵列面板，其中：
所述第一晶体管的所述第一绝缘体、所述浮置电极、所述第二绝缘体和所述第二电极具有相同的平面形状，所述第一晶体管的所述浮置电极、所述第二绝缘体和所述第二电极的边缘匹配。
9.根据权利要求2所述的晶体管阵列面板，其中：
所述第一晶体管的所述半导体层、栅极绝缘层和所述栅电极具有相同的平面形状，所述第一晶体管的所述半导体层、所述栅极绝缘层和所述栅电极的边缘匹配，并且
所述第二晶体管的所述半导体层、栅极绝缘层和所述栅电极具有相同的平面形状，所述第二晶体管的所述半导体层、所述栅极绝缘层和所述栅电极的边缘匹配。
10.根据权利要求2所述的晶体管阵列面板，其中：
所述第一晶体管的所述浮置电极的边缘位于所述第一晶体管的所述第一绝缘体的边缘内部；并且
所述第二晶体管的所述第二电极的边缘位于所述第二晶体管的所述第一绝缘体的边缘内部。
11.根据权利要求1所述的晶体管阵列面板，所述晶体管阵列面板还包括：
像素电极，连接到所述第一晶体管的所述第二电极。
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