CN108292609A - 具有含多层组装垫的引线框的半导体封装 - Google Patents

具有含多层组装垫的引线框的半导体封装 Download PDF

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CN108292609A
CN108292609A CN201680065353.7A CN201680065353A CN108292609A CN 108292609 A CN108292609 A CN 108292609A CN 201680065353 A CN201680065353 A CN 201680065353A CN 108292609 A CN108292609 A CN 108292609A
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pad
layer
frame
lead
metal
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CN108292609B (zh
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张家韵
侯志谦
史蒂文·苏
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Texas Instruments Inc
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Abstract

在所描述的实例中，一种引线框(100)包含：片状金属框(101)，其在第一平面层中，其中所述框(101)具有金属引线(110)及从所述框(101)向内延伸的第一金属垫(120)，且所述第一金属垫(120)由第一金属带(120a)系结到所述框(101)。所述引线框(100)进一步具有：第二金属垫(130)，其在平行于所述第一平面层且与所述第一平面层间隔开的第二平面层中，其中所述第二金属垫(130)由第二金属带(132)系结到所述框(101)。而且，所述引线框(100)具有：第三金属垫(140)，其在平行于所述第二平面层且与所述第二平面层间隔开并且从所述第一平面层附加的第三平面层中，其中所述第三金属垫(140)由第三金属带(131)系结到所述第二金属垫(130)。

Description

具有含多层组装垫的引线框的半导体封装
本发明大体上涉及半导体装置及过程，且更特定来说，涉及引线框结构及引线框制造方法，所述引线框具有位于一个以上层处的组装垫。
背景技术
用于半导体装置的金属引线框提供组装垫作为用于牢固地定位半导体芯片的稳定支撑件，且进一步提供用于使电导体极其靠近芯片的大量引线。引线的尖端与芯片端子之间的剩余间隙通常由细线(通常是直径约25μm的铜或金)桥接。
出于制造容易性及降低成本的原因，单件式引线框通常由例如铜(厚度范围通常是120到250μm)的平坦薄金属片制造。引线框的所期望形状从原始平坦片蚀刻或冲压而成。出于多数目的，典型引线的长度可大大长于其宽度。
出于线接合的技术原因，通常需要将芯片安装垫定位在引线的起始平面下端约10到20μm的水平平面中。在一些装置中，高度差可能更大。因此，连接芯片安装垫与框的那些带必须弯曲以克服两个平行平面之间所需的高度差。
耗散高功率或用于高频电信中的半导体装置通常需要封装以使得所述封装允许引线框暴露封装的底表面处的芯片组装垫以便促进垫到外部散热器的直接附接。在这些装置中，芯片安装垫的水平平面与引线的水平平面之间的距离(以与平面成直角沿着线所测量)显著增大。在具有约1.0mm的最终厚度的封装中，所述距离可在400与500μm之间。如果所述距离由带以30°或更小的倾斜角桥接，那么此挑战通常可通过伸长同时保持在材料特性限制内(例如对于铜，小于约8％)来满足。
发明内容
在所描述的实例中，一种引线框包含：框及多个引线，其在第一水平平面中；第一芯片安装件，其在第二水平平面中；第二芯片安装垫，其在第三水平平面中；以及多个带，其连接所述芯片安装垫与所述框。所述带具有几何结构，其经设计以使得所述带可基于固有材料特性适应形成过程中超过简单伸长限制的弯曲及伸展。所述芯片安装垫中的至少一个芯片安装垫延伸到囊封塑料封装且延伸穿过所述囊封塑料封装。
附图说明
图1展示根据一实施例的引线框的透视俯视图，其中半导体芯片附接到多个平面层处的垫。
图2说明图1的引线框的透视仰视图，其中半导体芯片附接到多个平面层处的垫。
图3显示根据另一实施例的引线框的透视俯视图，其中半导体芯片附接到多个平面层处的垫。
图4描绘图3的引线框的透视仰视图，其中半导体芯片附接到多个平面层处的垫。
具体实施方式
对于具有囊封于标准厚度封装(>1.0mm)中的芯片的许多装置系列，电子设备及应用的市场需要如下装置，其中封装暴露芯片组装垫以进行有效热耗散，甚至对于大芯片区及(有时)多芯片组合件也是如此。而且，封装应具有小占用面积。为了暴露厚度大于约1.0mm的封装中的芯片安装垫，芯片安装垫的水平平面与引线的水平平面之间的直线距离增大高达超过“薄”封装中的相应距离的260％(在1100到1200μm的范围内)。由于标准厚度封装，可能需要大于8％的铜带伸长，其超过了铜引线框材料的弹性限制且将导致片段破裂及断开。
当必须以比30°陡峭(例如45°)的角度桥接芯片垫与引线的平面之间的直线距离时，在封装中出现类似困难。通常，此陡峭的角度是期望缩减封装的轮廓(即，当安装在印刷线路板上时其消耗的面积)或在固定封装中容纳额外大芯片垫的结果。此处，再次，可能需要大于8％的铜带伸长，其超过了铜引线框材料的弹性限制。
为了解决占用面积问题，实例实施例使用一种方法，其将组装垫分布在一个以上层上且因此拓宽了三维引线框的概念。
图1以俯视图说明实例实施例，整体以100标示引线框。在图2中将相同实施例展示为仰视图。在图3中以俯视图将引线框300说明为另一实例实施例，且在图4中以仰视图将引线框300说明为另一实例实施例。引线框100及300同时满足半导体装置及其操作的若干需求。
引线框100包括若干部分；一个部分是框101，其由平坦片状金属制成。框101位于其中的平面层或平面在本文中称为第一平面层；框101在二维中操作。相应地，引线框300包括若干部分；一个部分是第一平面层中的框301。为了以大批量生产制造引线框，首先从原始平坦薄金属片冲压或蚀刻出框、垫、引线及支撑结构的完整图案；实例厚度在约0.25与0.15mm之间。第一平面层是起始金属片的平面。起始材料包含(但不限于)铜、铜合金、铝、铁镍合金及KovarTM。
参考图1及2，框101具有多个引线110及从框向内延伸的第一组装垫120；引线110及垫120与框101在相同的第一平面层或平面中。第一垫120由第一带120a附接到框101。基于制造过程，引线110及第一垫120由与框101相同的金属制成。第一垫120可适于组装半导体芯片121或无源电子组件。然而，其它实施例可具有一个以上组装垫。其它装置可能不具有第一平面层中的组装垫120。组装垫120的功能是提供稳定支撑件以用于牢固地定位一或多个半导体芯片或无源电子组件。因为包含垫的引线框由导电材料制成，所以垫可在需要时偏置到涉及半导体装置的网络所需的任何电势，尤其是接地电势。
参考图3及4，框301类似地具有多个引线310及从所述框向内延伸的第一组装垫320；引线310及垫320在与框301相同的第一平面层或平面中，且由与框301相同的金属制成。第一垫320由第一带320a附接到框301。第一垫320可操作以组装且在此之后支撑半导体芯片321或无源电子组件。然而，其它实施例可具有一个以上组装垫。其它装置可能不具有第一平面层中的组装垫320。
多个导电引线110及310的功能是使多个电线极其靠近芯片。引线的尖端与芯片的端子之间的剩余间隙通常由个别地接合到芯片端子以及引线110及310的细线桥接。在图1中，一些接合线被展示为球及针脚接合连接，且被标示为150。
如图1及2所指示，实例实施例100进一步包含：第二金属垫130，其在第二平面层中，所述第二平面层平行于第一层而又与其间隔开一定距离。类似地，在图3及4中，实施例300包含：第二金属垫330，其在第二平面层中，所述第二平面层平行于第一杠杆而又与其间隔开一定距离。应该提到的是，在本文中，第一层的平面与第二层的平面之间的距离应沿着垂直于两个平面的轴线来考虑。在图1中，第二垫130经设定大小以为芯片131提供支撑，且由第二带132连接到引线框100的引线111以便实现接入到如由引线111提供的所附接芯片131或无源组件的离散输入/输出偏置。在带131的帮助下，此离散偏置可进一步转移到第三垫140。
相比而言，在图3中，第二垫330经设计单独作为第二平面层处的带332的支撑垫；带332附接到输入/输出引线311。垫330又由带331连接到第三垫340；因此，第三垫340可在引线311的电势下偏置。引入中间支撑层330的优点是在无层330的情况下，带332必须被设计得极度长以将第三垫340连接到引线311。在制造过程中难以处理极度长的带。或者，如同带332的带可以某一配置设计，其适于基于固有材料特性适应超过简单伸长限制的弯曲及伸展。此类配置可选自包含弯曲几何结构、弧形几何结构及环形几何结构的群组。
如由图1及2中的实施例展示，内部框101是第三平面层处的第三金属垫140，所述第三平面层平行于第二层且与第二层间隔开。因为层之间的距离是相加的，所以第三层比第二层距第一层更远。优选地，第三垫140目前从框101的第一层移除，使得底表面140a从未来装置封装160暴露且因此可在具有在冶金学上能够直接焊接附接到板或散热器的可焊接表面时使用。第三垫140可经设定大小以为多个半导体芯片或无源组件中的一个提供支撑。在图1及2的实例实施例中，两个芯片141及142的垂直堆叠附接在第三垫140上，从而利用垫140相对于框的原始第一层的深下端。
类似地，图3及4中描绘的实施例显示第三平面层处的第三金属垫340，所述第三平面层平行于第二层且与第二层间隔开，其容纳垫320。因为层之间的距离是附加的，所以第三层比第二层距第一层更远。优选地，第三垫340目前从框301的第一层移除，使得底表面340a从未来装置封装暴露且因此可在具有在冶金学上能够直接焊接附接到板或散热器的可焊接表面时使用。第三垫340可经设定大小以为多个半导体芯片或无源组件中的一个提供支撑。在图3的实例实施例中，两个芯片341及342的垂直堆叠附接在第三垫340上，从而利用垫340相对于框的原始第一层的深下端。而且，垫340具有附加物343，其扩大可用于组装芯片或无源组件344的第三垫的面积。
为了以大批量生产制造如同100及300的引线框，首先从原始平坦薄金属片冲压或蚀刻出芯片垫、引线及支撑结构的完整图案。起始片状金属的厚度优选地在约0.25与0.15mm之间。起始材料包含(但不限于)铜、铜合金、铝、铁镍合金及KovarTM。在冲压或蚀刻过程中，引线框的个别引线及带采取薄金属带的形式，其中其特定几何形状由设计确定。出于多数目的，实例引线及带的长度大大长于其宽度。
接着，引线框的主要部分被夹持在一个水平平面中，同时外力被施加到芯片垫以便将其按压到其新的水平平面中。支撑芯片垫的带必须通过伸展吸收此力；其被“按压”成其最终几何形状。
沿着带的长度施加的外力可使带在长度方向上伸展，同时宽度的尺寸仅被稍微减小，使得新的形状呈现为伸长。对于比长度小且高达一定限制(称为由材料特性给定的弹性限制)的伸长，伸长量与力成线性比例。超过那个弹性限制，带的内部强度经受不可逆变化。
如图2及4中的透视图说明，带(例如131、132及332)的长度在引证的弹性伸长范围内(原始带长度的大约7到8％)。如果需要比此弹性限制更多的伸长，那么所需伸长可通过使设计弯曲线性化来获得。线性化的贡献量可在拓扑学上长的主体首先被设计且冲压以使得其含有弧形、弯曲、曲折或类似非线性时获得。实例是选自包含弯曲几何结构、弧形几何结构及环形几何结构的群组的配置。通过施加力，至少部分非线性经伸展或拉直以使得此后主体伸长。
在图4中由标示为335的带指示设计弯曲的线性化的实例。带335原始地具有由虚线轮廓335a指示的弧形形状。
另一实施例是半导体装置，例如在图1及2中说明。所述装置包含引线框100、半导体芯片121、131、141及142以及封装160。如上文论述，引线框100包括第一平面层中的片状金属框101，其中所述框具有金属垫110及从所述框向内延伸的第一金属垫120；所述第一垫由第一金属带120a系结到所述框。此外，所述引线框包含第二平面层中的第二金属垫130，所述第二平面层平行于第一层且与第一层间隔开；第二垫130可由第二金属带系结到所述框。第三金属垫140在平行于第二层且与第二层间隔开并且从第一层附加的第三平面层中；第三垫140由第三金属带131系结到第二垫。优选地，背对第一垫的第三垫表面140a是可焊接的。举例来说，当垫140由铜制成时，表面140a可包含锡层或可具有由镍、钯及(任选地)金制成的一系列薄层。
半导体芯片的端子在组合件囊封于封装160中之前连接到相应引线。为了清楚的目的，图1及2将封装展示为由透明材料制成且以虚线轮廓展示。优选地，封装由环氧基化合物制成，其是不透明的且囊封芯片及接合线、引线、第一垫及第二垫以及第三垫的部分，同时其使可焊接第三垫表面140a未囊封且因此暴露到环境。
在完成囊封过程之后，经封装单元经受削整及形成过程步骤。在削整过程中，框101经移除以使得个别引线110被释放。在形成过程中，离散引线110可弯曲或以其它方式形成以获得所期望轮廓，以使得完工的经封装装置可被插入到板中或附接到板。
实例实施例适用于使用任何类型半导体芯片、离散或集成电路的产品。半导体芯片的材料可包括硅、硅锗、砷化镓、氮化镓或用于集成电路制造中的任何其它半导体或化合物材料。
作为另一实例，实例实施例适用于具有通过附接及电连接组装在引线框上的一或多个半导体芯片的装置。
作为又一实例，实例实施例适用于具有用于以各种度数容纳芯片的垫平面层的引线框。在一些装置中，所有层的垫可由芯片填充。在其它装置中，仅一个层(或几个层)的垫可被如此填充。在一些装置中，垫可具有所组装的一个以上芯片。在其它装置中，可不填充一个以上垫。
修改在所描述的实施例中是可能的，且其它实施例在权利要求书的范围内是可能的。

Claims (9)

1.一种引线框，其包括：
片状金属框，其在第一平面层中，所述框具有金属引线及从所述框向内延伸的第一金属垫，所述第一垫由第一金属带系结到所述框；
第二金属垫，其在平行于所述第一层且与所述第一层间隔开的第二平面层中，所述第二垫由第二金属带系结到所述框；及
第三金属垫，其在平行于所述第二层且与所述第二层间隔开并且从所述第一层附加的第三平面层中，所述第三垫由第三金属带系结到所述第二垫。
2.根据权利要求1所述的引线框，其中所述第二垫进一步由第二带系结到一或多个引线。
3.根据权利要求1所述的引线框，其中所述第三垫进一步由第三带系结到所述框。
4.根据权利要求1所述的引线框，其中所述第三垫进一步由第三带系结到一或多个引线。
5.根据权利要求1所述的引线框，其进一步包含所述第一带及所述第二带的配置，其适于基于固有金属特性适应超过简单伸长限制的弯曲及伸展。
6.根据权利要求5所述的引线框，其中所述配置选自包含弯曲几何结构、弧形几何结构及环形几何结构的群组。
7.根据权利要求1所述的引线框，其中所述第一层、所述第二层及所述第三层中的一或多个垫适于用作用于半导体芯片或无源电子组件的安装垫。
8.根据权利要求1所述的引线框，其中背对所述第一垫的第三垫表面是可焊接的。
9.一种半导体装置，其包括：
引线框，其包含：
片状金属框，其在第一平面层中，所述框具有金属引线及从所述框向内延伸的第一金属垫，所述第一垫由第一金属带系结到所述框；
第二金属垫，其在平行于所述第一层且与所述第一层间隔开的第二平面层中，所述第二垫由第二金属带系结到所述框；及
第三金属垫，其在平行于所述第二层且与所述第二层间隔开并且从所述第一层附加的第三平面层中，所述第三垫由第三金属带系结到所述第二垫，背对所述第一垫的第三垫表面是可焊接的；
至少一个半导体芯片，其附接到所述垫中的至少一个且连接到邻近引线；以及
封装，其囊封所述至少一个芯片、所述引线、所述第一垫及所述第二垫以及所述第三垫的部分，同时使所述可焊接第三垫表面未囊封且暴露于环境。
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Publication number Priority date Publication date Assignee Title
US9922908B2 (en) * 2015-12-18 2018-03-20 Texas Instruments Incorporated Semiconductor package having a leadframe with multi-level assembly pads
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1322377A (zh) * 1999-08-24 2001-11-14 通用半导体公司 用于制造混合式半导体器件的引线框架
US20090278248A1 (en) * 2008-05-09 2009-11-12 Kazuhiko Matsumura Semiconductor device and method of fabrication
US7790500B2 (en) * 2002-04-29 2010-09-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20130249051A1 (en) * 2012-03-23 2013-09-26 Texas Instruments Incorporated Packaged Semiconductor Device Having Multilevel Leadframes Configured as Modules

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100490140C (zh) * 2003-07-15 2009-05-20 飞思卡尔半导体公司 双规引线框
US7169651B2 (en) * 2004-08-11 2007-01-30 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages
US20140210062A1 (en) 2013-01-28 2014-07-31 Texas Instruments Incorporated Leadframe-Based Semiconductor Package Having Terminals on Top and Bottom Surfaces
US9134193B2 (en) * 2013-12-06 2015-09-15 Freescale Semiconductor, Inc. Stacked die sensor package
US9236331B2 (en) * 2014-02-25 2016-01-12 Freescale Semiconductor, Inc. Multiple die lead frame
US9922908B2 (en) * 2015-12-18 2018-03-20 Texas Instruments Incorporated Semiconductor package having a leadframe with multi-level assembly pads

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1322377A (zh) * 1999-08-24 2001-11-14 通用半导体公司 用于制造混合式半导体器件的引线框架
US7790500B2 (en) * 2002-04-29 2010-09-07 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20090278248A1 (en) * 2008-05-09 2009-11-12 Kazuhiko Matsumura Semiconductor device and method of fabrication
US20130249051A1 (en) * 2012-03-23 2013-09-26 Texas Instruments Incorporated Packaged Semiconductor Device Having Multilevel Leadframes Configured as Modules
CN104221145A (zh) * 2012-03-23 2014-12-17 德克萨斯仪器股份有限公司 具有配置为模块的多级引线框的封装半导体器件

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