CN108242407A - Package substrate, encapsulating structure and preparation method thereof - Google Patents
Package substrate, encapsulating structure and preparation method thereof Download PDFInfo
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- CN108242407A CN108242407A CN201611202972.4A CN201611202972A CN108242407A CN 108242407 A CN108242407 A CN 108242407A CN 201611202972 A CN201611202972 A CN 201611202972A CN 108242407 A CN108242407 A CN 108242407A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1712—Layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A kind of encapsulating structure, the encapsulating structure include a package substrate and an at least chip, which is embedded into the first conductive circuit layer in the dielectric layer including a dielectric layer and one, which further includes at least two electrical contact pads；The package substrate further includes at least two metal columns, and at least two metal columns are formed at least two electrical contact pads, and at least one chip is electrically connected at least two metal columns.The invention further relates to a kind of package substrate and a kind of production methods of encapsulating structure.
Description
Technical field
The present invention relates to encapsulation technologies more particularly to a kind of package substrate, encapsulating structure and preparation method thereof.
Background technology
Now, electronic product just flourishes towards the direction of high integration, miniaturization, micromation.Print package substrate
Or semiconductor integrated circuit package substrate is meeting the good electricity of electronic product, under the premise of hot property, also towards it is light, thin, short,
Small designer trends development.And with the development of this trend, interconnection density of the electronic product on design level is continuously increased.
In other words, it in more and more limited surface area, needs to design more input/output signal circuits.In addition, due to member
Device operates under high speed signal circuit, and therefore, the performance of component also will be improved accordingly.
Based on the demand, it is developed flip chip flips interconnection techniques and wire bonding encapsulation connection skills
Art.But in encapsulation process, flip chip flips interconnection techniques and wire bonding encapsulation interconnection technique are also easily produced
Raw following problem：
1.flip chip flip interconnection techniques：The combination of the tin ball of flip chip chips and the electrical contact pad for support plate of sunkening cord
Surface area is too small so that the binding force between the electrical contact pad of flip chip chips and support plate of sunkening cord declines, and is susceptible to plate face
Damage or chip obscission.
2.wire bonding encapsulate interconnection technique：Wire bonding chips connect wire bonding by metal wire
Chip and support plate of sunkening cord since finger of sunkening cord is less than the surface of dielectric layer, be easy to cause routing porcelain mouth and hit to dielectric layer edge,
There is the phenomenon that routing is bad.
Invention content
In view of this, the present invention provides a kind of package substrate that can be solved the above problems, encapsulating structure and its making side
Method.
A kind of production method of encapsulating structure, includes the following steps：A loading plate is provided, which includes a core board
And one be formed in the first copper foil layer on one surface of core board；The shape on the surface far from the core board of first copper foil layer
Into first conductive circuit layer, which includes at least two electrical contact pads；And in first conductive circuit layer
Far from the loading plate surface formed a dielectric layer so that first conductive circuit layer is embedded into the dielectric layer；Removal should
Core board and first copper foil layer；Plating forms at least two metal columns at least two electrical contact pads；And it provides at least
At least one chip is electrically connected at least two metal columns by one chip by flip or routing technology.
A kind of encapsulating structure, the encapsulating structure include a package substrate and an at least chip, which includes one and be situated between
Electric layer and one it is embedded into the first conductive circuit layer in the dielectric layer, which further includes at least two electrical contacts
Pad；The package substrate further includes at least two metal columns, and at least two metal columns are formed at least two electrical contact pads,
At least one chip is electrically connected at least two metal columns.
A kind of package substrate, the package substrate are embedded into the first conducting wire in the dielectric layer including a dielectric layer and one
Layer, first conductive circuit layer further include at least two electrical contact pads；The package substrate further includes multiple metal columns, and at least two
The metal column is formed at least two electrical contact pads.
Compared with the prior art, a kind of package substrate provided by the invention, encapsulating structure and preparation method thereof, at least two
Form at least two metal columns on a electrical contact pad, 1) knot between the electrical contact pad of crystal covered chip and support plate of sunkening cord can be increased
With joint efforts, it comes off to avoid plate face damage or chip；At least two metal columns are formed in the electrical contact pad of first conductive circuit layer
On, 2) metal column (finger of sunkening cord) can be made higher than the surface of dielectric layer, it is bad to avoid routing.
Description of the drawings
Fig. 1 is the sectional view for the loading plate that first embodiment of the invention provides.
Fig. 2 is one first photopolymer layer to be formed on the surface of a copper foil layer of the loading plate of Fig. 1 and in first photopolymer layer
Gap forms the sectional view after the first conductive circuit layer.
Fig. 3 is the sectional view after the first photopolymer layer shown in Fig. 2 is removed.
Fig. 4 is that the surface of the first conductive circuit layer shown in Fig. 3 presses the sectional view after a dielectric layer and a copper foil layer.
Fig. 5 is to form a sectional view after the blind hole on dielectric layer shown in Fig. 4 and copper foil layer.
Fig. 6 is that the surface of copper foil layer shown in Fig. 5 forms one second photopolymer layer and formed in the gap of the second photopolymer layer
Sectional view after one second conductive circuit layer.
Fig. 7 is the sectional view after removal the second photopolymer layer shown in fig. 6.
Fig. 8 be remove loading plate shown in Fig. 7 core board and the first copper foil layer and microetch fall the first copper foil shown in Fig. 7
Sectional view after layer and third copper foil layer.
Fig. 9 is that the surface formation one first of the first conductive circuit layer and the second conductive circuit layer shown in Fig. 8 respectively is anti-
Sectional view after layer and the second soldermask layer.
Figure 10 is that the surface of the first soldermask layer shown in Fig. 9 and the second soldermask layer is respectively formed a third, the 4th dry film
Sectional view after layer.
Figure 11 is that plating forms gold on exposed electrical contact pad in the opening from third photopolymer layer shown in Fig. 10
Belong to the sectional view after column.
Figure 12 is the sectional view after the third photopolymer layer peeled off shown in Figure 11.-
Figure 13 is the section view after an at least chip is formed in the copper post shown in Figure 11, and then after one encapsulating structure of formation
Figure.
Figure 14 is the sectional view for one second encapsulating structure that second embodiment of the invention provides.
Main element symbol description
Following specific embodiment will be further illustrated the present invention with reference to above-mentioned attached drawing.
Specific embodiment
For can the present invention is further explained reaches the technological means and effect that predetermined goal of the invention taken, below in conjunction with attached
Fig. 1-13 and better embodiment, to the specific embodiment, structure, feature of flexible encapsulating substrate of the present invention and preparation method thereof
And its effect, detailed description are as follows.
2 are please referred to Fig.1, first embodiment of the invention provides a kind of encapsulating structure 100, which includes an envelope
Fill substrate 20, at least a chip 30 and an adhesive body 50.The chip 30 is formed in by a scolding tin 40 on the package substrate 20, should
Adhesive body 50 coats the chip 30 and the part package substrate 20.
The dielectric layer 21, one that the package substrate 20 includes an insulation is embedded into the first conductive circuit layer in the dielectric layer 21
22nd, one be fitted on the dielectric layer 21 and second conductive circuit layer 23, one opposite with first conductive circuit layer 22 be bonded
The first soldermask layer 25 and one on 22 surface of the first conductive circuit layer is fitted in the second of 23 surface of the second conductive circuit layer
Soldermask layer 26.
In the present embodiment, the material of the dielectric layer 21 is polypropylene (polypropylene, PP).In other embodiment
In, the material of the dielectric layer 21 can also be polyethylene terephthalate (Polyethylene Terephthalate,
PET), polyethylene naphthalate (Polyethylene Naphthalate, PEN), polyimides (polyimide, PI)
Or other resin hard materials.
The dielectric layer 21 includes a first surface 211, which includes a second surface 221, this
Two surfaces 221 are concordant with the first surface 211.
First conductive circuit layer 22 further includes at least two electrical contact pads 222.
Second conductive circuit layer 23 includes an at least weld pad 231.Each weld pad 231 is first for being electrically connected external electrical
Part.
First soldermask layer 25 includes at least two first openings 251, and the electrical contact pad 222 is out of this first opening 251
It exposes.First soldermask layer 25 further includes a third surface 252, and the third surface 252 is far from first conductive circuit layer
22。
Second soldermask layer 26 includes at least one second opening 261, and at least one weld pad 231 is out of this second opening 261
It exposes.
The package substrate 20 further includes at least two metal columns 29, the metal column 29 be formed on the electrical contact pad 222 and
It is exposed out of this first opening 251.The size of the metal column 29 is less than the size of the electrical contact pad 222.The metal column 29
Including one the 4th surface 291, the 4th surface 291 is concordant with the third surface 252.
The metal column 29 is used to increase the contact area between the scolding tin 40 and the metal column 29, and then increase the chip 30
With the binding force between the package substrate 20, to avoid occurring, plate face is damaged or chip comes off.
In the present embodiment, which is copper post.In other embodiments, the material of the metal column 29 is not limited to
Copper, shape are not limited to column, as long as can function as described above.
The package substrate 20 further includes an at least conductive blind hole 24, at least one conductive blind hole 24 electrical connection first conduction
Line layer 22 and second conductive circuit layer 23.
The chip 30 includes one the 5th surface 31, and the 5th surface 31 is towards the metal column 29.Shape on 5th surface 31
Into there is at least two conductive bumps 32, which corresponds with the metal column 29.Each conductive bump 32 passes through
Scolding tin 40 is fixed on each metal column 29.Wherein, which coats the metal column 29 completely.
The adhesive body 40 coats the chip 30.The adhesive body 40 includes one the 6th surface 41.6th surface 41 with this
One soldermask layer 25 is in contact.
- Figure 11 is please referred to Fig.1, first embodiment of the invention also provides a kind of production method of the encapsulating structure 100, packet
It is as follows to include step：
The first step, referring to Fig. 1, providing a loading plate 11.
The loading plate 11 include a core board 111, one be formed in the first copper foil layer 112 on 111 surface of core board and
One is formed in the second copper foil layer 113 on the surface far from the core board 111 of first copper foil layer 112.
In the present embodiment, material with carrying effect of the material of the core board 111 for any insulation.At this
In embodiment, the material of the core board 111 is polyimides (polyimide, PI).In other embodiments, the core board 111
Material can also be polyethylene terephthalate (Polyethylene Terephthalate, PET), poly- naphthalenedicarboxylic acid
Other resin hard materials such as glycol ester (Polyethylene Naphthalate, PEN).
First copper foil layer 112 and second copper foil layer 113 can be chemical plating copper layer, or native copper layer.
In the present embodiment, the thickness of second copper foil layer 113 is less than the thickness of first copper foil layer 112.
Second step please refers to Fig. 2-3, and one the is formed on surface of second copper foil layer 113 far from the core board 111
One conductive circuit layer 22.
Specifically, the production method of first conductive circuit layer 22 includes the following steps：First, referring to Fig. 2, this
A dry film is bonded on the surface far from the core board 111 of two copper foil layers 113, which is made by exposure, developing manufacture process
One first photopolymer layer 12 is formed, and first conductive circuit layer is formed by being vertically electroplated in the gap of first photopolymer layer 12
22；Secondly, referring to Fig. 3, removing first photopolymer layer 12.
In the present embodiment, the thickness of first conductive circuit layer 22 is less than the thickness of first photopolymer layer 12.
Second step, referring to Fig. 4, the surface far from the loading plate 11 in first conductive circuit layer 22 forms a dielectric
Layer 21 simultaneously forms a third copper foil layer 13 on the surface far from first conductive circuit layer 22 of the dielectric layer 21.
Specifically, which is embedded into the dielectric layer 21.
Specifically, which can be chemical plating copper layer, or native copper layer.
In the present embodiment, the thickness of the third copper foil layer 13 is equal to the thickness of second copper foil layer 113.
Third walks, referring to Fig. 5, forming at least one through the third copper foil layer 13 and the conductive blind hole of the dielectric layer 21
24。
Specifically, which is electrically connected the third copper foil layer 13 and first conductive circuit layer 22.
4th step, please refers to Fig. 6-7, and one second conductive circuit layer 23 is formed on the surface of the third copper foil layer 13.
Specifically, the production method of second conductive circuit layer 23 includes the following steps：First, referring to Fig. 6, this
A dry film is bonded on the surface far from the dielectric layer 21 of three copper foil layers 13, which is made into shape by exposure, developing manufacture process
It is vertically electroplated into one second photopolymer layer 14 and in the gap of second photopolymer layer 14；Secondly, referring to Fig. 7, remove this
Two photopolymer layers 14 form second conductive circuit layer 23.
In the present embodiment, the thickness of second conductive circuit layer 23 is less than the thickness of second photopolymer layer 14.
5th step referring to Fig. 8, removing the core board 111 and first copper foil layer 112, and is removed and is somebody's turn to do by microetch
First photopolymer layer, 12 corresponding second copper foil layer 113 and removal and the corresponding third copper foil layer of second photopolymer layer 14
13, it obtains one and sunkens cord support plate 10.
Wherein, the dielectric layer 21, one which includes an insulation is embedded into conductive in first in the dielectric layer 21
Line layer 22, one is fitted in the second conductive circuit layer 23 on the dielectric layer 21 and opposite with first conductive circuit layer 22.
The dielectric layer 21 include a first surface 211, first conductive circuit layer 22 include one or two surfaces 221, the second surface 221 with
The first surface 211 is concordant.First conductive circuit layer 22 further includes at least two electrical contact pads 222.Second conducting wire
Layer 23 includes an at least weld pad 231.
The support plate 10 of sunkening cord further includes an at least conductive blind hole 24, at least one conductive blind hole 24 electrical connection first conduction
Line layer 22 and second conductive circuit layer 23.
6th step, please refers to Fig. 9-11, a copper post 29 is formed on each electrical contact pad 222, and then form the encapsulation
Substrate 20.
Specifically, the production method of the package substrate 20 further includes following steps：
First, referring to Fig. 9, being respectively formed on the surface of first conductive circuit layer 22 and second conductive circuit layer 23
One first soldermask layer 25 and one second soldermask layer 26.First soldermask layer 25 include at least two first opening 251, at least two
The electrical contact pad 222 is exposed out of this first opening 251.First soldermask layer 25 further includes a third surface 252, this
Three surfaces 252 are far from first conductive circuit layer 22.Second soldermask layer 26 includes at least one second opening 261, and at least one should
Weld pad 231 is exposed out of this second opening 261.
Secondly, referring to Fig. 10, being bonded a third respectively on the surface of first soldermask layer 25 and second soldermask layer 26
27 and 1 the 4th photopolymer layer 28 of photopolymer layer.27 covering part of third photopolymer layer, first opening 251.On the third photopolymer layer 27
At least two thirds opening 271 is formed with, each electrical contact pad 222 is exposed out of each three opening 271, each should
The size of third opening 271 is less than the size of each electrical contact pad 222.It is second anti-welding that this is completely covered in 4th photopolymer layer 28
Layer 26.
Again, 1 is please referred to Fig.1, the copper facing in each third opening 271, forms the gold by way of being vertically electroplated
Belong to column 29.Wherein, the thickness of the metal column 29 is equal to the thickness of first soldermask layer 25.
Finally, 2 are please referred to Fig.1, removes 26 and the 4th photopolymer layer 27 of third photopolymer layer, and then form the package substrate
20。
7th step, please refers to Fig.1 3, provides a chip 30 and an adhesive body 50, which is formed in the metal column 29
On, and the adhesive body 50 is caused to coat the chip 30 and the metal column 29, and then form the encapsulating structure 100.
Wherein, which includes one the 5th surface 31, and the 5th surface 31 is towards the metal column 29.5th surface 31
On be formed at least two conductive bumps 32, the metal column 29 corresponds at least two conductive bumps 32 at least two.
Each conductive bump 32 is fixed in by scolding tin 40 on each metal column 29.Wherein, which coats the conductive bump
32 and the metal column 29.The adhesive body 40 includes one the 6th surface 41.6th surface 41 is in contact with first soldermask layer 25.
4 are please referred to Fig.1, second embodiment of the invention provides a kind of encapsulating structure 200, the encapsulating structure 200 and the present invention
The structure for the encapsulating structure 100 that first embodiment provides is similar, and distinctive points are only that：The chip 30 does not include conductive bump
32, which is fixed on first soldermask layer 25, which is electrically connected the metal column 29 by an at least metal wire 60.
Compared with the prior art, a kind of package substrate provided by the invention, encapsulating structure and preparation method thereof, at least two
Form at least two metal columns on a electrical contact pad, 1) knot between the electrical contact pad of crystal covered chip and support plate of sunkening cord can be increased
With joint efforts, it comes off to avoid plate face damage or chip；At least two metal columns are formed in the electrical contact pad of first conductive circuit layer
On, 2) metal column (finger of sunkening cord) can be made higher than the surface of dielectric layer, it is bad to avoid routing.
The above is only the better embodiment of the present invention, the not limitation to the present invention in any form, though
The right present invention has been that better embodiment is disclosed above, is not limited to the present invention, any person skilled in the art,
Without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or are modified to
With the equivalent implementations of variation, as long as be without departing from technical solution of the present invention content, technical spirit according to the present invention to
Any simple modification, equivalent change and modification that upper embodiment is done, in the range of still falling within technical solution of the present invention.
Claims (11)
1. a kind of package substrate, which is embedded into the first conducting wire in the dielectric layer including a dielectric layer and one
Layer, first conductive circuit layer further include at least two electrical contact pads；It is characterized in that, the package substrate further includes at least two
Metal column, at least two metal columns are formed at least two electrical contact pads.
2. package substrate as described in claim 1, which is characterized in that the dielectric layer includes a first surface, first conduction
Line layer includes a second surface, and the second surface is concordant with the first surface.
3. package substrate as described in claim 1, which is characterized in that the size of the metal column is less than the ruler of the electrical contact pad
It is very little.
4. a kind of encapsulating structure, which includes such as claim 1-3 any one of them package substrate and an at least core
Piece, at least one chip are electrically connected at least two metal columns.
5. encapsulating structure as claimed in claim 4, which is characterized in that it is conductive that at least one at least two are formed on the chip
Convex block, at least two conductive bumps and at least two metal columns correspond, and each conductive bump is consolidated by a scolding tin
It is connected on each metal column.
6. encapsulating structure as claimed in claim 5, which is characterized in that the scolding tin coats the metal column completely.
7. encapsulating structure as claimed in claim 4, which is characterized in that the chip is electrically connected the metal by an at least metal wire
Column.
8. encapsulating structure as claimed in claim 4, which is characterized in that the encapsulating structure further includes an adhesive body, the adhesive body
Coat the chip.
9. a kind of production method of encapsulating structure, includes the following steps：
A loading plate is provided, which is formed in the first copper foil layer on one surface of core board including a core board and one；
First conductive circuit layer is formed on the surface far from the core board of first copper foil layer, first conductive circuit layer
Including at least two electrical contact pads；And
A dielectric layer is formed on the surface far from the loading plate of first conductive circuit layer so that first conductive circuit layer is embedding
It is embedded in the dielectric layer；
Remove the core board and first copper foil layer；
Plating forms at least two metal columns at least two electrical contact pads；And
An at least chip is provided, at least one chip is electrically connected to by least two metal columns by flip or routing technology.
10. the production method of encapsulating structure as claimed in claim 9, which is characterized in that form the metal column the step of it
Before, further include step：
One first soldermask layer is formed on the surface of first conductive circuit layer, which opens including at least two first
Mouthful, each electrical contact pad is exposed out of each first opening；
A third photopolymer layer is formed on the surface of first soldermask layer, the third photopolymer layer covering part first opening, this
At least two thirds opening is formed on three photopolymer layers, each electrical contact pad is exposed out of each three opening；
The copper facing in each third opening, forms the metal column by way of being vertically electroplated；And
Remove the third photopolymer layer.
11. the production method of encapsulating structure as claimed in claim 9, which is characterized in that in the step for providing at least chip
While rapid, step is further included：One adhesive body is provided, and the adhesive body is caused to coat the chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611202972.4A CN108242407A (en) | 2016-12-23 | 2016-12-23 | Package substrate, encapsulating structure and preparation method thereof |
| TW106116320A TWI665773B (en) | 2016-12-23 | 2017-05-17 | Package substrate, package structure and method for manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611202972.4A CN108242407A (en) | 2016-12-23 | 2016-12-23 | Package substrate, encapsulating structure and preparation method thereof |
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| CN108242407A true CN108242407A (en) | 2018-07-03 |
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| CN201611202972.4A Pending CN108242407A (en) | 2016-12-23 | 2016-12-23 | Package substrate, encapsulating structure and preparation method thereof |
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| CN (1) | CN108242407A (en) |
| TW (1) | TWI665773B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681358A (en) * | 2012-08-31 | 2014-03-26 | 富葵精密组件(深圳)有限公司 | Chip package substrate and chip package structure and manufacturing methods thereof |
| CN104282618A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104681531A (en) * | 2013-11-27 | 2015-06-03 | 矽品精密工业股份有限公司 | Package substrate and method for fabricating the same |
| CN105990268A (en) * | 2015-01-30 | 2016-10-05 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9508637B2 (en) * | 2014-01-06 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protrusion bump pads for bond-on-trace processing |
| US10002843B2 (en) * | 2015-03-24 | 2018-06-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate structure, semiconductor package and method of manufacturing the same |
-
2016
- 2016-12-23 CN CN201611202972.4A patent/CN108242407A/en active Pending
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2017
- 2017-05-17 TW TW106116320A patent/TWI665773B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681358A (en) * | 2012-08-31 | 2014-03-26 | 富葵精密组件(深圳)有限公司 | Chip package substrate and chip package structure and manufacturing methods thereof |
| CN104282618A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104681531A (en) * | 2013-11-27 | 2015-06-03 | 矽品精密工业股份有限公司 | Package substrate and method for fabricating the same |
| CN105990268A (en) * | 2015-01-30 | 2016-10-05 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201824482A (en) | 2018-07-01 |
| TWI665773B (en) | 2019-07-11 |
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