CN104282618A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
- Publication number
- CN104282618A CN104282618A CN201310277147.0A CN201310277147A CN104282618A CN 104282618 A CN104282618 A CN 104282618A CN 201310277147 A CN201310277147 A CN 201310277147A CN 104282618 A CN104282618 A CN 104282618A
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor device
- formation method
- formation
- seed material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Disclosed is a method for forming a semiconductor device. The method includes the steps that a semiconductor substrate is provided, and a dielectric layer is formed on the semiconductor substrate; a groove or a through hole is formed in the dielectric layer; a barrier layer is formed on the bottom and the side wall of the groove or the through hole; a seed crystal layer is formed on the barrier layer, the seed crystal layer comprises at least two seed crystal material layers, and a degassing technology is executed after each seed crystal material layer is formed; a metal layer used for filling the groove or the through hole is formed on the seed crystal layer. According to the method for forming the semiconductor device, the metal layer does not comprise a cavity, and the performance of the semiconductor device including the metal layer is good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of semiconductor device.
Background technology
Along with the making of integrated circuit develops to very lagre scale integrated circuit (VLSIC) (ULSI), the current densities of its inside is increasing, contained number of elements constantly increases, and makes the surface of wafer that enough area cannot be provided to make required interconnection line (Interconnect).In order to co-operating member reduces rear increased interconnection line demand, the design of the two-layer above multiple layer metal interconnection line utilizing through hole to realize, becomes the method that very large scale integration technology must adopt.
Because the resistivity of copper metal is low, electromigration lifetime is long, utilize process for copper to make metal interconnecting wires, the resistance of metal interconnecting wires can be reduced.In addition, utilize low-k materials or ultralow-k material film as the dielectric layer of metal interconnecting wires, effectively can reduce electric capacity.Therefore, the copper interconnection structure that copper interconnecting line collocation low-k materials is formed becomes interconnection structure combination most popular at present, it effectively can improve the phenomenon of RC delays (Resistive Capacitive delay), improves the integrity problem that electromigration etc. causes.
In existing technique, a kind of formation method of copper interconnecting line comprises:
Bulk semiconductor substrate is provided, and forms the dielectric layer of low k or ultralow-k material film on the semiconductor substrate;
Groove is formed in described dielectric layer;
Carry out cleaning;
Barrier layer and copper seed layer are formed successively on the bottom and sidewall of described groove;
Adopt electroplating technology in described copper seed layer, form the copper metal layer of filling full described groove.
But find when testing formed copper interconnecting line, there is cavity (void) in the copper interconnecting line that existing technique is formed, the contact of copper interconnecting line is poor, easily leaks electricity, and has had a strong impact on the performance of the semiconductor device comprising formed copper interconnecting line.
Similar, when adopting above-mentioned technique to form copper metal plug, also there is identical problem.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device, avoids formed metal level to comprise cavity, improves the performance of the semiconductor device formed.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprising:
Semiconductor substrate is provided, and forms dielectric layer on the semiconductor substrate;
Groove or through hole is formed in described dielectric layer;
Barrier layer is formed on the bottom and sidewall of described groove or through hole;
Described barrier layer forms inculating crystal layer, and described inculating crystal layer comprises at least two-layer seed material layer, after formation every layer of seed material layer, carry out degasification technique;
Described inculating crystal layer is formed the metal level of filling full described groove or through hole.
Optionally, described inculating crystal layer comprises two-layer seed material layer.
Optionally, after formation groove or through hole, and before the described barrier layer of formation, described formation method also comprises: carry out degasification technique.
Optionally, form described barrier layer, form every layer of seed material layer and carry out degasification technique and carry out in same reaction chamber.
Optionally, the temperature of described degasification technique is greater than or equal to 200 DEG C and is less than or equal to 400 DEG C, the time of carrying out degasification technique is greater than or equal to 2min and is less than or equal to 10min, and after carrying out degasification technique, the pressure in described reaction chamber is less than or equal to 20mTorr.
Optionally, form described seed material layer and comprise: first carry out deposition processes, then carry out densification.
Optionally, form groove or through hole in described dielectric layer after, after formation groove or through hole, and before the described barrier layer of formation, described formation method also comprises: carry out cleaning.
Compared with prior art, technical scheme of the present invention has the following advantages:
After being arranged in the dielectric layer in Semiconductor substrate and forming groove or through hole, barrier layer is formed on the bottom and sidewall of described groove or through hole, then on described barrier layer, form the inculating crystal layer comprising at least two-layer seed material layer, and carry out degasification technique after every layer of seed material layer is formed; By carrying out repeatedly degasification technique to the reaction chamber forming seed material layer, water, air and other impurity (polymer, ion etc.) residual in reaction chamber are gradually reduced, copper atom in seed material layer is avoided to be oxidized to cupric oxide, and then the seed crystal surface avoided cupric oxide to be removed when forming metal level and cause is discontinuous, barrier layer is covered by inculating crystal layer completely, and then enable metal level homoepitaxial on inculating crystal layer, prevent from comprising cavity in formed metal level, improve the performance of formed semiconductor device.
Further, the temperature of described degasification technique is greater than or equal to 200 DEG C and is less than or equal to 400 DEG C, the time of carrying out degasification technique is greater than or equal to 2min and is less than or equal to 10min, and after carrying out degasification technique, the pressure in described reaction chamber is less than or equal to 20mTorr.Be greater than or equal to 200 DEG C when temperature in reaction chamber and be less than or equal to 400 DEG C, the water residued in dielectric layer is converted into gaseous state.When carrying out degasification technique to reaction chamber, the water of gaseous state, air and other impurity (polymer, ion etc.) are discharged reaction chamber.Because in reaction chamber after carrying out degasification technique, pressure is less than or equal to 20mTorr, the water of its inner gaseous, air and other impurity (polymer, ion etc.) are less, effectively avoid inculating crystal layer Atom generation oxidation reaction, make the surface of formed inculating crystal layer continuous, and then enable metal level homoepitaxial on inculating crystal layer, prevent from comprising cavity in formed metal level, improve the performance of formed semiconductor device.
Accompanying drawing explanation
Fig. 1 ~ Fig. 5 is the schematic diagram of a formation method embodiment of semiconductor device of the present invention.
Embodiment
The copper interconnecting line that existing technique is formed or copper metal plug comprise cavity to be caused primarily of following reason:
(1) material of dielectric layer is low k or ultralow-k material film, it typically is porous material.When carrying out cleaning, cleaning solution easily residues in described dielectric layer.Formed in copper seed layer process subsequently through a step depositing operation, the water remained when carrying out cleaning and other impurity exist in the whole process forming copper seed layer always, copper atom reacts with the water residued in dielectric layer and the oxygen formed in the reaction chamber of inculating crystal layer, forms cupric oxide.When adopting electroplating technology to form copper metal layer on described inculating crystal layer, in inculating crystal layer, cupric oxide and electroplating solution (form primarily of copper sulphate, sulfuric acid and water, the multiple additives such as catalyst, inhibitor, adjusting agent are also included in described electroplating solution) react and be removed, expose described barrier layer, cause copper seed layer surface discontinuous, copper cannot be grown on barrier layer, in the copper metal layer of follow-up formation, form cavity.
(2) polymer forming groove process residual cannot be removed by cleaning completely, and the part ion (as: chloride ion, fluorine ion etc.) in cleaning solution easily residues in described dielectric layer surface.By wafer transfer box, the semiconductor device being formed with groove or through hole is being transferred to the reaction chamber carrying out inculating crystal layer depositing operation, during to form inculating crystal layer, residual polymer is easily attached on the surface of formed inculating crystal layer, on the inculating crystal layer causing copper to be grown on being covered by polymer, thus form cavity in copper metal layer.And, when copper atom in copper seed layer reacts with oxygen in the water residued in dielectric layer and reaction chamber, residual chloride ion, fluorine ion can as the catalyst of reaction, improve the speed of reaction, make oxidized faster of copper atom on inculating crystal layer, the cupric oxide formed is more, and the area exposing barrier layer when plating forms copper metal layer is larger, to be formed in copper metal layer the more of cavity, the performance of semiconductor device is poorer.
(3) form the interval time longer (being usually greater than 1.5 hours) between inculating crystal layer and formation copper metal layer, the oxygen of copper atom easily in reaction chamber of seed crystal surface is combined, and forms cupric oxide.Because formed cupric oxide is removed in electroplating technology, cause seed crystal surface discontinuous, and then on the barrier layer causing copper to be grown on not covered by inculating crystal layer, there is cavity in the copper metal layer formed, have impact on the performance of formed semiconductor device.And, form inculating crystal layer and interval time of being formed between copper metal layer longer, to form the amount of cupric oxide more, also larger on the impact of formed performance of semiconductor device.
Technical scheme of the present invention is after formation barrier layer, form the seed material layer of multilayer laminated setting over the barrier layer from the bottom to top successively, and after each seed material layer is formed, carry out degasification technique, using the multilayer seed material layer that is positioned on barrier layer jointly as the inculating crystal layer of follow-up formation metal level.All degasification technique is carried out after being formed in every one deck seed material layer, be used in water residual in the reaction chamber forming seed material layer, air and other impurity (polymer, ion etc.) gradually reduce, seed material layer surface is avoided to be covered by polymer, and avoid the oxidized formation cupric oxide of copper atom in formed seed material layer, prevent cupric oxide and electroplating solution from reacting and being removed, make formed seed material layer even compact, and then make barrier layer completely cover by inculating crystal layer exposure, avoid comprising cavity at formed metal level, improve the performance of formed semiconductor device.And, owing to having carried out repeatedly degasification technique to reaction chamber in formation inculating crystal layer process, in reaction chamber, the content of water, polymer and other impurity is extremely low, even if the interval time formed between inculating crystal layer and formation copper metal layer is longer, also the metallic atom in inculating crystal layer can not be made to be oxidized, thus cavity can not to be formed in the metal layer, make the contact of formed metal level and inculating crystal layer better, avoid leaking electricity, improve the performance of the semiconductor device comprising formed metal level.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
It should be noted that, in the present embodiment, only for the formation method of metal interconnecting wires (namely metal level is for metal interconnecting wires), the formation method of semiconductor device of the present invention is described.In other embodiments, described metal level also can be metal plug, and the formation process of its formation process and metal interconnecting wires is similar, does not repeat at this.
With reference to figure 1, provide Semiconductor substrate 200, and form dielectric layer 202 in described Semiconductor substrate 200.
In the present embodiment, the material of described Semiconductor substrate 200 can be monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or can also comprise other semi-conducting material, the present invention does not limit this.
In addition, also device architecture (not shown) can be formed with in described Semiconductor substrate 200.Described device architecture can for the device architecture formed in semiconductor FEOL, such as MOS transistor etc.
In the present embodiment, the material of described dielectric layer 202 is the low-k materials of porous or the ultralow-k material film of porous.
Continue with reference to figure 1, in described dielectric layer 202, form groove 203a.
Concrete, in described dielectric layer 202, form groove 203a can comprise the steps:
Described dielectric layer 202 is formed photoresist layer (not shown), is formed with photoengraving pattern in described photoresist layer, described photoengraving pattern is corresponding with the opening shape of the groove 203a of follow-up formation;
With described photoresist layer for mask, etch described dielectric layer 202, to form groove 203a in described dielectric layer 202;
Remove described photoresist layer.
In the present embodiment, the method etching described dielectric layer 202 can be dry etching.
The gas of described dry etching can be fluoro-gas, chlorine-containing gas, CO and N
2in one or more combination, the present invention does not limit this.
Continue with reference to figure 1, carry out cleaning.
In the present embodiment, the solution of described cleaning is the hydrofluoric acid solution of EKC and dilution.Concrete, first adopt EKC to carry out cleaning, then adopt the hydrofluoric acid solution of dilution to carry out cleaning.Wherein, a kind of alkaline solution of EKC for being provided by E.I.Du Pont Company.
By carrying out described cleaning, forming polymer residual in groove 203a process and ion to remove etching, being beneficial to the formation of subsequent barrier and inculating crystal layer, improve form the performance of semiconductor device.
It should be noted that, because dielectric layer 202 is porous material, when carrying out cleaning, the water in cleaning solution and ion (as: Cl
-, F
-deng) be easily adsorbed on described dielectric layer 202.
Semiconductor structure in Fig. 1 is transferred in the reaction chamber that can form barrier layer and inculating crystal layer, and before formation barrier layer, degasification technique is carried out to described reaction chamber.
In the present embodiment, formation barrier layer and inculating crystal layer carry out in same reaction chamber.The reaction chamber forming barrier layer and inculating crystal layer can be Applied Materials (AMAT) or promise and sends out the barrier layer and inculating crystal layer forming apparatus that system (Novellus) provides.
In the present embodiment, the temperature of described degasification technique is greater than or equal to 200 DEG C and is less than or equal to 400 DEG C, as 200 DEG C, 250 DEG C, 300 DEG C, 350 DEG C, 380 DEG C or 400 DEG C; The time of carrying out degasification technique is greater than or equal to 2min and is less than or equal to 10min, as 2min, 5min, 5.5min, 7min, 9min or 10min; After carrying out degasification technique, the pressure in described reaction chamber is less than or equal to 20mTorr, as 5mTorr, 10mTorr, 15mTorr, 17mTorr or 20mTorr.
By carrying out degasification technique to described reaction chamber, remove the water, air and other impurity (polymer, ion etc.) that residue in reaction chamber and Fig. 1 in semiconductor structure, reduce water, air and other impurity (polymer, the ion etc.) formation process to subsequent barrier and inculating crystal layer and impact.
It should be noted that, by degasification technique, reaction chamber is evacuated to vacuum (in reaction chamber, pressure is 0), can causes damage to semiconductor device if consider, degasification technique only needs to ensure pressure drop in reaction chamber to being less than or equal to 20mTorr.And be attached to that impurity in dielectric layer is more difficult to be removed by degasification technique.Therefore, degasification technique only can reduce the water, air and other impurity (polymer, ion etc.) that residue in reaction chamber and Fig. 1 in semiconductor structure, but cannot remove completely.
With reference to figure 2, on dielectric layer 202 and on the bottom of the 203a of groove described in Fig. 1 and sidewall, form barrier layer 204.
Concrete, the material on described barrier layer 204 can be one in tantalum and tantalum nitride or combination.The method forming described barrier layer 204 can be physical gas-phase deposition.The thickness range on described barrier layer 204 is 50 dust ~ 120 dusts.
In the present embodiment, the material on barrier layer 204 is tantalum and tantalum nitride.Described barrier layer 204 can effectively stop copper atom in follow-up formation inculating crystal layer and metal level to enter in described dielectric layer 202, avoids formed metal interconnecting wires generation electromigration invalidation, improves the performance of formed semiconductor device.
It should be noted that, in the present embodiment, form barrier layer 204 and follow-up formation each layer seed material layer and degasification technique carries out in same reaction chamber, avoid semiconductor structure to be polluted in transfer process, and avoid formed seed material layer to contact with extraneous air and oxidized.Meanwhile, also reduce the step of transfer of semiconductor structure, reduce the cost forming semiconductor device.
Continue with reference to figure 2, described barrier layer 204 forms ground floor seed material layer 206a.
In the present embodiment, the material of described ground floor seed material layer 206a is copper, and the thickness range of described ground floor seed material layer 206a is 150 dust ~ 250 dusts.
Form described ground floor seed material layer 206a to comprise: first carry out deposition processes, then carry out densification.The object of described deposition processes is deposited copper atom on barrier layer 204, the object of described densification be to make to be positioned at copper atom on barrier layer be evenly distributed, fine and close.The method of carrying out deposition processes can be physical gas-phase deposition, and its concrete formation process is well known to those skilled in the art, and does not repeat them here.Described densification is also physical gas-phase deposition.The difference of itself and deposition processes is: when carrying out this physical gas-phase deposition, power is larger, the speed of reactive ion, while formation deposited copper atom, the copper atom deposited is bombarded, and the speed that copper atom is removed in the speed of deposited copper atom and bombardment is close, while not increasing ground floor seed crystal material layer thickness, make ground floor seed material layer on the surface copper atom be evenly distributed, fine and close, thus form the ground floor seed material layer 206a of surface uniform densification and comprise the groove 203b of barrier layer 204 and ground floor seed material layer 206a.
It should be noted that, when carrying out deposition processes, the deposition rate being positioned at groove 203b opening part copper atom is greater than the deposition rate be positioned at copper atom on sidewall and groove 203b surrounding barrier layers 204 bottom groove 203b, copper atom in formed ground floor seed material layer 206a is caused to be piled up at the opening part of groove 203b, final formation projection (Overhang does not mark).By carrying out densification, the projection at groove opening place can also be made progressively to reduce, reducing the formation process of projection to follow-up seed material layer and metal level and impacting, final improve form the performance of semiconductor device.
In other embodiments, the projection at groove opening place can also be removed by densification, avoid the formation process of projection to follow-up seed material layer and metal level to impact.
After formation ground floor seed material layer 206a, degasification technique is carried out to described reaction chamber.The temperature of described degasification technique is greater than or equal to 200 DEG C and is less than or equal to 400 DEG C, the time of carrying out degasification technique is greater than or equal to 2min and is less than or equal to 10min, after carrying out degasification technique, the pressure in described reaction chamber is less than or equal to 20mTorr.Specifically can with reference to degasification technique above.
Be greater than or equal to 200 DEG C due to the temperature in reaction chamber and be less than or equal to 400 DEG C, residuing in water in dielectric layer 202 and be converted into gaseous state.When carrying out degasification technique, other impurity (polymer, ion etc.) residual in the water of gaseous state, air and reaction chamber are discharged reaction chamber together.Because in reaction chamber after carrying out degasification technique, pressure is less than or equal to 20mTorr, the water of its inner gaseous, air and other impurity (polymer, ion etc.) are less, make the copper atom negligible amounts reacted with oxygen and water in ground floor seed material layer 206a, and avoid formed ground floor seed material layer 206a surface cover by polymer, make the surface of formed ground floor seed material layer 206a continuous, be beneficial to the formation of subsequent metal layer, prevent from comprising cavity in formed metal level, improve the performance of formed semiconductor device.
When carrying out degasification technique, if the temperature in reaction chamber is more than or equal to 100 DEG C and be less than 200 DEG C, although residue in water in dielectric layer 202 to be converted into gaseous state, other impurity (polymer, ion etc.) residual in the water of gaseous state, air and reaction chamber can be discharged reaction chamber together, but its speed of discharging reaction chamber is slower, the time of carrying out needed for degasification technique is longer, and the time cost forming semiconductor device is higher.If the temperature in reaction chamber is less than 100 DEG C, water in dielectric layer 202 is stayed to be still liquid state, degasification technique is difficult to aqueous water to discharge reaction chamber, a large amount of water easily makes copper atom in the first seed material layer 206a be oxidized to cupric oxide, the cupric oxide formed easily is removed at subsequent technique, makes the first seed material layer 206a surface discontinuous.If the temperature in reaction chamber is greater than 400 DEG C, too high temperature can cause damage to formed semiconductor device, reduces the rate of finished products of formed semiconductor device.
Because the Thickness Ratio of ground floor seed material layer 206a is thinner, therefore after formation ground floor seed material layer 206a, just degassed process is carried out in time, greatly can improve degassing efficiency, as far as possible other impurity (polymer, ion etc.) residual in the water of gaseous state, air and reaction chamber be discharged reaction chamber together.
With reference to figure 3, described ground floor seed material layer 206a forms second layer seed material layer 206b, define the groove 203c comprising second layer seed material layer 206b simultaneously.
In the present embodiment, the formation method of described second layer seed material layer 206b is identical with the formation method of described ground floor seed material layer 206a, to form the surface uniform of second layer seed material layer 206b fine and close, the quantity being piled up in groove 203c opening part copper atom can also be reduced simultaneously.When forming metal level, avoid because groove 203c A/F is too small that groove that is that cause seals in advance, and then avoid forming cavity in the metal level of follow-up formation, improve the performance of formed semiconductor device.The thickness range of described second layer seed material layer 206b is 150 dust ~ 250 dusts.
In the present embodiment, described ground floor seed material layer 206a and second layer seed material layer 206b is common as the inculating crystal layer for the formation of metal level in semiconductor device.When forming metal level subsequently through electroplating technology, described inculating crystal layer is connected with power cathode as negative electrode.
After second layer seed material layer 206b is formed, degasification technique is carried out to described reaction chamber.The temperature of described degasification technique is greater than or equal to 200 DEG C and is less than or equal to 400 DEG C, the time of carrying out degasification technique is greater than or equal to 2min and is less than or equal to 10min, after carrying out degasification technique, the pressure in described reaction chamber is less than or equal to 20mTorr.Specifically can with reference to degasification technique above.
When temperature in reaction chamber is greater than or equal to 200 DEG C and is less than or equal to 400 DEG C, residue in water in dielectric layer 202 and be converted into gaseous state.By carrying out described degasification technique, the water of gaseous state in reaction chamber, air and other impurity (polymer, ion etc.) is made to discharge reaction chamber together, reduce to form in the second layer seed material layer 206b oxygen and water in copper atom and reaction chamber and react and be oxidized into cupric oxide, and avoid second layer seed material layer 206b surface to be covered by the polymer remained, to form the surface of second layer seed material layer 206b continuous, be beneficial to the formation of subsequent metal layer.
In addition, because in reaction chamber, water, air and other impurity (polymer, ion etc.) are less, even if the interval time formed between inculating crystal layer and follow-up formation metal level is longer, the copper atom of seed crystal surface also can not be oxidized or covered by polymer, to form seed crystal surface continuous, be formed on inculating crystal layer and do not comprise cavity in metal level, form the better performances of semiconductor device.
After formation second layer seed material layer 206b, semiconductor device described in Fig. 3 is transferred in electroplating reaction pond by reaction chamber, to form metal material layer by electroplating technology on described second layer seed material layer 206b.
With reference to figure 4, described second layer seed material layer 206b forms metal material layer 208a, described metal material layer 208a fills groove 203c described in full Fig. 3.
In the present embodiment, the method forming described metal material layer 208a is electroplating technology.
Concrete, semiconductor structure in Fig. 3 is placed in electroplating reaction pond.Electroplating solution, metallic copper anodes and power positive cathode is had in described electroplating reaction pond.Described electroplating solution, primarily of copper sulphate, sulfuric acid and water composition, also includes the multiple additives such as catalyst, inhibitor, adjusting agent in described electroplating solution.The process of described electroplating technology is: described inculating crystal layer connects the negative pole of power supply, described metallic copper anodes connects the positive pole of power supply, the copper atom generation oxidation reaction be positioned in described metallic copper anodes forms metal copper ion, be positioned at the metal copper ion generation reduction reaction near described seed crystal surface, the copper atom generated is deposited on described seed crystal surface, forms metal material layer 208a.
Because seed crystal surface does not form cupric oxide, there is not the barrier layer 204 that cupric oxide and electroplating solution react and cause to expose, to form seed crystal surface continuous, electroplating technology generate copper atom can homoepitaxial on inculating crystal layer, finally make to there is not cavity in formed metal material layer 208a.
With reference to figure 5, chemical mechanical milling tech is carried out to metal material layer 208a, ground floor seed material layer 206a, second layer seed material layer 206b and barrier layer 204 in Fig. 4, to exposing described dielectric layer 202, remaining ground floor seed material layer 206c and second layer seed material layer 206d and defining metal level 208b.
In the present embodiment, described chemical mechanical milling tech is well known to those skilled in the art, and does not repeat them here.The metal level 208b formed is metal interconnecting wires.
In the present embodiment, form inculating crystal layer at twice, and degasification technique is carried out after every one deck seed material layer is formed, thus make the water in the reaction chamber of formation seed material layer, the minimizing gradually of air and other impurity, copper atom in seed material layer is avoided to be oxidized to cupric oxide, and then the seed material layer surface avoided cupric oxide to be removed when forming metal level and cause is discontinuous, and avoid the surface of formed seed material layer discontinuous because being covered by polymer, barrier layer 204 can be covered by inculating crystal layer completely, and then enable metal level homoepitaxial on inculating crystal layer, prevent from comprising cavity in formed metal level 208b, improve the performance of formed semiconductor device.
It should be noted that, in the present embodiment, described inculating crystal layer comprises two-layer seed material layer.
In other embodiments, described inculating crystal layer also comprises two-layer above seed material layer.Equally, degasification technique is carried out after formation every layer of seed material layer, be used in water, air and other impurity residual in the reaction chamber forming seed material layer and carry out repeatedly the minimizing gradually in degasification technique process, copper atom in seed material layer is avoided to be oxidized to cupric oxide, make the surface uniform of every layer of seed material layer fine and close, and then barrier layer is covered completely by seed material layer, with when forming metal level subsequently through electroplating technology, avoid forming cavity in the metal layer.The formation side comprising the semiconductor device of two-layer above seed material layer is similar to the above embodiments, does not repeat at this.
Even if when dielectric layer is non-porous materials, as long as the material of inculating crystal layer and metal level is easily oxidized, still can there is the problem in cavity, therefore in other embodiments, described inculating crystal layer and metal level also can be the metal material that oxidation easily occurs for other; Described dielectric layer also can be non-porous low-k materials or non-porous ultralow-k material film, the present invention is not limited thereto.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. a formation method for semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided, and forms dielectric layer on the semiconductor substrate;
Groove or through hole is formed in described dielectric layer;
Barrier layer is formed on the bottom and sidewall of described groove or through hole;
Described barrier layer forms inculating crystal layer, and described inculating crystal layer comprises at least two-layer seed material layer, after formation every layer of seed material layer, carry out degasification technique;
Described inculating crystal layer is formed the metal level of filling full described groove or through hole.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, described inculating crystal layer comprises two-layer seed material layer.
3. the formation method of semiconductor device as claimed in claim 1, is characterized in that, after formation groove or through hole, and before the described barrier layer of formation, described formation method also comprises: carry out degasification technique.
4. the formation method of the semiconductor device as described in claim 1 or 3, is characterized in that, forms described barrier layer, forms every layer of seed material layer and carry out degasification technique to carry out in same reaction chamber.
5. the formation method of semiconductor device as claimed in claim 4, it is characterized in that, the temperature of described degasification technique is greater than or equal to 200 DEG C and is less than or equal to 400 DEG C, the time of carrying out degasification technique is greater than or equal to 2min and is less than or equal to 10min, after carrying out degasification technique, the pressure in described reaction chamber is less than or equal to 20mTorr.
6. the formation method of semiconductor device as claimed in claim 1, is characterized in that, form described seed material layer and comprise: first carry out deposition processes, then carry out densification.
7. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described inculating crystal layer is copper; The material of described metal level is copper.
8. as right wants the formation method of the semiconductor device as described in 7, it is characterized in that, the method forming described metal level is electroplating technology.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, after formation groove or through hole, and before the described barrier layer of formation, described formation method also comprises: carry out cleaning.
10. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described dielectric layer is the low-k materials of porous or the ultralow-k material film of porous.
The formation method of 11. semiconductor device as claimed in claim 1, is characterized in that, the material on described barrier layer is one in tantalum and tantalum nitride or combination, and the thickness range on described barrier layer is 50 dust ~ 120 dusts.
The formation method of 12. semiconductor device as claimed in claim 1, is characterized in that, the thickness range of described seed material layer is 150 dust ~ 250 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310277147.0A CN104282618A (en) | 2013-07-03 | 2013-07-03 | Method for forming semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310277147.0A CN104282618A (en) | 2013-07-03 | 2013-07-03 | Method for forming semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104282618A true CN104282618A (en) | 2015-01-14 |
Family
ID=52257385
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310277147.0A Pending CN104282618A (en) | 2013-07-03 | 2013-07-03 | Method for forming semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104282618A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990216A (en) * | 2015-01-29 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
| CN108242407A (en) * | 2016-12-23 | 2018-07-03 | 碁鼎科技秦皇岛有限公司 | Package substrate, encapsulating structure and preparation method thereof |
| CN110752183A (en) * | 2019-10-31 | 2020-02-04 | 上海华力集成电路制造有限公司 | Forming method of contact hole structure and contact hole structure |
| CN111029299A (en) * | 2019-12-18 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Method for forming metal interconnection structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6998337B1 (en) * | 2003-12-08 | 2006-02-14 | Advanced Micro Devices, Inc. | Thermal annealing for Cu seed layer enhancement |
| CN101764084A (en) * | 2008-12-24 | 2010-06-30 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for preparing copper barrier layer-seed crystal layer film |
| CN102790009A (en) * | 2011-05-16 | 2012-11-21 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing fringe effect in copper plating process and manufacturing method of copper interconnection structure |
-
2013
- 2013-07-03 CN CN201310277147.0A patent/CN104282618A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6998337B1 (en) * | 2003-12-08 | 2006-02-14 | Advanced Micro Devices, Inc. | Thermal annealing for Cu seed layer enhancement |
| CN101764084A (en) * | 2008-12-24 | 2010-06-30 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for preparing copper barrier layer-seed crystal layer film |
| CN102790009A (en) * | 2011-05-16 | 2012-11-21 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing fringe effect in copper plating process and manufacturing method of copper interconnection structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105990216A (en) * | 2015-01-29 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Formation method of interconnection structure |
| CN108242407A (en) * | 2016-12-23 | 2018-07-03 | 碁鼎科技秦皇岛有限公司 | Package substrate, encapsulating structure and preparation method thereof |
| CN110752183A (en) * | 2019-10-31 | 2020-02-04 | 上海华力集成电路制造有限公司 | Forming method of contact hole structure and contact hole structure |
| CN111029299A (en) * | 2019-12-18 | 2020-04-17 | 华虹半导体(无锡)有限公司 | Method for forming metal interconnection structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100541718C (en) | Form the method for fine pattern of semiconductor device and form the method for contact with it | |
| CN105575887B (en) | The forming method of interconnection structure | |
| US11164780B2 (en) | Process integration approach for selective metal via fill | |
| CN104282618A (en) | Method for forming semiconductor device | |
| CN104253081A (en) | A formation method of a semiconductor device | |
| CN100449731C (en) | Method for forming double mosaic structure | |
| KR20040055596A (en) | Semiconductor device and manufacturing method for the same | |
| CN102130036B (en) | Method for producing shallow trench isolating structure | |
| CN112885773A (en) | Semiconductor structure and manufacturing method thereof | |
| KR102118580B1 (en) | Chemical vapor deposition (cvd) of ruthenium films and applications for same | |
| CN101123214B (en) | Making method for dual enchasing structure | |
| CN103515292B (en) | The formation method of semiconductor structure | |
| CN101996929B (en) | Forming method of dual-damascene structure and semiconductor structure | |
| CN101414577A (en) | Method for manufacturing semiconductor device | |
| CN104979275A (en) | Formation method of contact plug | |
| CN104022068A (en) | Semiconductor structure and forming method thereof | |
| CN100499070C (en) | Making method for dual enchasing structure | |
| CN102024790A (en) | Semiconductor device for interconnection process and manufacturing method thereof | |
| JP4948278B2 (en) | Manufacturing method of semiconductor device | |
| EP1320128B1 (en) | Method for making interconnect structures | |
| KR100752189B1 (en) | Method of fabricating semiconductor device | |
| CN112435923B (en) | Etching process method for multi-product mixed production | |
| US8420544B2 (en) | Method for fabricating interconnection structure with dry-cleaning process | |
| KR100201721B1 (en) | A method for manufacturing a semiconductor device | |
| CN114695252A (en) | Method for forming metal layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150114 |
|
| RJ01 | Rejection of invention patent application after publication |