CN111029299A - Method for forming metal interconnection structure - Google Patents
Method for forming metal interconnection structure Download PDFInfo
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- CN111029299A CN111029299A CN201911308057.7A CN201911308057A CN111029299A CN 111029299 A CN111029299 A CN 111029299A CN 201911308057 A CN201911308057 A CN 201911308057A CN 111029299 A CN111029299 A CN 111029299A
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- copper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
The application discloses a forming method of a metal interconnection structure, which comprises the following steps: degassing and copper reduction are carried out on the wafer, a dielectric layer is formed on the wafer, a through hole is formed in the dielectric layer, the degassing and the copper reduction are carried out in the same cavity, and the copper reduction reaction is promoted by heating in the copper reduction process; depositing a first barrier layer on the side wall of the through hole; depositing a second barrier layer on the surfaces of the first barrier layer and the dielectric layer; depositing copper seed crystals on the surface of the second barrier layer; and forming a copper metal layer on the surface of the copper seed crystal, wherein the copper metal layer fills the through hole. This application is through in metal interconnect's formation process, go on degasification and copper reduction in same cavity, and promotes copper reduction reaction through the heating in the copper reduction process, has improved the efficiency that the copper was reduced to can improve the clearance of the copper oxide that the wafer surface produced, reduce the contact resistance of device to a certain extent.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for forming a metal interconnection structure in a back-end process of semiconductor manufacturing.
Background
As the Critical Dimension (CD) of semiconductor devices decreases, the back end of Line (BOEL) is becoming a Critical layer affecting semiconductor fabrication. As the semiconductor manufacturing process goes below 28 nm, the back-end process contributes more than 80% to the manufacturing yield, and the key factors affecting the back-end process yield include Resistance (R) and capacitance (C). In view of this, the improvement proposed in the Continuous Improvement Program (CIP) of the semiconductor manufacturing industry is directed to lower resistance and lower parasitic capacitance.
The forming method of the metal interconnection structure proposed in the related art includes: step S1, degassing (Degas) the wafer; step S2, preprocessing the wafer; step S3, depositing a diffusion barrier layer on the wafer; step S4, carrying out reverse sputtering to remove redundant diffusion barrier layers; step S5, depositing copper seed crystals on the diffusion barrier layer; step S6, depositing a copper metal layer on the copper seed crystal, wherein the copper metal layer fills the through hole of the dielectric layer of the wafer.
However, the semiconductor device manufactured based on the formation method of the metal interconnection structure provided in the related art has a large contact resistance and a large parasitic capacitance.
Disclosure of Invention
The application provides a forming method of a metal interconnection structure, which can solve the problem that the contact resistance of a device is large due to the forming method of the metal interconnection structure provided in the related technology.
In one aspect, an embodiment of the present application provides a method for forming a metal interconnect structure, including:
degassing and copper reduction are carried out on a wafer, a dielectric layer is formed on the wafer, a through hole is formed in the dielectric layer, the degassing and the copper reduction are carried out in the same cavity, and the copper reduction reaction is promoted by heating in the copper reduction process;
depositing a first barrier layer on the side wall of the through hole;
depositing a second barrier layer on the surfaces of the first barrier layer and the dielectric layer;
depositing copper seed crystals on the surface of the second barrier layer;
and forming a copper metal layer on the surface of the copper seed crystal, wherein the copper metal layer fills the through hole.
Optionally, the first barrier layer includes a high-nitrogen amorphous tantalum layer, and the high-nitrogen amorphous tantalum layer includes a nitrogen element and a tantalum element.
Optionally, the depositing a first barrier layer on the sidewall of the via hole includes:
and depositing the high-nitrogen amorphous tantalum layer on the side wall of the through hole by a selective deposition process.
Optionally, the reaction gas in the degassing process comprises argon and hydrogen.
Optionally, the heating temperature in the copper reduction process is 200 to 400 ℃.
Optionally, in the copper reduction process, the copper oxide on the surface of the wafer is reduced to copper by generating atomic hydrogen and/or hydrogen ions in the cavity.
Optionally, in the copper reduction process, atomic hydrogen and/or hydrogen ions are generated outside the chamber, and the atomic hydrogen and/or hydrogen ions are carried into the chamber by a carrier gas to reduce the copper oxide on the surface of the wafer into copper.
Optionally, the second barrier layer comprises tantalum.
Optionally, depositing a second barrier layer on the surfaces of the first barrier layer and the dielectric layer includes:
and depositing tantalum on the surfaces of the first barrier layer and the dielectric layer by a PVD (physical vapor deposition) process.
Optionally, the forming a copper metal layer on the surface of the copper seed crystal includes:
and forming the copper metal layer on the surface of the copper seed crystal through an electroplating process.
Optionally, the dielectric layer sequentially includes, from bottom to top, an NDC layer, a low dielectric constant layer, and a titanium nitride layer.
Optionally, after forming the copper metal layer on the surface of the copper seed crystal, the method further includes:
and removing the first barrier layer, the second barrier layer, the copper seed crystal and the metal copper layer outside the through hole by a planarization process.
Optionally, the planarization process comprises a CMP process.
The technical scheme at least comprises the following advantages:
in the forming process of the metal interconnection structure, degassing and copper reduction are carried out in the same cavity, and copper reduction reaction is promoted by heating in the copper reduction process, so that the copper reduction efficiency is improved, the removal rate of copper oxide generated on the surface of a wafer can be improved, and the contact resistance of a device is reduced to a certain extent.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method of forming a metal interconnect structure provided in one exemplary embodiment of the present application;
fig. 2 is a cross-sectional view of a metal interconnect structure provided in an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for forming a metal interconnect structure provided by an exemplary embodiment of the present application is shown, the method including:
101, degassing and copper reduction are carried out on a wafer, a dielectric layer is formed on the wafer, a through hole is formed in the dielectric layer, the degassing and the copper reduction are carried out in the same cavity, and the copper reduction reaction is promoted by heating in the copper reduction process.
And 103, depositing a second barrier layer on the surfaces of the first barrier layer and the dielectric layer.
And 104, depositing copper seed crystals on the surface of the second barrier layer.
And 105, forming a copper metal layer on the surface of the copper seed crystal, wherein the copper metal layer fills the through hole.
In summary, in the embodiment, in the forming process of the metal interconnection structure, the degassing and the copper reduction are performed in the same cavity, and the copper reduction reaction is promoted by heating in the copper reduction process, so that the efficiency of copper reduction is improved, the removal rate of copper oxide generated on the surface of the wafer can be improved, and the contact resistance of the device is reduced to a certain extent.
Referring to fig. 2, a cross-sectional view of a wafer including a metal interconnect structure is shown, according to an exemplary embodiment of the present application. As shown in fig. 2, a pre-formed pattern layer 210 and a dielectric layer 220 are formed on the wafer, wherein a via 201 is formed in the dielectric layer 220.
In an alternative embodiment, step 10 of the above-described embodiment1, the reaction gas in the degassing process includes argon (Ar) and hydrogen (H)2) (ii) a The heating temperature in the copper reduction process is 200 ℃ to 400 ℃. By setting the reaction gas to contain argon and hydrogen, the thermal conductivity can be improved, and residual gas adsorbed on the surface of the wafer can be effectively removed.
In an alternative embodiment, in step 101 of the above embodiment, during the copper reduction process, the copper oxide (CuO) on the wafer surface may be reduced to copper (Cu) by generating atomic hydrogen (H;) and/or hydrogen ions (H +) in the chamber, which is called Reactive Pre-clean (RPC); alternatively, atomic hydrogen and/or hydrogen ions are generated outside the Chamber, and the atomic hydrogen and/or hydrogen ions are carried into the Chamber by the carrier gas to reduce the copper oxide on the wafer surface to copper, which is called as Active Pretreatment (APC).
In an alternative embodiment, referring to fig. 2, in step 102 of the above embodiment, a first Barrier Layer (Barrier Layer)230 is deposited on the sidewalls of the via 201. Optionally, the first barrier layer 230 includes a High-Nitrogen amorphous Tantalum (TAN) layer, and the TAN layer may be deposited on the sidewalls of the via 201 by a selective deposition process. The adsorption rate of the TAN layer on the medium is several times higher than that of the metal layer, the TAN layer is deposited on the side wall of the through hole 201 through a selective deposition process, reverse sputtering of the TAN layer is not needed, the working procedures of a device manufacturing process are reduced, and manufacturing efficiency is improved to a certain extent.
In an alternative embodiment, the second barrier layer comprises tantalum (Ta); referring to fig. 2, step 103 of the above embodiment, depositing a second barrier layer on the surfaces of the first barrier layer and the dielectric layer includes: the second barrier layer 240 is obtained by depositing tantalum on the surfaces of the first barrier layer 230 and the dielectric layer 220 by a Physical Vapor Deposition (PVD) process. Tantalum deposition by PVD breaks down the scarce TAN on the bottom copper, resulting in a low resistance contact Via (Via).
In an alternative embodiment, referring to fig. 2, step 105 of the above embodiment includes: a copper metal layer 250 is formed on the surface of the copper seed (not labeled in fig. 2) by an electroplating process, and the copper metal layer 250 fills the via hole 201.
In an alternative embodiment, referring to fig. 2, the dielectric layer 220 includes a Nitride Doped Silicon Carbide (NDC) layer 221, a low dielectric constant layer 222, and a titanium Nitride (TiN) layer 223 in that order from bottom to top. Wherein the low-k layer 222 comprises a material with a dielectric constant lower than 5, such as silicon dioxide (SiO)2)。
In an alternative embodiment, referring to fig. 2, after step 105 of the foregoing embodiment, the method further includes: and removing the first barrier layer, the second barrier layer, the copper seed crystal and the metal copper layer outside the through hole 201 through a planarization process to form a metal interconnection structure. Alternatively, the planarization process may be a Chemical Mechanical Polishing (CMP) process.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (13)
1. A method for forming a metal interconnection structure is characterized by comprising the following steps:
degassing and copper reduction are carried out on a wafer, a dielectric layer is formed on the wafer, a through hole is formed in the dielectric layer, the degassing and the copper reduction are carried out in the same cavity, and the copper reduction reaction is promoted by heating in the copper reduction process;
depositing a first barrier layer on the side wall of the through hole;
depositing a second barrier layer on the surfaces of the first barrier layer and the dielectric layer;
depositing copper seed crystals on the surface of the second barrier layer;
and forming a copper metal layer on the surface of the copper seed crystal, wherein the copper metal layer fills the through hole.
2. The method of claim 1, wherein the first barrier layer comprises a high nitrogen amorphous tantalum layer comprising elemental nitrogen and elemental tantalum.
3. The method of claim 2, wherein depositing a first barrier layer on sidewalls of the via comprises:
and depositing the high-nitrogen amorphous tantalum layer on the side wall of the through hole by a selective deposition process.
4. The method of claim 3, wherein the reactant gases in the degassing process include argon and hydrogen.
5. The method of claim 4, wherein the heating temperature during the copper reduction is 200 to 400 degrees Celsius.
6. A method as claimed in claim 5, wherein during the copper reduction process, the copper oxide on the wafer surface is reduced to copper by generating atomic hydrogen and/or hydrogen ions within the chamber.
7. The method as claimed in claim 5, wherein during the copper reduction process, the copper oxide on the wafer surface is reduced to copper by generating atomic hydrogen and/or hydrogen ions outside the chamber and carrying the atomic hydrogen and/or hydrogen ions into the chamber by a carrier gas.
8. The method of any of claims 1 to 7, wherein the second barrier layer comprises tantalum.
9. The method of claim 8, wherein depositing a second barrier layer on the surface of the first barrier layer and the dielectric layer comprises:
and depositing tantalum on the surfaces of the first barrier layer and the dielectric layer by a PVD (physical vapor deposition) process.
10. The method of claim 9, wherein the forming a copper metal layer on the surface of the copper seed comprises:
and forming the copper metal layer on the surface of the copper seed crystal through an electroplating process.
11. The method of claim 10, wherein the dielectric layer comprises an NDC layer, a low dielectric constant layer, and a titanium nitride layer in this order from bottom to top.
12. The method as claimed in any one of claims 1 to 7, further comprising, after forming the copper metal layer on the surface of the copper seed crystal:
and removing the first barrier layer, the second barrier layer, the copper seed crystal and the metal copper layer outside the through hole by a planarization process.
13. The method of claim 12, wherein the planarization process comprises a CMP process.
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| CN201911308057.7A CN111029299A (en) | 2019-12-18 | 2019-12-18 | Method for forming metal interconnection structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111696918A (en) * | 2020-07-15 | 2020-09-22 | 华虹半导体(无锡)有限公司 | Manufacturing method and device of interconnection structure |
| CN112635398A (en) * | 2020-12-18 | 2021-04-09 | 华虹半导体(无锡)有限公司 | Process method for filling copper in groove |
| CN112750763A (en) * | 2021-01-22 | 2021-05-04 | 上海华虹宏力半导体制造有限公司 | Method for reducing contact resistance of through hole |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6309970B1 (en) * | 1998-08-31 | 2001-10-30 | Nec Corporation | Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface |
| US20040121582A1 (en) * | 2002-12-16 | 2004-06-24 | Dongbu Electronics Co., Ltd. | Method of manufacturing a semiconductor device |
| CN1815708A (en) * | 2004-12-27 | 2006-08-09 | 联华电子股份有限公司 | Interconnect structure with low-resistance inlaid copper/barrier and method for manufacturing the same |
| US20070155166A1 (en) * | 2005-12-14 | 2007-07-05 | Jong-Guk Kim | Method and apparatus for depositing copper wiring |
| US20080052886A1 (en) * | 2006-08-29 | 2008-03-06 | Dongbu Hitek Co., Ltd. | Degas chamber for fabricating semiconductor device and degas method employing the same |
| CN101174577A (en) * | 2001-10-26 | 2008-05-07 | 应用材料公司 | Integration of ald tantalum nitride and alpha-phase tantalum for copper metallization application |
| CN103779269A (en) * | 2012-10-26 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Method for processing copper surface of interconnected wire |
| TW201418503A (en) * | 2012-06-18 | 2014-05-16 | Tokyo Electron Ltd | Method for forming film containing manganese |
| CN103811409A (en) * | 2012-11-12 | 2014-05-21 | 中微半导体设备(上海)有限公司 | Method for enhancing etching selectivity of low dielectric material for TiN hard mask |
| CN104112697A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Copper filling quality improving method |
| CN104282618A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| US20150126027A1 (en) * | 2012-07-18 | 2015-05-07 | Tokyo Electron Limited | Method for manufacturing semiconductor device |
| CN104979276A (en) * | 2014-04-09 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN105990221A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal interconnection |
| US20170200632A1 (en) * | 2016-01-11 | 2017-07-13 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| CN110289208A (en) * | 2019-06-28 | 2019-09-27 | 惠科股份有限公司 | The preparation method and thin film transistor (TFT) of copper conductive layer |
-
2019
- 2019-12-18 CN CN201911308057.7A patent/CN111029299A/en active Pending
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6309970B1 (en) * | 1998-08-31 | 2001-10-30 | Nec Corporation | Method of forming multi-level copper interconnect with formation of copper oxide on exposed copper surface |
| CN101174577A (en) * | 2001-10-26 | 2008-05-07 | 应用材料公司 | Integration of ald tantalum nitride and alpha-phase tantalum for copper metallization application |
| US20040121582A1 (en) * | 2002-12-16 | 2004-06-24 | Dongbu Electronics Co., Ltd. | Method of manufacturing a semiconductor device |
| CN1815708A (en) * | 2004-12-27 | 2006-08-09 | 联华电子股份有限公司 | Interconnect structure with low-resistance inlaid copper/barrier and method for manufacturing the same |
| US20070155166A1 (en) * | 2005-12-14 | 2007-07-05 | Jong-Guk Kim | Method and apparatus for depositing copper wiring |
| US20080052886A1 (en) * | 2006-08-29 | 2008-03-06 | Dongbu Hitek Co., Ltd. | Degas chamber for fabricating semiconductor device and degas method employing the same |
| TW201418503A (en) * | 2012-06-18 | 2014-05-16 | Tokyo Electron Ltd | Method for forming film containing manganese |
| US20150126027A1 (en) * | 2012-07-18 | 2015-05-07 | Tokyo Electron Limited | Method for manufacturing semiconductor device |
| CN103779269A (en) * | 2012-10-26 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Method for processing copper surface of interconnected wire |
| CN103811409A (en) * | 2012-11-12 | 2014-05-21 | 中微半导体设备(上海)有限公司 | Method for enhancing etching selectivity of low dielectric material for TiN hard mask |
| CN104112697A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Copper filling quality improving method |
| CN104282618A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104979276A (en) * | 2014-04-09 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN105990221A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal interconnection |
| US20170200632A1 (en) * | 2016-01-11 | 2017-07-13 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
| CN110289208A (en) * | 2019-06-28 | 2019-09-27 | 惠科股份有限公司 | The preparation method and thin film transistor (TFT) of copper conductive layer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111696918A (en) * | 2020-07-15 | 2020-09-22 | 华虹半导体(无锡)有限公司 | Manufacturing method and device of interconnection structure |
| CN112635398A (en) * | 2020-12-18 | 2021-04-09 | 华虹半导体(无锡)有限公司 | Process method for filling copper in groove |
| CN112750763A (en) * | 2021-01-22 | 2021-05-04 | 上海华虹宏力半导体制造有限公司 | Method for reducing contact resistance of through hole |
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