CN114695252A - Method for forming metal layer - Google Patents

Method for forming metal layer Download PDF

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Publication number
CN114695252A
CN114695252A CN202210187224.2A CN202210187224A CN114695252A CN 114695252 A CN114695252 A CN 114695252A CN 202210187224 A CN202210187224 A CN 202210187224A CN 114695252 A CN114695252 A CN 114695252A
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CN
China
Prior art keywords
layer
contact hole
metal
dielectric layer
hydrofluoric acid
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Pending
Application number
CN202210187224.2A
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Chinese (zh)
Inventor
张志诚
陈明志
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202210187224.2A priority Critical patent/CN114695252A/en
Publication of CN114695252A publication Critical patent/CN114695252A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Abstract

The invention provides a method for forming a metal layer, which comprises the steps of providing a semiconductor substrate, wherein a dielectric layer and a contact hole penetrating through the dielectric layer are formed on the semiconductor substrate; depositing a barrier layer on the surface of the dielectric layer; depositing metal on the surface of the barrier layer, wherein the contact hole is filled with the metal; grinding until the dielectric layer is exposed to form a contact hole plug; depositing a medium barrier layer, an interlayer medium layer, an anti-reflection layer and a mask layer above the semiconductor substrate in sequence, and etching to form a groove exposing the upper surface of the contact hole plug; cleaning with hydrofluoric acid solution to remove etching residues; cleaning with water to remove hydrofluoric acid solution residues; and filling metal in the groove to form a metal layer electrically contacted with the contact hole plug. According to the invention, the DHF cleaning solvent is used for replacing EKC as a wet cleaning solution to clean and remove etching residues, so that the defect of open circuit at the bottom of the contact hole plug is avoided, and the product yield of devices is improved.

Description

Method for forming metal layer
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a metal layer.
Background
At present, in the manufacturing process of a semiconductor device, Contact holes (CT) are used as channels for interconnection among multiple metal layers and connection between an active region of the device and an external circuit, and play an important role in the structure composition of the device. With the increasing of semiconductor technology, the size of the contact hole is continuously reduced, the size of the contact hole required by the manufacturing process is correspondingly reduced, and the manufacturing difficulty of the contact hole is correspondingly increased.
FIG. 1 is a flow chart of a conventional method for forming a contact hole. As shown in fig. 1, the conventional method for forming a contact hole includes: forming a contact hole 12 in a dielectric layer 11 on the surface of a semiconductor substrate 10; depositing a barrier layer 13 on the surface of the dielectric layer 11; depositing metal tungsten 14 on the surface of the barrier layer 13, wherein the metal tungsten 14 fills the contact hole; and grinding until the dielectric layer 11 is exposed to form a contact hole plug 15. Fig. 2-5 are schematic structural diagrams illustrating steps in a conventional contact hole forming method. As shown in fig. 2-5, in the conventional contact hole forming process, since the size of the contact hole 12 is too small, an overhang (overhand) phenomenon occurs when the barrier layer 13 is deposited on the surface thereof, as shown at 16 in fig. 3. This phenomenon causes the presence of voids 17 in contact hole plugs 15 formed by the subsequent deposition of metallic tungsten.
The voids 17 may cause, in a back end of line (BEOL) process of semiconductor device fabrication, as shown in fig. 6, in a process of etching a metal layer above the contact hole plug 15, because an EKC solution is introduced into the bottom of the contact hole 12 due to etching residues removed by cleaning with the EKC solution, the EKC has a high etching rate to tungsten, and may etch the bottom of the contact hole plug 15, and the formed contact hole plug 15 generates an open defect (open defect), as shown in fig. 6 at 18, which may seriously affect the performance and yield of the semiconductor device.
Disclosure of Invention
Accordingly, the present invention provides a method for forming a metal layer to avoid the occurrence of open-circuit defect of a contact plug and to improve the performance and yield of a semiconductor device.
The invention provides a method for forming a metal layer, which comprises the following steps:
providing a semiconductor substrate, wherein a dielectric layer and a contact hole penetrating through the dielectric layer are formed on the semiconductor substrate;
depositing a barrier layer on the surface of the dielectric layer;
depositing metal on the surface of the barrier layer, and filling the contact hole with the metal;
grinding until the dielectric layer is exposed to form a contact hole plug;
depositing and forming a medium barrier layer, an interlayer medium layer, an anti-reflection layer and a mask layer in sequence, and etching to form a groove exposing the upper surface of the contact hole plug;
sixthly, cleaning by adopting a hydrofluoric acid solution to remove etching residues;
seventhly, cleaning with water to remove the hydrofluoric acid solution residue;
and step eight, filling metal in the groove to form a metal layer electrically contacted with the contact hole plug.
Preferably, the semiconductor substrate in the first step is a silicon substrate.
Preferably, the metal in step three is tungsten.
Preferably, the grinding in step four is a chemical mechanical grinding method.
Preferably, the etching in the fifth step is a photolithography etching process.
Preferably, the volume ratio of the deionized water to the hydrofluoric acid in the hydrofluoric acid solution in the sixth step is in the range of 100: 1 to 1000: 1.
Preferably, the water in step seven is distilled water or deionized water.
Preferably, the material of the metal layer in the step eight is aluminum, copper, aluminum-copper alloy or tungsten.
According to the invention, the cleaning solution containing DHF is used for wet cleaning of the etching residues, so that compared with the wet cleaning method using the solution containing EKC in the prior art, the etching rate of metal tungsten is reduced, the open circuit defect of the contact hole is avoided, and the performance and yield of the semiconductor device are improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a flow chart illustrating a conventional method for forming a contact hole;
FIGS. 2-5 are schematic structural diagrams illustrating steps in a conventional method for forming a contact hole;
FIG. 6 is a schematic view of a semiconductor structure having a contact plug with a short defect;
FIG. 7 is a schematic diagram of a transmission electron of a contact hole plug having a short defect;
FIG. 8 is a graph comparing the tungsten etch rate of a DHF cleaning solution to an EKC cleaning solution;
FIG. 9 is a flow chart of a method of forming a metal layer according to an embodiment of the invention;
FIG. 10 is a schematic diagram illustrating a transmission electron of a contact hole plug formed according to an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout this application, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
The CMOS integrated circuit process enters the production stage and the process of the interconnect layer changes accordingly. To provide larger area interconnects, more flexible multilayer metal processes are introduced. The continuity between the metal layers is realized by vertical interconnection via plugs, and the connection between each level of MOS and the metal is realized by vertical contact hole plugs.
The EKC cleaning solvent is a post-etch residue remover, which is commonly used to remove organic polymer components, post-photoresist ashing residues, and organometallic etching residues from the surface of semiconductor substrates during a semiconductor wet cleaning process. However, the etching rate of tungsten is high, and the wet cleaning process for removing the etching or polishing residue of tungsten metal is very likely to cause short circuit at the bottom of the contact plug due to the chemical reaction and subsequent high temperature, as shown in fig. 7, 19. Therefore, the embodiment of the invention proposes that the DHF cleaning solvent is used as a wet cleaning solution to replace EKC to clean and remove the residues after the etching of the metal tungsten. As shown in fig. 8, the DHF cleaning solution has a tungsten etch rate of 0.3A, which is indeed significantly less than the 1.3 w etch rate of the EKC solution. The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Fig. 9 is a flowchart illustrating a method for forming a metal layer according to an embodiment of the invention. As shown in fig. 9, the method comprises the following steps:
step one, providing a semiconductor substrate, wherein a dielectric layer and a contact hole penetrating through the dielectric layer are formed on the semiconductor substrate.
The semiconductor substrate may be single crystal silicon, polycrystalline silicon, or amorphous silicon; the semiconductor substrate may also be silicon, germanium, gallium arsenide, or a silicon germanium compound; the semiconductor substrate may also have an epitaxial layer or a silicon-on-insulator substrate (SOI substrate); the semiconductor substrate may also be other semiconductor materials. In an embodiment of the present invention, the semiconductor substrate is a silicon substrate. Before forming the contact hole, a source region, a drain region, a metal silicide on the surface, a gate structure on the substrate and a dielectric layer covering the gate structure need to be formed in the semiconductor substrate, wherein the dielectric layer is an interlayer dielectric layer (ILD). The interlevel dielectric layer may be silicon oxide, silicon nitride, or a low-K dielectric. When the contact hole is formed, the size of the contact hole needs to be defined by patterning the interlayer dielectric layer.
And secondly, depositing a barrier layer on the surface of the dielectric layer.
In the embodiment of the present invention, the barrier layer may be silicon oxide formed by a thermal oxidation or deposition process, and may also be silicon nitride, silicon oxynitride, or silicon carbide nitride.
And thirdly, depositing metal on the surface of the barrier layer, and filling the contact hole with the metal.
In the embodiment of the invention, the deposited metal is tungsten. Tungsten is commonly used in integrated circuits to fill contact holes or contact holes between metal layers to form so-called plugs (plugs) to connect the metal layers with silicon or a different metal layer. In particular, tungsten may be used to connect the drain, source, gate, body or well resistors of the MOS transistor to the first layer of metal, referred to as contact holes. Tungsten also enables connections between metal layers. Tungsten may also be used as the first layer of interconnect metal.
And step four, grinding until the dielectric layer is exposed to form a contact hole plug.
In the embodiment of the invention, the grinding is a chemical mechanical grinding method.
And step five, depositing and forming a medium barrier layer, an interlayer medium layer, an anti-reflection layer and a mask layer in sequence, and etching to form a groove exposing the upper surface of the contact hole plug.
In step five, back end of line (BEOL) of semiconductor device fabrication is performed, and formation of metal layers is performed. And depositing a medium barrier layer, an interlayer medium layer, an anti-reflection layer and a mask layer on the basis of the semiconductor structure, and forming a groove exposing the upper surface of the contact hole plug by utilizing a photoetching process. Here, the formation of the corresponding pattern by using the photolithography and etching processes is common knowledge and common means of those skilled in the art, and detailed process procedures thereof will not be described herein.
And sixthly, cleaning by adopting a hydrofluoric acid solution to remove etching residues.
The most commonly used method for removing the residues after etching is the EKC solution, but due to the limitation of the small size of the contact hole in the semiconductor process, the phenomenon of hanging 16(overhang) shown in fig. 3 is very easy to occur, so that the gap 17 shown in fig. 4 exists in the formed contact hole plug, which causes that the EKC solution flows into the bottom of the contact hole along the vertical arrow shown in fig. 6 when the EKC solution is used for removing the etching material in the subsequent metal layer forming process, and the EKC solution has high corrosion performance on the metal tungsten, so that the contact hole plug is disconnected in the metal layer interconnection process, and the performance and yield of the device are seriously affected. Therefore, in the embodiment of the invention, the etching residues are cleaned and removed by using the hydrofluoric acid solution. In the embodiment of the invention, the volume ratio of the deionized water to the hydrofluoric acid in the hydrofluoric acid solution is 100: 1 to 1000: 1, and the hydrofluoric acid solution is a dilute hydrofluoric acid cleaning solution. Compared with the EKC solution, the etching rate of the hydrofluoric acid solution to tungsten is lower, so that even if the hydrofluoric acid solution flows into the bottom of the contact hole due to gaps in the subsequent process, the contact hole plug cannot be broken, and the performance of a semiconductor device cannot be seriously influenced.
And seventhly, cleaning with water to remove the hydrofluoric acid solution residue.
In the present embodiment, the water is distilled water or deionized water. The solution used in wet cleaning is generally corrosive and needs to be cleaned with water after cleaning to remove the residue of the cleaning solution.
And step eight, filling metal in the groove to form a metal layer electrically contacted with the contact hole plug.
In the embodiment of the invention, the metal layer is made of aluminum, copper, aluminum-copper alloy or tungsten.
Of course, the metal layer forming method of the embodiment of the invention is also suitable for the metal layer of the multi-layer interconnection formed subsequently.
FIG. 9 is a schematic diagram illustrating transmission electrons of a contact hole plug formed according to an embodiment of the present invention. As is apparent from comparison with fig. 7, the contact hole plug formed by removing the etching residue by cleaning with a hydrofluoric acid solution has no open defect.
According to the invention, the cleaning solution containing DHF is adopted to carry out wet cleaning on the etching residues, and compared with the wet cleaning method adopting the solution containing EKC in the prior art, the wet cleaning method reduces the etching rate of metal tungsten, avoids the generation of open circuit defects of contact holes, and improves the performance and yield of semiconductor devices.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A method for forming a metal layer, comprising the steps of:
providing a semiconductor substrate, wherein a dielectric layer and a contact hole penetrating through the dielectric layer are formed on the semiconductor substrate;
depositing a barrier layer on the surface of the dielectric layer;
depositing metal on the surface of the barrier layer, and filling the contact hole with the metal;
grinding until the dielectric layer is exposed to form a contact hole plug;
depositing and forming a medium barrier layer, an interlayer medium layer, an anti-reflection layer and a mask layer in sequence, and etching to form a groove exposing the upper surface of the contact hole plug;
sixthly, cleaning by adopting a hydrofluoric acid solution to remove etching residues;
seventhly, cleaning with water to remove the hydrofluoric acid solution residue;
and step eight, filling metal in the groove to form a metal layer electrically contacted with the contact hole plug.
2. The method of claim 1, wherein in step one the semiconductor substrate is a silicon substrate.
3. The method according to claim 1, wherein the metal is tungsten in step three.
4. The method of claim 1, wherein the polishing in step four is a chemical mechanical polishing.
5. The method of claim 1, wherein the etching in step five is a photolithography etching process.
6. The method of claim 1, wherein the hydrofluoric acid solution in the sixth step has a volume ratio of deionized water to hydrofluoric acid in a range of 100: 1 to 1000: 1.
7. The method of claim 1, wherein the water in step seven is distilled water or deionized water.
8. The method according to claim 1, wherein a material of the metal layer in the step eight is aluminum, copper, an aluminum-copper alloy, or tungsten.
CN202210187224.2A 2022-02-28 2022-02-28 Method for forming metal layer Pending CN114695252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210187224.2A CN114695252A (en) 2022-02-28 2022-02-28 Method for forming metal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210187224.2A CN114695252A (en) 2022-02-28 2022-02-28 Method for forming metal layer

Publications (1)

Publication Number Publication Date
CN114695252A true CN114695252A (en) 2022-07-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210187224.2A Pending CN114695252A (en) 2022-02-28 2022-02-28 Method for forming metal layer

Country Status (1)

Country Link
CN (1) CN114695252A (en)

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