TWI665773B - Package substrate, package structure and method for manufacturing the same - Google Patents

Abstract

A packaging structure includes a packaging substrate and at least one chip. The packaging substrate includes a dielectric layer and a first conductive circuit layer embedded in the dielectric layer. The first conductive circuit layer includes at least two Electrical contact pads; the package substrate further includes at least two metal posts, at least two of the metal posts are formed on at least two of the electrical contact pads, and at least one of the wafers is electrically connected to at least two of the metal posts. The invention also relates to a packaging substrate and a manufacturing method of a packaging structure.

Description

Packaging substrate, packaging structure and manufacturing method thereof

The invention relates to packaging technology, in particular to a packaging substrate, a packaging structure and a manufacturing method thereof.

At present, electronic products are booming in the direction of high integration, miniaturization and miniaturization. On the premise of meeting the good electrical and thermal performance of electronic products, printed package substrates or semiconductor integrated circuit package substrates are also moving towards light, thin, short, and small design trends. With the development of this trend, the interconnection density of electronic products at the design level has been increasing. That is to say, in the increasingly limited area, more input and output signal lines need to be designed. In addition, since the components operate under high-speed signal lines, the performance of the components must also be improved accordingly.

Based on the above requirements, people have developed flip chip flip chip connection technology and wire bonding package connection technology. However, during the packaging process, flip chip flip-chip connection technology and wire bonding package connection technology are also prone to the following problems: Flip chip flip-chip connection technology: The bonding surface area of the solder balls of the flip chip and the electrical contact pads of the buried carrier board is too small, which reduces the bonding force between the flip chip wafer and the electrical contact pads of the buried carrier board, and the board is prone to appear. Surface damage or wafer peeling.

Wire bonding package connection technology: Wire bonding chip connects wire bonding chip and buried wire carrier board with metal wires. Because the buried fingers are lower than the surface of the dielectric layer, it is easy to cause the wire bonding porcelain to hit the edge of the dielectric layer, resulting in poor wiring. phenomenon.

In view of this, the present invention provides a package substrate, a package structure, and a manufacturing method thereof capable of solving the above problems.

A method for manufacturing a packaging structure includes the steps of: providing a carrier board, the carrier board including a core board and a first copper foil layer formed on a surface of the core board; The first conductive circuit layer is formed on the surface of the core board, the first conductive circuit layer includes at least two electrical contact pads; and a dielectric layer is formed on a surface of the first conductive circuit layer away from the carrier board, so that the A first conductive circuit layer is embedded in the dielectric layer; removing the core board and the first copper foil layer; forming at least two metal pillars by electroplating on at least two of the electrical contact pads; and providing at least one wafer by covering Crystal or wire bonding technology electrically connects at least one of the wafers to at least two of the metal pillars.

A packaging structure includes a packaging substrate and at least one chip. The packaging substrate includes a dielectric layer and a first conductive circuit layer embedded in the dielectric layer. The first conductive circuit layer includes at least two Electrical contact pads; the package substrate further includes at least two metal posts, at least two of the metal posts are formed on at least two of the electrical contact pads, and at least one of the wafers is electrically connected to at least two of the metal posts.

A packaging substrate includes a dielectric layer and a first conductive circuit layer embedded in the dielectric layer. The first conductive circuit layer further includes at least two electrical contact pads. The packaging substrate further includes a plurality of electrical contact pads. Metal posts, at least two of which are formed on at least two of the electrical contact pads.

Compared with the prior art, a packaging substrate, a packaging structure and a manufacturing method thereof provided by the present invention form at least two metal pillars on at least two electrical contact pads. 1) The electrical contact between a flip-chip wafer and a buried carrier can be increased. The bonding force between the pads to avoid board surface damage or wafer peeling; at least two metal pillars are formed on the electrical contact pad of the first conductive circuit layer, 2) the metal pillars (buried fingers) can be higher than the dielectric layer Surface to avoid poor wiring.

100, 200‧‧‧ package structure

10‧‧‧ Buried Wire Carrier Board

11‧‧‧carrying plate

111‧‧‧Core board

112‧‧‧The first copper foil layer

113‧‧‧Second copper foil layer

12‧‧‧The first dry film layer

22‧‧‧The first conductive circuit layer

221‧‧‧Second surface

222‧‧‧electric contact pad

21‧‧‧ Dielectric layer

211‧‧‧first surface

13‧‧‧The third copper foil layer

24‧‧‧Conductive blind hole

14‧‧‧Second dry film layer

23‧‧‧Second conductive circuit layer

231‧‧‧pad

20‧‧‧ package substrate

25‧‧‧First solder resist

251‧‧‧First opening

252‧‧‧ Third surface

26‧‧‧Second solder mask

261‧‧‧Second opening

27‧‧‧ third dry film

271‧‧‧Third opening

28‧‧‧ Fourth dry film

29‧‧‧ metal pillar

291‧‧‧ Fourth Surface

30‧‧‧Chip

31‧‧‧ fifth surface

32‧‧‧Conductive bump

40‧‧‧solder

50‧‧‧ seal colloid

60‧‧‧metal wire

FIG. 1 is a cross-sectional view of a carrier plate according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view after forming a first dry film layer on a surface of a copper foil layer of the carrier board of FIG. 1 and forming a first conductive circuit layer in a gap between the first dry film layers.

FIG. 3 is a cross-sectional view after removing the first dry film layer shown in FIG. 2.

4 is a cross-sectional view of a first conductive circuit layer shown in FIG. 3 after a dielectric layer and a copper foil layer are laminated on the surface.

5 is a cross-sectional view after forming a blind hole penetrating through the dielectric layer and the copper foil layer shown in FIG. 4.

6 is a cross-sectional view after a second dry film layer is formed on the surface of the copper foil layer shown in FIG. 5 and a second conductive circuit layer is formed between the second dry film layers.

FIG. 7 is a cross-sectional view after removing the second dry film layer shown in FIG. 6.

FIG. 8 is a cross-sectional view after removing the core plate and the first copper foil layer of the carrier plate shown in FIG. 7 and slightly etching away the first copper foil layer and the third copper foil layer shown in FIG. 7.

FIG. 9 is a cross-sectional view after a first solder resist layer and a second solder resist layer are formed on the surfaces of the first conductive circuit layer and the second conductive circuit layer shown in FIG. 8, respectively.

FIG. 10 is a cross-sectional view after a third and a fourth dry film layer are respectively formed on the surfaces of the first solder resist layer and the second solder resist layer shown in FIG. 9.

11 is a cross-sectional view of a metal post formed by electroplating on the electrical contact pad exposed from the opening of the third dry film layer shown in FIG. 10.

FIG. 12 is a cross-sectional view of the third dry film layer shown in FIG. 11.

FIG. 13 is a cross-sectional view after forming at least one wafer on the copper pillar shown in FIG. 11 and then forming a package structure.

14 is a cross-sectional view of a second package structure provided by a second embodiment of the present invention.

In order to further explain the technical means and effects adopted by the present invention to achieve the intended purpose of the present invention, the specific implementations, structures, features, and methods of the flexible package substrate and the manufacturing method of the present invention are described below with reference to FIGS. 1-14 and the preferred embodiments. The effect is explained in detail below.

12-13, a first embodiment of the present invention provides a packaging structure 100. The packaging structure 100 includes a packaging substrate 20, at least one wafer 30, and a colloid 50. The wafer 30 is formed on the packaging substrate 20 by a solder 40, and the sealing compound 50 covers the wafer 30 and a part of the packaging substrate 20.

Referring to FIG. 12, the package substrate 20 includes an insulating dielectric layer 21, a first conductive circuit layer 22 embedded in the dielectric layer 21, and an adhesive layer attached to the dielectric layer 21 and connected to the first layer. A second conductive circuit layer 23 opposite to a conductive circuit layer 22, a first solder resist layer 25 adhered to the surface of the first conductive circuit layer 22, and a first solder resist layer 25 adhered to the surface of the second conductive circuit layer 23.二 防焊 层 26。 Two welding layer 26.

In this embodiment, the material of the dielectric layer 21 is polypropylene (PP). In other embodiments, the material of the dielectric layer 21 may also be polyethylene terephthalate. (Polyethylene Terephthalate, PET), Polyethylene Naphthalate (PEN), Polyimide (PI) or other resin hard materials.

The dielectric layer 21 includes a first surface 211, and the first conductive circuit layer 22 includes a second surface 221, and the second surface 221 is flush with the first surface 211.

The first conductive circuit layer 22 further includes at least two electrical contact pads 222.

The second conductive circuit layer 23 includes at least one solder pad 231. Each of the bonding pads 231 is used to electrically connect an external electronic component.

The first solder resist layer 25 includes at least two first openings 251, and the electrical contact pads 222 are exposed from the first openings 251. The first solder mask layer 25 further includes a third surface 252. The third surface 252 is far from the first conductive circuit layer 22.

The second solder mask layer 26 includes at least one second opening 261, and at least one of the solder pads 231 is exposed from the second opening 261.

The package substrate 20 further includes at least two metal pillars 29 formed on the electrical contact pad 222 and exposed through the first opening 251. The size of the metal post 29 is smaller than the size of the electrical contact pad 222. The metal pillar 29 includes a fourth surface 291 that is flush with the third surface 252.

The metal pillars 29 are used to increase the contact area between the solder 40 and the metal pillars 29, thereby increasing the bonding force between the chip 30 and the package substrate 20 to avoid board surface damage or chip peeling.

In this embodiment, the metal pillar 29 is a copper pillar. In other embodiments, the material of the metal pillar 29 is not limited to copper, and the shape is not limited to a columnar shape, as long as it can fulfill the above functions.

The package substrate 20 further includes at least one conductive blind hole 24. The at least one conductive blind hole 24 is electrically connected to the first conductive circuit layer 22 and the second conductive circuit layer 23.

The wafer 30 includes a fifth surface 31, and the fifth surface 31 faces the metal pillar 29. At least two conductive bumps 32 are formed on the fifth surface 31, and the conductive bumps 32 correspond to the metal pillars 29 one-to-one. Each of the conductive bumps 32 is fixed to each of the metal pillars 29 by solder 40. The solder 40 completely covers the metal pillar 29.

The sealing compound 40 covers the wafer 30. The sealing compound 40 includes a sixth surface 41. The sixth surface 41 is in contact with the first solder resist 25.

Please refer to FIG. 1 to FIG. 11. The first embodiment of the present invention further provides a method for manufacturing the packaging structure 100, which includes the following steps: First, referring to FIG. 1, a carrier board 11 is provided.

The carrier plate 11 includes a core plate 111, a first copper foil layer 112 formed on a surface of the core plate 111, and a second copper layer formed on a surface of the first copper foil layer 112 remote from the core plate 111. Foil layer 113.

In this embodiment, the material of the core plate 111 is any kind of insulating material with a bearing effect. In this embodiment, the material of the core plate 111 is polyimide (PI). In other embodiments, the material of the core plate 111 may also be other resin hard materials such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and the like. .

The first copper foil layer 112 and the second copper foil layer 113 may be an electroless copper plating layer or an original copper layer.

In this embodiment, the thickness of the second copper foil layer 113 is smaller than the thickness of the first copper foil layer 112.

In the second step, referring to FIGS. 2-3, a first conductive circuit layer 22 is formed on a surface of the second copper foil layer 113 away from the core plate 111.

Specifically, the manufacturing method of the first conductive circuit layer 22 includes the following steps: First, referring to FIG. 2, a dry film is pasted on a surface of the second copper foil layer 113 away from the core plate 111, and the dry film is bonded. A first dry film layer 12 is formed by the exposure and development processes, and the first conductive circuit layer 22 is formed by vertical plating between the first dry film layers 12; secondly, referring to FIG. 3, the first dry film layer is peeled off.膜层 12。 Film layer 12.

In this embodiment, the thickness of the first conductive circuit layer 22 is smaller than the thickness of the first dry film layer 12.

In the second step, referring to FIG. 4, a dielectric layer 21 is formed on a surface of the first conductive circuit layer 22 away from the carrier plate 11 and is formed on a surface of the dielectric layer 21 remote from the first conductive circuit layer 22.一 第一 铜 铜 层 13。 A third copper foil layer 13.

Specifically, the first conductive circuit layer 22 is embedded in the dielectric layer 21.

Specifically, the third copper foil layer 13 may be an electroless copper plating layer or an original copper layer.

In this embodiment, the thickness of the third copper foil layer 13 is equal to the thickness of the second copper foil layer 113.

In the third step, referring to FIG. 5, at least one conductive blind hole 24 penetrating the third copper foil layer 13 and the dielectric layer 21 is formed.

Specifically, the conductive blind hole 24 is electrically connected to the third copper foil layer 13 and the first conductive circuit layer 22.

In the fourth step, referring to FIGS. 6-7, a second conductive circuit layer 23 is formed on the surface of the third copper foil layer 13.

Specifically, the manufacturing method of the second conductive circuit layer 23 includes the following steps: First, referring to FIG. 6, a dry film is pasted on a surface of the third copper foil layer 13 away from the dielectric layer 21, and the dry The film is formed through a process of exposure and development to form a second dry film layer 14 and vertical plating is performed between the second dry film layers 14; secondly, referring to FIG. 7, the second dry film layer 14 is peeled off to form the second dry film layer 14. Conductive line layer 23.

In this embodiment, the thickness of the second conductive circuit layer 23 is smaller than the thickness of the second dry film layer 14.

Fifth step, referring to FIG. 8, remove the core plate 111 and the first copper foil layer 112, and remove the second copper foil layer 113 corresponding to the first dry film layer 12 by micro-etching, and remove the second copper foil layer 113 corresponding to the first dry film layer 12. The third copper foil layer 13 corresponding to the second dry film layer 14 obtains a buried wire carrier board 10.

Wherein, the buried carrier board 10 includes an insulating dielectric layer 21, a first conductive circuit layer 22 embedded in the dielectric layer 21, and a bonding layer on the dielectric layer 21 and the first A second conductive circuit layer 23 opposite to the conductive circuit layer 22. The dielectric layer 21 includes a first surface 211, and the first conductive circuit layer 22 includes a two surface 221, and the second surface 221 is flush with the first surface 211. The first conductive circuit layer 22 further includes at least two electrical contact pads 222. The second conductive circuit layer 23 includes at least one solder pad 231.

The buried wire carrier board 10 further includes at least one conductive blind hole 24. The at least one conductive blind hole 24 is electrically connected to the first conductive circuit layer 22 and the second conductive circuit layer 23.

Sixth step, referring to FIGS. 9-11, a copper pillar 29 is formed on each of the electrical contact pads 222 to form the package substrate 20.

Specifically, the method for manufacturing the package substrate 20 further includes the following steps: First, referring to FIG. 9, a first solder resist layer 25 and a second solder resist layer 26 are formed on the surfaces of the first conductive circuit layer 22 and the second conductive circuit layer 23, respectively. The first solder resist layer 25 includes at least two first openings 251, and at least two of the electrical contact pads 222 are exposed from the first openings 251. The first solder mask layer 25 further includes a third surface 252. The third surface 252 is far from the first conductive circuit layer 22. The second solder mask layer 26 includes at least one second opening 261, and at least one of the solder pads 231 is exposed from the second opening 261.

Secondly, referring to FIG. 10, a third dry film layer 27 and a fourth dry film layer 28 are respectively adhered on the surfaces of the first solder resist layer 25 and the second solder resist layer 26. The third dry film layer 27 covers a part of the first opening 251. At least two third openings 271 are formed on the third dry film layer 27. Each of the electrical contact pads 222 is exposed from each of the three openings 271. The size of each of the third openings 271 is smaller than that of each of the electrical openings. The size of the contact pad 222. The fourth dry film layer 28 completely covers the second solder mask layer 26.

Again, referring to FIG. 11, copper is plated in each of the third openings 271 by vertical plating to form the metal pillar 29. The thickness of the metal pillar 29 is equal to the thickness of the first solder resist layer 25.

Finally, referring to FIG. 12, the third dry film layer 26 and the fourth dry film layer 27 are peeled off to form the package substrate 20.

The seventh step, referring to FIG. 13, provides a wafer 30 and a colloid 50. The wafer 30 is formed on the metal pillar 29, and the sealing gel 50 covers the wafer 30 and the metal pillar 29 to form The packaging structure 100.

The wafer 30 includes a fifth surface 31, and the fifth surface 31 faces the metal pillar 29. At least two conductive bumps 32 are formed on the fifth surface 31. At least two of the conductive bumps 32 correspond to at least two of the metal pillars 29. Each of the conductive bumps 32 is fixed to each of the metal pillars 29 by solder 40. The solder 40 covers the conductive bump 32 and the metal pillar 29. The sealing compound 40 includes a sixth surface 41. The sixth surface 41 is in contact with the first solder resist 25.

Referring to FIG. 14, a second embodiment of the present invention provides a packaging structure 200. The packaging structure 200 is similar to the packaging structure 100 provided by the first embodiment of the present invention, and the only difference is that the wafer 30 does not include electrical conductivity. A bump 32, the wafer 30 is fixed on the first solder resist layer 25, and the wafer 30 is electrically connected to the metal pillar 29 through at least one metal wire 60.

Compared with the prior art, a package substrate, a package structure and a manufacturing method thereof provided by the present invention form at least two metal pillars on at least two electrical contact pads. The bonding force between the electrical contact pads of the wire carrier board to avoid board damage or chip falling off; at least two metal pillars are formed on the electrical contact pads of the first conductive circuit layer, 2) the metal pillars (buried fingers) ) Higher than the surface of the dielectric layer to avoid poor wiring.

In summary, the present invention has indeed met the requirements for an invention patent, and a patent application was filed in accordance with the law. However, the above are only preferred embodiments of the present invention, and the scope of patent application in this case cannot be limited by this. For example, those who are familiar with the skills of this case and equivalent modifications or changes made according to the spirit of the present invention should be covered by the following patent applications.

Claims (2)

A method for manufacturing a packaging structure includes the following steps: providing a carrier board including a core board and a copper foil layer formed on a surface of the core board; on a surface of the copper foil layer remote from the core board Forming the conductive circuit layer thereon, the conductive circuit layer including at least two electrical contact pads; and forming a dielectric layer on a surface of the conductive circuit layer remote from the carrier board, so that the conductive circuit layer is embedded in the dielectric layer Inside; removing the core board and the copper foil layer; forming a solder resist layer on the surface of the conductive circuit layer, the solder resist layer including at least two first openings, each of the electrical contact pads from each of the first openings The inner part is exposed; a dry film layer is formed on the surface of the solder mask layer, the dry film layer covers part of the first opening, and at least two third openings are formed on the dry film layer, each of the electrical contact pads is from each The three openings are exposed; copper is plated in each of the third openings by vertical plating to form the metal pillars; the dry film layer is peeled off; and at least one wafer is provided, and at least one The chip is electrically connected to At least two of the metal posts. The manufacturing method of the package structure according to item 1 of the claim, wherein, while providing at least one step of the wafer, the method further comprises the steps of: providing a colloid and covering the wafer with the encapsulant.