CN108231737A - 用于减少硅通孔电容变异性的具有改良衬底接触的硅通孔 - Google Patents

用于减少硅通孔电容变异性的具有改良衬底接触的硅通孔 Download PDF

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CN108231737A
CN108231737A CN201711321298.6A CN201711321298A CN108231737A CN 108231737 A CN108231737 A CN 108231737A CN 201711321298 A CN201711321298 A CN 201711321298A CN 108231737 A CN108231737 A CN 108231737A
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J·M·萨夫兰
J·N·恩杜马洛
刘觉
S·罗森布拉特
C·科桑达拉曼
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Abstract

本发明揭示用于减少硅通孔电容变异性的具有改良衬底接触的硅通孔，其涉及半导体结构，并且特别涉及具有改良型衬底接触的贯穿硅通孔(TSV)结构及制造方法。该结构包括：第一物种类型的衬底；位在该衬底上的一层不同物种类型；贯穿该衬底所形成、并包含绝缘体侧壁及导电填充材料的贯穿衬底通孔；相邻该贯穿衬底通孔的第二物种类型；与该层不同物种类型电接触的第一接触；以及与该贯穿衬底通孔的该导电填充材料电接触的第二接触。

Description

用于减少硅通孔电容变异性的具有改良衬底接触的硅通孔
技术领域
本发明涉及半导体结构，并且特别涉及具有改良型衬底接触的贯穿硅通孔(through-silicon via；TSV)结构及制造方法。
背景技术
贯孔是一种介于实体电子电路中布线结构(例如：布线层)之间的电连接，其贯穿一或多个相邻的层的平面。举例而言，在集成电路设计中，贯孔是绝缘氧化物层中的小型开口，在不同布线层之间提供导电性连接。将最下层的金属连接至扩散或多晶的贯孔一般称为「接触」。贯穿硅通孔(TSV)是一种完全通过硅晶片或晶粒的垂直电连接(贯孔)。
TSV电浆处理造成相邻于TSV的半导体(硅)材料出现耗尽区。此耗尽导致衬底接触不良，而且还造成TSV的电气特性出现变异性。此变异性影响携载中至高频信号的能力。更具体地说，TSV程序产生MOS电容器与TSV氧化物电容器串联现象。半导体(硅)衬底中的耗尽/反型现象使TSV(其用于携载高频信号)的阻抗增加。尽管氧化物电容因几何形态而固定，串联电容仍随着掺杂与处理而变。
发明内容
在本发明的一态样中，一种结构包含：第一物种类型的衬底；一层不同物种类型，位在该衬底上；贯穿衬底通孔，贯穿该衬底所形成、并包含绝缘体侧壁及导电填充材料；第二物种类型，相邻该贯穿衬底通孔；与第一接触，该层不同物种类型电接触；以及第二接触，与该贯穿衬底通孔的该导电填充材料电接触。
在本发明的一态样中，一种结构包含：p型衬底；N+层，位在该衬底上；贯穿衬底通孔，贯穿该衬底所形成、并包含绝缘体侧壁及导电填充材料、且通过n型物种所围绕；第一接触，与该N+层直接电接触、并通过该绝缘体侧壁与该导电填充材料隔离；以及第二接触，与该贯穿衬底通孔的该导电填充材料电接触。
在本发明的一态样中，一种方法包含：形成位在该衬底上的一层第一物种类型；在形成贯孔结构期间将该衬底从第一材料类型转换成第二材料类型；形成与该层第一物种类型直接电接触的第一接触；以及形成与该贯孔结构的导电填充材料电接触的第二接触。
附图说明
本发明是通过本发明例示性具体实施例的非限制性实施例，参照注记的多个图式，在以下详细说明中作说明。
图1根据本发明的态样，展示具有N型注入层的半导体衬底。
图2根据本发明的态样，展示除了其它特征以外还具有N+转换的贯孔结构。
图3根据本发明的态样，展示填充有绝缘体及导电材料的贯孔结构。
图4根据本发明的态样，展示使受填充贯孔结构与N型注入层接触的接触。
图5展示图4中代表性所示结构与习知贯穿硅通孔结构之间的电容变异性比较图。
主要组件符号说明
10 结构
12 衬底或半导体衬底
14 N+层
16 贯孔结构
16' 贯穿硅通孔(TSV)
18 n型材料、n型半导体或TSV N+层
20 绝缘体材料或绝缘体层
22 导电材料
24 绝缘体层
26a 接触
26b 接触。
具体实施方式
本发明涉及半导体结构，并且特别涉及具有改良型衬底接触的贯穿硅通孔(TSV)结构及制造方法。更具体地说，本文中所述的TSV结构提供用于使晶粒间及跨布所有频率的TSV电容变异性减少的改良型接触。因此，且有助益的是，对于因TSV电浆刻蚀程序而使p型半导体(硅)衬底转换成n型所造成的TSV阻抗变异性，本文中所述的TSV结构提供一种解决方案。
TSV的电容可随着不同晶片及不同晶粒而变。举例而言，TSV若是通过BOSCH程序所制造，发现p型半导体(硅)衬底会转换成n型半导体(硅)。这通过扫描电容显微术(ScanningCapacitance Microscopy；SCM)而得到确认，假设前提是，硼错合物(例如：n型物种)的形成表现与n型杂质相似。此外，C-V特性分析显示半导体(硅)中存在N型层。然而，通过利用本文中所述的N型注入层，现有可能对TSV附近的衬底产生改良型接触。具体而言，N型注入层产生均匀的TSV电容。
本发明的具有改良型衬底接触的TSV结构可使用若干不同工具按照若干方式来制造。不过，一般来说，该等方法及工具用于形成微米及纳米级尺寸的结构。用于制造本发明的具有改良型衬底接触的TSV结构的方法(即技术)已获得集成电路(IC)技术采用。举例而言，此等结构建置于晶片上，并且在晶片的顶端通过光微影制程所图案化的材料膜中实现。特别的是，制作该等具有改良型衬底接触的TSV结构使用了三个基本建构块：(i)在衬底上沉积材料薄膜，(i i)通过光微影成像术在膜上涂敷图案化遮罩，以及(i ii)选择性地对遮罩进行膜的刻蚀。
图1根据本发明的态样，展示具有N型注入物的半导体衬底。更具体地说，图1中所示的结构10包括半导体衬底12。在具体实施例中，衬底12可以是由任何合适的含Si材料所组成的p型衬底，包括但不局限于Si、SiGe、SiGeC及SiC，这里仅列举数例。举例来说，衬底12可以是主体(bulk)衬底或绝缘体上硅(SOI)衬底。
在具体实施例中，N+层14是在衬底12中形成，较佳是在TSV图案化及接触形成的区域中形成。在SOI实施例中，N+层14会在绝缘体层(例如：埋置型氧化物层)下面形成。亦即，在SOI实作态样中，举例而言，N带部(N-band)注入物是在埋置型氧化物绝缘体下面建立，并且毗连通过TSV插置程序所建立的n层。
在更特定具体实施例中，N+层14可使用n型注入物，例如砷及磷，通过离子注入程序或扩散层程序所形成。在具体实施例中，离子注入程序将会是产生N+层14(例如：N+带部层14)的深离子注入。如所属领域技术人员应该理解的是，离子之能量、以及靶材(例如：衬底12)的离子物种与组成判定衬底12中离子的穿透深度。举例而言，离子注入程序的典型离子能量的范围可以是1keV至10keV；但其它能量也在本文的考量范围内。离子注入的深度会导致再穿透数纳米，例如：介于约10nm至约1μm之间。
在图2中，贯孔结构16是在衬底12中使用标准刻蚀程序所形成，该等标准刻蚀程序将p型衬底12转换成相邻于贯孔结构16的n型材料18。更具体地说，在具体实施例中，形成贯孔结构16所藉用的是反应性离子刻蚀(reactive ion etching；RIE)程序，并且更特别的是要藉用BOSCH程序，例如：脉冲式或经时间复用处理的刻蚀程序，此程序在两种模式之间反复交替，用以得到几乎垂直的贯孔结构16。
举更特定的实施例来说，在第一模式中，进行标准、几乎各向同性的电浆刻蚀，例如：六氟化硫(SF6)，后面跟着沉积化学惰性钝化层(使用例如C4F8(八氟环丁烷)来源气体，用以产生类似于聚四氟乙烯
(Teflon)之物质)的第二模式。在具体实施例中，钝化层将会保护衬底12免于化学侵蚀，并且防止进一步刻蚀衬底12。据信在第一模式中，电浆含有从几乎垂直方向侵蚀衬底12的离子，将p型衬底转换成相邻于贯孔结构16的n型半导体(硅)18，例如：贯孔结构16的底端及侧壁。相邻于贯孔结构16的n型半导体(硅)18与N+层14电气且直接接触。此刻蚀/沉积步骤反复进行许多次，导致仅在受刻蚀凹坑的底端处进行大量非常小的各向同性刻蚀步骤。
如图3所示，贯孔结构16与绝缘体材料20排齐，并且填充有导电材料22。在具体实施例中，绝缘体材料20是氧化物材料，使用习知沉积方法所沉积。举例而言，绝缘体材料20可通过化学气相沉积
(chemical vapor deposition；CVD)在贯孔结构16的侧壁及底端上沉积。衬垫(liner)沉积过后，可在贯孔结构16中沉积导电材料22，例如：铜、钨、铝等。导电材料22可通过习知的CVD程序来沉积，后面跟着化学机械抛光(chemical mechanical polishing；CMP)，用以将导电材料22及绝缘体材料20从衬底12的表面移除。在具体实施例中，绝缘体材料20将会在导电材料22与N+层14之间提供电隔离。
如图4所示，衬底12的背面经由薄化程序，例如：研磨程序，用以形成贯穿硅通孔16'。衬底12的正面上沉积绝缘体层24，例如：层间介电层，而衬底12中形成接触26a及26b，分别接触N+层14及TSV16'的敷金属(metallization)。在具体实施例中，N+层14位在“受排除区域”内，例如：TSV 16'的周界外侧。因此，电路中若使用TSV 16'，接触26a可为电路接地接触，例如：与接地平面接触，直接连接至N+层14，例如：NB注入块，相邻于TSV 16'的绝缘体层20。此外，由于TSV N+层18位于TSV 16'的局部处(例如：估计位于离TSV 16'约0.3μm处)，N+层14将会呈良好的电接触而形成可靠的TSV电容器。按照这种方式，接触26a可当作欧姆接触用于对围绕TSV 16'的TSV N+层18进行静电控制，导致不同晶粒间及跨布诸频率的TSV电容值稳定。还有，使用接触26b将会避免p-n结介面及其串联变异性。
仍请参阅图4，接触26a及26b可通过所属领域技术人员已知的习知微影、刻蚀及沉积程序所形成。更具体地说，衬底12上方沉积绝缘体层24之后，使绝缘体层24上方形成的阻剂曝露至能量(光)以形成图案(开口)。用到选择性化学作用的刻蚀程序(例如：反应性离子刻蚀(RIE))将用于贯穿阻剂的开口在绝缘体层24中形成一或多个沟槽。阻剂可接着通过习知的氧气灰化程序或其它已知的条化剂(stripant)来移除。阻剂移除过后，导电材料可通过任何习知的沉积程序来沉积，例如：化学气相沉积(CVD)程序，用以形成接触26a、26b。绝缘体层24的表面上的任何残余材料可通过习知的化学机械抛光(CMP)程序来移除。
图5展示图4中代表性所示结构与习知贯穿硅通孔结构之间的电容变异性比较图。在图5中，Y轴是电容而X轴是电压。此外，上图“A”是根据本文所述态样的结构；而下图“B”是习知结构，例如：无接触的N+层的结构。如图所示，在“A”中，注意区中就本文所述结构有因低偏压引起的小电容变异性。经过比较，在“B”所示的习知结构中，如代表不同测试晶粒的数条线的垂直范围、以及图中各处线条彼此之间隔所示，有非常大的电容变异性。
本方法如以上所述，用于制作集成电路晶片。产生的集成电路晶片可由制造商以空白晶片形式(也就是说，作为具有多个未封装晶片的单一晶片)、当作裸晶粒、或以封装形式来配送。在后例中，晶片嵌装于单晶片封装(例如：塑胶载体，有引线粘贴至母板或其它更高层次载体)中、或多芯片封装(例如：具有表面互连或埋置型互连任一者或两者的陶瓷载体)中。在任一例子中，该芯片接着与其它芯片、离散电路元件、及/或其它信号处理装置整合成下列的部分或任一者：(a)诸如母板的中间产品，或(b)最终产品。最终产品可以是任何包括集成电路芯片的产品，范围涵盖玩具及其它具有显示器、键盘或其它输入装置的低阶应用至进阶电脑产品、以及中央处理器。
本发明的各项具体实施例已为了说明而介绍，但不是意味着穷举或受限于所揭示的具体实施例。许多修改及变例对于所属领域技术人员将会显而易知，但不会脱离所述具体实施例的范畴及精神。本文中使用的术语是为了最佳阐释具体实施例的原理、对市场出现的技术所作的实务应用或技术改良、或让所属领域技术人员能够理解本文中所揭示的具体实施例而选择。

Claims (20)

1.一种结构，其特征为，该结构包含：
第一物种类型的衬底；
一层不同物种类型，位在该衬底上；
贯穿衬底通孔，贯穿该衬底所形成、并包含绝缘体侧壁及导电填充材料；
第二物种类型，相邻该贯穿衬底通孔；
第一接触，与该层不同物种类型电接触；以及
第二接触，与该贯穿衬底通孔的该导电填充材料电接触。
2.如权利要求1所述的结构，其特征为，该衬底是Si材料。
3.如权利要求1所述的结构，其特征为，该衬底是主体衬底。
4.如权利要求1所述的结构，其特征为，该衬底是绝缘体上硅(SOI)，而该层不同物种类型是位于该绝缘体下面。
5.如权利要求1所述的结构，其特征为，该层不同物种类型是N+层，其围绕该贯穿衬底通孔、并通过该绝缘体侧壁与该导电填充材料电隔离、且耦合至相邻该贯穿衬底通孔的该第二物种类型。
6.如权利要求1所述的结构，其特征为，该第一物种类型属于P型且该第二物种类型属于n型。
7.如权利要求1所述的结构，其特征为，该第一接触与该层不同物种类型直接电接触。
8.如权利要求1所述的结构，其特征为，该第一接触是欧姆接触，用于对围绕该贯穿衬底通孔的该层不同物种类型进行静电控制。
9.一种结构，其特征为，该结构包含：
p型衬底；
N+层，位在该衬底上；
贯穿衬底通孔，贯穿该衬底所形成、并包含绝缘体侧壁及导电填充材料、且由n型物种所围绕；
第一接触，与该N+层直接电接触、并通过该绝缘体侧壁与该导电填充材料隔离；以及
第二接触，与该贯穿衬底通孔的该导电填充材料电接触。
10.如权利要求9所述的结构，其特征为，该p型衬底是Si材料。
11.如权利要求9所述的结构，其特征为，该p型衬底是主体衬底。
12.如权利要求9所述的结构，其特征为，该p型衬底是绝缘体上硅(SOI)，而该N+层是位于该绝缘体下面。
13.如权利要求9所述的结构，其特征为，该第一接触是欧姆接触，用于对围绕该贯穿衬底通孔的该N+层进行静电控制。
14.一种方法，其特征为，该方法包含：
形成位在该衬底上的一层第一物种类型；
在形成贯孔结构期间将该衬底从第一材料类型转换成第二材料类型；
形成与该层第一物种类型直接电接触的第一接触；以及
形成与该贯孔结构的导电填充材料电接触的第二接触。
15.如权利要求14所述的方法，其特征为，该层第一物种类型是N+层，其通过该贯孔结构中所形成的该绝缘体侧壁与该导电填充材料隔离。
16.如权利要求15所述的方法，其特征为，该贯孔结构是通过BOSCH刻蚀程序所形成，并且填充有绝缘体衬垫及该导电填充材料。
17.如权利要求16所述的方法，其特征为，该第一接触是通过该绝缘体侧壁与该导电填充材料隔离，其沿该贯孔结构的多个侧壁排齐。
18.如权利要求16所述的方法，其特征为，该绝缘体侧壁是设于该导电填充材料与该N+层之间。
19.如权利要求16所述的方法，其中，该N+层是通过离子注入程序所形成。
20.如权利要求16所述的方法，其特征为，该贯孔结构是贯穿式贯孔结构，通过研磨该衬底的背面所形成。
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