CN108231706B - Power semiconductor device packaging structure and packaging method - Google Patents
Power semiconductor device packaging structure and packaging method Download PDFInfo
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- CN108231706B CN108231706B CN201711444169.6A CN201711444169A CN108231706B CN 108231706 B CN108231706 B CN 108231706B CN 201711444169 A CN201711444169 A CN 201711444169A CN 108231706 B CN108231706 B CN 108231706B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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Abstract
The embodiment of the invention provides a power semiconductor device packaging structure and a packaging method, wherein the power semiconductor device packaging structure comprises: at least one package sub-module, the package sub-module comprising: the power chip is arranged on the lower metal sheet, the upper metal sheet is clamped in the positioning frame and is arranged on the power chip together with the positioning frame, the size of the upper metal sheet is not smaller than that of the lower metal sheet, and the size difference between the size of the upper metal sheet and the size of the lower metal sheet is smaller than a preset difference value, so that the area of the upper metal sheet is equivalent to that of the lower metal sheet, the bending of the chip in the power semiconductor device is effectively reduced, the failure of the chip due to crack generation and even brittle fracture generation is avoided, and the reliability of the power semiconductor device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor device packaging, in particular to a power semiconductor device packaging structure and a packaging method.
Background
Insulated Gate Bipolar Transistors (IGBTs) have the advantages of large input impedance, small driving power, simple control circuit, small switching loss, high switching speed, high operating frequency, large element capacity, no absorption circuit and the like, and are widely applied to the fields of industrial current transformation, electric power traction and the like. The compression joint packaging is the latest packaging form of the high-power IGBT, compared with the traditional welding type IGBT (soldered IGBT module), the compression joint type IGBT (Press-pack IGBT) realizes the thermodynamic and electrical connection by utilizing pressure, ensures the double-sided heat dissipation, has high reliability, is considered as an ideal device for high-power application occasions and application occasions with greatly fluctuated output power, can meet the requirements of high-voltage direct-current power transmission and new energy grid connection on a switch device, and can also meet the requirements of a power system on high reliability of power supply.
In a traditional rigid compression joint IGBT device structure, a collector and an emitter of a power chip are in direct contact with a rigid material, the collector is arranged on the back of the power chip according to the layout of a surface functional area of the power chip, and three areas, namely the emitter, an insulated terminal and a grid, are distributed on one side of the emitter on the front side, so that the area of the collector of the power chip is larger than that of the emitter. In the conventional crimping type IGBT device, the pressure areas applied by the rigid electrodes on both sides of the power chip are different, the pressure area of the rigid electrode on the collector side is often equal to the collector area itself, i.e., the pressure is uniformly distributed on all the surfaces of the collector, while the pressure area of the rigid electrode on the emitter side is equal to the emitter area, and the pressure is uniformly distributed on all the surfaces of the emitter.
When a device adopting the packaging structure bears pressure, the upper contact surface and the lower contact surface are not equal, so that the chip is bent. In the traditional packaging of the low-medium voltage and small-capacity IGBT device, because the size ratio of an insulated terminal is smaller, the influence of the packaging structure for asymmetrically applying pressure on two sides of the chip on the power chip is not obvious; however, as the IGBT device is required to be applied to an electric power system, higher requirements are placed on the voltage and the capacity of the chip, and in this background, as the voltage level is increased, the area ratio of the insulated terminal on the surface of the chip is increased, which causes the bending phenomenon of the chip to be more serious, and generates a larger tensile stress on the collector side of the chip. Because the chip is a brittle material, the tensile capacity of the brittle material is relatively weak, cracks are easily generated inside the chip, the chip is brittle, and the preparation and service reliability of the device are seriously threatened.
Disclosure of Invention
In view of the above analysis, the embodiment of the invention provides a power semiconductor device packaging structure and a packaging method, which are used for solving the problems that in the existing packaging structure, the pressure bearing areas of the upper side and the lower side of a chip are greatly different, so that the chip is seriously bent, the chip fails due to cracks and even brittle fracture, and the preparation and service reliability of the device are seriously threatened.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
an embodiment of the present invention provides a power semiconductor device package structure, including: at least one encapsulation submodule, the encapsulation submodule includes: the device comprises an upper metal sheet, a positioning frame, a power chip and a lower metal sheet; the power chip is arranged on the lower metal sheet; the upper metal sheet is clamped in the positioning frame and is arranged on the power chip together with the positioning frame; the size of the upper metal sheet is not smaller than that of the lower metal sheet, and the size difference between the upper metal sheet and the lower metal sheet is smaller than a preset difference value.
In one embodiment, the package sub-module further comprises: the top of the insulating frame is in a buckle shape, the first end of the connecting piece is fixed in the positioning through hole of the insulating frame, and the second end of the connecting piece is connected to the first electrode of the power chip.
In one embodiment, the connector is a spring probe.
In one embodiment, the package sub-module further comprises: and the support sheet is arranged below the lower metal sheet and is fixed in the insulating frame together with the upper metal sheet, the positioning frame, the power chip and the lower metal sheet.
In one embodiment, the power semiconductor device package structure further includes: the lower cover plate is provided with a plurality of metal bosses, the encapsulation sub-modules are fixedly arranged on the metal bosses, and the metal bosses and the encapsulation sub-modules are arranged in a one-to-one correspondence mode.
In one embodiment, the power semiconductor device package structure further includes: and the PCB is arranged on the upper surface of the lower cover plate and is connected with the connecting piece.
In one embodiment, the power semiconductor device package structure further includes: and the leading-out piece is fixedly connected to the PCB, and leads out the first electrode of the power chip to the side surface of the power semiconductor packaging structure through the connecting piece and the PCB.
In one embodiment, the power semiconductor device package structure further includes: and the upper cover plate is in compression joint with the plurality of packaging sub-modules and is in insulation connection with the lower cover plate.
The embodiment of the invention also provides a packaging method of the power semiconductor device, which comprises the following steps: obtaining a packaged sub-module, the obtaining the packaged sub-module comprising: arranging a power chip on the lower metal sheet; and clamping an upper metal sheet in a positioning frame, and arranging the upper metal sheet and the positioning frame on the power chip together, wherein the size of the upper metal sheet is not smaller than that of the lower metal sheet, and the size difference between the upper metal sheet and the lower metal sheet is smaller than a preset difference value.
In an embodiment, before disposing the power chip on the lower metal sheet in the obtained package sub-module, the method further includes: fixing a first end of a connecting piece in a positioning through hole of the insulating frame; fixing a support sheet in the insulating frame; and arranging the lower metal sheet on the supporting sheet.
In an embodiment, the obtaining the package sub-module further includes: and connecting the second end of the connecting piece to the first electrode of the power chip.
In an embodiment, after obtaining the encapsulation sub-module, the method further includes: arranging a PCB on the upper surface of the lower cover plate; fixedly arranging a plurality of the packaging sub-modules on a plurality of metal bosses on the lower cover plate, wherein the plurality of the packaging sub-modules and the plurality of the metal bosses are arranged in a one-to-one correspondence manner; connecting the PCB board with the connecting piece; fixedly connecting a leading-out piece with the PCB, and leading out a first electrode of the power chip to the side face of the power semiconductor packaging structure through the connecting piece, the PCB and the leading-out piece; and pressing an upper cover plate on the plurality of packaging sub-modules in a crimping manner, wherein the upper cover plate is connected with the lower cover plate in an insulating manner.
Compared with the prior art, the technical scheme of the invention at least has the following advantages:
the embodiment of the invention provides a power semiconductor device packaging structure and a packaging method, wherein the power semiconductor device packaging structure comprises: at least one package sub-module, the package sub-module comprising: the power chip is arranged on the lower metal sheet, the upper metal sheet is clamped in the positioning frame and is arranged on the power chip together with the positioning frame, the size of the upper metal sheet is not smaller than that of the lower metal sheet, and the size difference between the size of the upper metal sheet and the size of the lower metal sheet is smaller than a preset difference value, so that the area of the upper metal sheet is equivalent to that of the lower metal sheet, the bending of the chip in the power semiconductor device is effectively reduced, the chip is prevented from generating cracks and even brittle fracture, and the reliability of the power semiconductor device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a cross-sectional view of one embodiment of a packaged sub-module in accordance with the present invention;
FIG. 2 is a cross-sectional view of another embodiment of a packaged sub-module in accordance with an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an exemplary package sub-module according to an embodiment of the invention;
FIG. 4 is a schematic structural diagram of another embodiment of a package sub-module according to an embodiment of the invention;
FIG. 5 is a schematic structural diagram of another embodiment of a package sub-module according to an embodiment of the invention;
fig. 6 is a sectional view of a specific example of a power semiconductor device package structure in an embodiment of the present invention;
FIG. 7 is a flowchart illustrating an exemplary method for encapsulating a sub-module according to an embodiment of the present invention;
FIG. 8 is a flow chart of another embodiment of a packaged sub-module according to the present invention;
fig. 9 is a flowchart of a specific example of a packaging method of a power semiconductor device in the embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the term "connected" is to be interpreted broadly, e.g. as a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present invention provides a power semiconductor device package structure, as shown in fig. 1, the power semiconductor device package structure includes: at least one encapsulation submodule, the encapsulation submodule includes: an upper metal sheet 11, a positioning frame 12, a power chip 13 and a lower metal sheet 14; the power chip 13 is arranged on the lower metal sheet 14; the upper metal sheet 11 is clamped in the positioning frame 12 and is arranged on the power chip 13 together with the positioning frame 12; the size of the upper metal sheet 11 is not smaller than that of the lower metal sheet 14, and the difference between the size of the upper metal sheet 11 and the size of the lower metal sheet 14 is smaller than a preset difference.
By adopting the positioning frame 12, the area of the upper metal sheet 11 is reduced, the area of the upper metal sheet 11 can be equivalent to that of the lower metal sheet 14, the bending of a chip in the power semiconductor device is effectively reduced, the failure of the chip due to crack generation and even brittle fracture is avoided, the reliability of the power semiconductor device is improved, and the stress reliability of the chip in packaging and service can be obviously improved for the chip with high voltage level (more than 3300V) and large capacity (more than 50A), particularly for the chip with larger insulating terminal at the side of an emitter; on the other hand, the positioning and installation of the upper metal sheet 11 can be realized, so that the upper metal sheet 11 is fixed at the central position of the power chip 13.
In a preferred embodiment, in order to prevent the power chip 13 from being damaged by thermal stress generated by thermal mismatch due to a difference in thermal expansion coefficient between different materials when the power chip 13 is subjected to a temperature cycling condition, the upper metal sheet 11 and the lower metal sheet 14 are made of the same material, which may be metal molybdenum or a metal-matrix composite kovar alloy, which may be an alloy of metal molybdenum and silicon or an alloy of metal molybdenum and aluminum, and the thermal expansion coefficients of the upper metal sheet 11 and the lower metal sheet 14 are close to the thermal expansion coefficient of the power chip 13, which may be 6 ± 2ppm/° c, so as to improve reliability of the power chip 13 against temperature cycling and power cycling. Alternatively, in some embodiments of the present invention, the upper metal sheet 11 and the lower metal sheet 14 have the same shape and may be square.
As shown in fig. 2, 3, 4 and 5, the package sub-module further includes: the insulating frame 17, optionally, in some embodiments of the present invention, the insulating frame 17 and the positioning frame 12 are made of the same material, in this case, the material is a thermoplastic polymer resistant to high temperature above 200 ℃, and may be polyetheretherketone, polyphenylene sulfide, polybutylene terephthalate, or other materials; in other embodiments of the present invention, the insulating frame 17 and the positioning frame 12 may also be made of different materials, and at this time, the hardness of the insulating frame 17 should be greater than that of the positioning frame 12, so that the positioning frame 12 absorbs the stress of the insulating frame 17, thereby playing a role of buffering and ensuring the reliability of the device package. In a preferred embodiment, the top of the insulating frame 17 is in a snap shape, so as to ensure that the positioning frame 12 is not easy to loosen and fall off after being installed in the insulating frame 17, thereby improving the stability and reliability of the structure.
As shown in fig. 2, 3 and 4, the package sub-module further includes: and a connecting piece 16, wherein a first end of the connecting piece 16 is fixed in the positioning through hole of the insulating frame 17, and a second end of the connecting piece 16 is connected to the first electrode of the power chip 13. Alternatively, in some embodiments of the present invention, the connector 16 may be a spring probe, the top metal of which is electrically connected to the first electrode of the power chip 13. Alternatively, in some embodiments of the present invention, the power chip 13 may be an Insulated Gate Bipolar Transistor (IGBT), and in this case, the first electrode is a gate. Optionally, in other embodiments of the present invention, the power chip 13 may also be a Fast Recovery Diode (FRD).
As shown in fig. 2, 3 and 4, the package sub-module further includes: the supporting sheet 15 is disposed below the lower metal sheet 14 and fixed in the insulating frame 17 together with the upper metal sheet 11, the positioning frame 12, the power chip 13 and the lower metal sheet 14, and optionally, in some embodiments of the present invention, the upper metal sheet 11 and the power chip 13, the power chip 13 and the lower metal sheet 14, and the lower metal sheet 14 and the supporting sheet 15 may be disposed by a sintering process or may be directly stacked to achieve physical contact. The material of the support sheet 15 has good heat conduction and electrical conductivity and lower hardness, because the high-voltage high-power chip heats seriously during operation, the material with good heat conduction and electrical conductivity is selected to reduce thermal resistance and reduce junction temperature of the power chip 13 during service, and the processing errors of different parts can influence the heights of different packaging sub-modules, so that the stress among the sub-modules is not uniform in the crimping process, and the support sheet 15 with lower hardness can absorb the stress through deformation, thereby improving the stress distribution among different packaging sub-modules and ensuring that the stress among the packaging sub-modules is uniform. Optionally, in some embodiments of the present invention, the material of the support sheet 15 may be gold, silver, carbon fiber, or graphene.
As shown in fig. 6, the power semiconductor device package structure provided in the embodiment of the present invention further includes: the lower cover plate 3 is provided with a plurality of metal bosses 31 on the lower cover plate 3, a plurality of encapsulation sub-modules are fixedly arranged on the plurality of metal bosses 31, and the plurality of metal bosses 31 and the plurality of encapsulation sub-modules are arranged in a one-to-one correspondence manner.
As shown in fig. 6, the power semiconductor device package structure provided in the embodiment of the present invention further includes: and a PCB 4 disposed on an upper surface of the lower cover 3 and connected to the connector 16. Specifically, be provided with on the PCB board 4 with the metal boss 31 one-to-one setting on the lower cover plate 3 opening for metal boss 31 can pass PCB board 4, and the root (bottom) metal of connecting piece 16 sets up in the wiring district of PCB board 4, realizes electrical connection with PCB board 4. Alternatively, in some embodiments of the present invention, the PCB 4 may be disposed on the upper surface of the lower cover plate 3 by bolts, or may be welded on the upper surface of the lower cover plate 3.
As shown in fig. 6, the power semiconductor device package structure provided in the embodiment of the present invention further includes: and a lead-out member 5, wherein the lead-out member 5 is provided for leading out an electrode of the power chip 13, and for an Insulated Gate Bipolar Transistor (IGBT), a gate electrode of the IGBT is led out, and the lead-out member 5 is fixedly connected to the PCB 4, and the gate electrode of the IGBT is led out to a side surface of the power semiconductor package structure through the connector 16 and the PCB 4. Alternatively, in some embodiments of the present invention, the lead-out member 5 and the PCB 4 may be fixedly connected by soldering or bolting.
As shown in fig. 6, the power semiconductor device package structure provided in the embodiment of the present invention further includes: and the upper cover plate 2 is pressed on the plurality of packaging sub-modules and is in insulation connection with the lower cover plate 3. Alternatively, in some embodiments of the present invention, the upper cover plate 2 and the lower cover plate 3 may be connected by direct pressure welding using a cold pressure welding process, or the upper cover plate 2 and the lower cover plate 3 may be welded at their peripheries respectively using an argon arc welding process, and the upper cover plate 2 and the lower cover plate 3 are insulated from each other, and the insulating material used may be ceramic (alumina or aluminum nitride). Optionally, in some embodiments of the present invention, the material of the upper cover plate 2 and the lower cover plate 3 may be a highly conductive metal material or a metal matrix composite material, and may be oxygen-free copper, kovar alloy or copper alloy, and the surfaces of the upper cover plate 2 and the lower cover plate 3 are respectively plated with nickel. Alternatively, the upper cover plate 2 and the lower cover plate 3 are identical in shape and may be circular or square.
The power semiconductor device packaging structure provided by the embodiment of the invention comprises a plurality of packaging sub-modules, and in specific application, the packaging of the power semiconductor devices with different current levels can be realized by changing the number of the packaging sub-modules, and when the current level requirement on the power semiconductor devices is higher, the capacity expansion of the power semiconductor devices can be realized by increasing the parallel connection number of the packaging sub-modules.
An embodiment of the present invention further provides a packaging method for a power semiconductor device, as shown in fig. 7, the packaging method for a power semiconductor device includes: step S1: obtaining a packaged sub-module, specifically, the step S1 includes the following steps:
step S11: the power chip 13 is disposed on the lower metal sheet 14.
Step S12: the upper metal sheet 11 is clamped in the positioning frame 12 and is arranged on the power chip 13 together with the positioning frame 12, the size of the upper metal sheet 11 is not smaller than that of the lower metal sheet 14, and the size difference between the size of the upper metal sheet 11 and the size of the lower metal sheet 14 is smaller than a preset difference.
Through the steps S11 and S12, the power semiconductor device is packaged by the positioning frame 12, so that the area of the upper metal sheet 11 is reduced, the area of the upper metal sheet 11 is equivalent to that of the lower metal sheet 14, the bending of a chip in the power semiconductor device is effectively reduced, the failure of the chip due to cracks and even brittle failure is avoided, the reliability of the power semiconductor device is improved, and the stress reliability of the chip in packaging and service can be obviously improved for the chips with high voltage level (above 3300V) and large capacity (above 50A), particularly the chips with large insulating terminals on the emitter side; on the other hand, the positioning and installation of the upper metal sheet 11 can be realized, so that the upper metal sheet 11 is fixed at the central position of the power chip 13.
In a preferred embodiment, in order to prevent the power chip 13 from being damaged by thermal stress generated by thermal mismatch due to a difference in thermal expansion coefficient between different materials when the power chip 13 is subjected to a temperature cycling condition, the upper metal sheet 11 and the lower metal sheet 14 are made of the same material, which may be metal molybdenum or a metal-matrix composite kovar alloy, which may be an alloy of metal molybdenum and silicon or an alloy of metal molybdenum and aluminum, and the thermal expansion coefficients of the upper metal sheet 11 and the lower metal sheet 14 are close to the thermal expansion coefficient of the power chip 13, which may be 6 ± 2ppm/° c, so as to improve reliability of the power chip 13 against temperature cycling and power cycling. Alternatively, in some embodiments of the present invention, the upper metal sheet 11 and the lower metal sheet 14 have the same shape and may be square.
Optionally, in some embodiments of the present invention, as shown in fig. 8, before disposing the power chip 13 on the lower metal sheet 14 in step S11, in step S1 of obtaining the packaged sub-module, the method further includes:
step S13: a first end of a connector 16 is fixed in the positioning through hole of the insulating frame 17, and the connector 16 may be a spring probe.
Step S14: a support sheet 15 is fixed in the insulating frame 17. The material of the support sheet 15 has good heat conduction and electrical conductivity and lower hardness, because the high-voltage high-power chip heats seriously during operation, the material with good heat conduction and electrical conductivity is selected to reduce thermal resistance and reduce junction temperature of the power chip 13 during service, and the processing errors of different parts can influence the heights of different packaging sub-modules, so that the stress among the sub-modules is not uniform in the crimping process, and the support sheet 15 with lower hardness can absorb the stress through deformation, thereby improving the stress distribution among different packaging sub-modules and ensuring that the stress among the packaging sub-modules is uniform. Optionally, in some embodiments of the present invention, the material of the support sheet 15 may be gold, silver, carbon fiber, or graphene.
Step S15: the lower metal sheet 14 is disposed on the support sheet 15.
Optionally, in some embodiments of the present invention, the insulating frame 17 and the positioning frame 12 are made of the same material, in this case, the material is a thermoplastic polymer resistant to high temperature above 200 ℃, and may be polyetheretherketone, polyphenylene sulfide, polybutylene terephthalate, or other materials; in other embodiments of the present invention, the insulating frame 17 and the positioning frame 12 may also be made of different materials, and at this time, the hardness of the insulating frame 17 should be greater than that of the positioning frame 12, so that the positioning frame 12 absorbs the stress of the insulating frame 17, thereby playing a role of buffering and ensuring the reliability of the device package. In a preferred embodiment, the top of the insulating frame 17 is in a snap shape, so as to ensure that the positioning frame 12 is not easy to loosen and fall off after being installed in the insulating frame 17, thereby improving the stability and reliability of the structure.
Optionally, in some embodiments of the present invention, as shown in fig. 8, in the step S1 of obtaining the package sub-module, the method further includes: step S16: the second end of the connection member 16 is connected to the first electrode of the power chip 13. Alternatively, in some embodiments of the present invention, the connector 16 may be a spring probe, the top metal of which is electrically connected to the first electrode of the power chip 13. Alternatively, in some embodiments of the present invention, the power chip 13 may be an Insulated Gate Bipolar Transistor (IGBT), and in this case, the first electrode is a gate. Optionally, in other embodiments of the present invention, the power chip 13 may also be a Fast Recovery Diode (FRD).
Through the above steps S11-S16, the connector 16, the support sheet 15, the lower metal sheet 14, the power chip 13, the positioning frame 12 and the upper metal sheet 11 are assembled into the insulating frame 17, so that the assembly of the single package sub-module is realized. Optionally, in some embodiments of the present invention, the upper metal sheet 11 and the power chip 13, the power chip 13 and the lower metal sheet 14, and the lower metal sheet 14 and the support sheet 15 may be disposed by a sintering process, or may be directly stacked to achieve physical contact.
As shown in fig. 9, after obtaining the package submodule through the steps S11 to S16, the method for packaging a power semiconductor device according to the embodiment of the present invention further includes:
step S2: the PCB board 4 is disposed on the upper surface of the lower cover plate 3. Specifically, the PCB 4 is provided with openings corresponding to the metal bosses 31 of the lower cover plate 3 one to one, so that the metal bosses 31 can penetrate through the PCB 4. Alternatively, in some embodiments of the present invention, the PCB 4 may be disposed on the upper surface of the lower cover plate 3 by bolts, or may be welded on the upper surface of the lower cover plate 3.
Step S3: a plurality of sub-modules are fixedly arranged on a plurality of metal bosses 31 on the lower cover plate 3, and the plurality of sub-modules and the plurality of metal bosses 31 are arranged in a one-to-one correspondence.
And step S4, connecting the PCB 4 with the connector 16, specifically, arranging the metal at the root (bottom) of the connector 16 in the wiring area of the PCB 4 to electrically connect with the PCB 4.
Step S5: a leading-out part 5 is fixedly connected with the PCB 4, and the first electrode of the power chip 13 is led out to the side surface of the power semiconductor packaging structure through the connecting part 16, the PCB 4 and the leading-out part 5, alternatively, the leading-out part 5 and the PCB 4 can be fixedly connected by adopting a solder welding or bolt punching mode.
Step S6: and the upper cover plate 2 is pressed on the plurality of packaging sub-modules, and the upper cover plate 2 is connected with the lower cover plate 3 in an insulating way. Alternatively, in some embodiments of the present invention, the upper cover plate 2 and the lower cover plate 3 may be connected by direct pressure welding using a cold pressure welding process, or the upper cover plate 2 and the lower cover plate 3 may be welded at their peripheries respectively using an argon arc welding process, and the upper cover plate 2 and the lower cover plate 3 are insulated from each other, and the insulating material used may be ceramic (alumina or aluminum nitride). Alternatively, in some embodiments of the present invention, the material of the upper cover plate 2 and the lower cover plate 3 may be a highly conductive metal material or a metal matrix composite material, and may be oxygen-free copper, kovar alloy or copper alloy, and the surfaces of the upper cover plate 2 and the lower cover plate 3 are respectively plated with nickel. Alternatively, the upper cover plate 2 and the lower cover plate 3 are identical in shape and may be circular or square.
When the packaging method of the power device provided by the embodiment of the invention is specifically implemented, the number of different packaging sub-modules can be set according to actual needs, and when the requirement on the current level of the power semiconductor device is higher, the capacity expansion of the power semiconductor device can be realized by increasing the parallel connection number of the packaging sub-modules.
The above-mentioned numbers S1 to S6 do not limit the order of the method for packaging the power semiconductor device of the present invention, and the steps may be interchanged without conflict, and the present invention is not limited thereto.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (12)
1. A power semiconductor device package structure, comprising: at least one encapsulation submodule, the encapsulation submodule includes: the device comprises an upper metal sheet (11), a positioning frame (12), a power chip (13) and a lower metal sheet (14);
the power chip (13) is arranged on the lower metal sheet (14);
the upper metal sheet (11) is clamped in the positioning frame (12) and is arranged on the power chip (13) together with the positioning frame (12);
the size of the upper metal sheet (11) is not smaller than that of the lower metal sheet (14), and the size difference between the upper metal sheet (11) and the lower metal sheet (14) is smaller than a preset difference value, so that the area of the upper metal sheet (11) is equivalent to that of the lower metal sheet (14).
2. The power semiconductor device package structure of claim 1, wherein the package sub-module further comprises:
the power chip comprises an insulating frame (17) and a connecting piece (16), wherein the top of the insulating frame (17) is in a buckle shape, the first end of the connecting piece (16) is fixed in a positioning through hole of the insulating frame (17), and the second end of the connecting piece (16) is connected to a first electrode of the power chip (13).
3. The power semiconductor device package according to claim 2, wherein the connector (16) is a spring probe.
4. The power semiconductor device package structure of claim 2 or 3, wherein the package sub-module further comprises:
and the support sheet (15) is arranged below the lower metal sheet (14) and is fixed in the insulating frame (17) together with the upper metal sheet (11), the positioning frame (12), the power chip (13) and the lower metal sheet (14).
5. The power semiconductor device package structure of claim 4, further comprising:
the lower cover plate (3) is provided with a plurality of metal bosses (31), the plurality of packaging sub-modules are fixedly arranged on the plurality of metal bosses (31), and the plurality of metal bosses (31) and the plurality of packaging sub-modules are arranged in a one-to-one correspondence mode.
6. The power semiconductor device package structure of claim 5, further comprising:
and the PCB (4) is arranged on the upper surface of the lower cover plate (3) and is connected with the connecting piece (16).
7. The power semiconductor device package structure of claim 6, further comprising:
and the leading-out piece (5) is fixedly connected to the PCB (4), and leads out the first electrode of the power chip (13) to the side face of the power semiconductor packaging structure through the connecting piece (16) and the PCB (4).
8. The power semiconductor device package structure according to any one of claims 5 to 7, further comprising:
and the upper cover plate (2) is in compression joint with the plurality of packaging sub-modules and is in insulation connection with the lower cover plate (3).
9. A method of packaging a power semiconductor device, comprising: obtaining a packaged sub-module, the obtaining the packaged sub-module comprising:
arranging a power chip (13) on the lower metal sheet (14);
the method comprises the steps that an upper metal sheet (11) is clamped in a positioning frame (12) and is arranged on a power chip (13) together with the positioning frame (12), the size of the upper metal sheet (11) is not smaller than that of a lower metal sheet (14), and the size difference between the size of the upper metal sheet (11) and the size of the lower metal sheet (14) is smaller than a preset difference value, so that the area of the upper metal sheet (11) can be equivalent to that of the lower metal sheet (14).
10. The method for packaging a power semiconductor device according to claim 9, wherein the obtaining of the packaged sub-module further comprises, before disposing the power chip (13) on the lower metal sheet (14):
fixing a first end of a connecting piece (16) in a positioning through hole of an insulating frame (17);
fixing a support sheet (15) in the insulating frame (17);
-arranging the lower metal sheet (14) on the support sheet (15).
11. The method of claim 10, wherein the obtaining of the packaged sub-module further comprises:
connecting a second end of the connector (16) to a first electrode of the power chip (13).
12. The method for packaging a power semiconductor device according to claim 11, wherein after obtaining the packaging submodules, the method further comprises:
arranging a PCB (4) on the upper surface of the lower cover plate (3);
fixedly arranging a plurality of the packaging sub-modules on a plurality of metal bosses (31) on the lower cover plate (3), wherein the plurality of the packaging sub-modules and the plurality of the metal bosses (31) are arranged in a one-to-one correspondence manner;
connecting the PCB board (4) with the connecting piece (16);
fixedly connecting a leading-out piece (5) with the PCB (4), and leading out a first electrode of the power chip (13) to the side face of the power semiconductor packaging structure through the connecting piece (16), the PCB (4) and the leading-out piece (5);
and pressing an upper cover plate (2) on the plurality of packaging sub-modules, wherein the upper cover plate (2) is in insulation connection with the lower cover plate (3).
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| CN109273371A (en) * | 2018-09-28 | 2019-01-25 | 全球能源互联网研究院有限公司 | A kind of encapsulating structure of power semiconductor part and packaging method |
| CN109273372A (en) * | 2018-09-28 | 2019-01-25 | 全球能源互联网研究院有限公司 | A kind of encapsulating structure of power semiconductor part and packaging method |
| CN110211885B (en) * | 2019-05-30 | 2021-08-06 | 全球能源互联网研究院有限公司 | Power chip pre-packaging method, power chip pre-packaging structure, power chip pre-packaging method, power chip pre-packaging structure and wafer pre-packaging structure |
| CN110246814B (en) * | 2019-05-30 | 2021-07-06 | 全球能源互联网研究院有限公司 | Power chip pre-packaging method, power chip pre-packaging structure, power chip pre-packaging method, power chip pre-packaging structure and wafer pre-packaging structure |
| CN111508902B (en) * | 2020-04-26 | 2021-09-10 | 全球能源互联网研究院有限公司 | Insulation structure, insulation piece wrapping chip periphery and preparation method thereof |
| CN116090261B (en) * | 2023-04-07 | 2023-06-23 | 深圳平创半导体有限公司 | Stress field reconstruction method and system for crimping type power semiconductor device |
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