CN109273372A - A kind of encapsulating structure of power semiconductor part and packaging method - Google Patents
A kind of encapsulating structure of power semiconductor part and packaging method Download PDFInfo
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- CN109273372A CN109273372A CN201811146182.8A CN201811146182A CN109273372A CN 109273372 A CN109273372 A CN 109273372A CN 201811146182 A CN201811146182 A CN 201811146182A CN 109273372 A CN109273372 A CN 109273372A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 title abstract description 10
- 238000005538 encapsulation Methods 0.000 claims abstract description 23
- 239000012790 adhesive layer Substances 0.000 claims abstract description 14
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 12
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 12
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 9
- 239000000956 alloy Substances 0.000 claims description 9
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910000833 kovar Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 238000005245 sintering Methods 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 229920006332 epoxy adhesive Polymers 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims description 3
- 239000000741 silica gel Substances 0.000 claims description 3
- 229910002027 silica gel Inorganic materials 0.000 claims description 3
- 238000005452 bending Methods 0.000 abstract description 5
- 238000005336 cracking Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 20
- 230000035882 stress Effects 0.000 description 13
- 239000011733 molybdenum Substances 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 238000002788 crimping Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 229910001092 metal group alloy Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 208000037656 Respiratory Sounds Diseases 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 2
- 239000007767 bonding agent Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000001291 vacuum drying Methods 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920006335 epoxy glue Polymers 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000017 hydrogel Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
Abstract
The invention discloses a kind of encapsulating structure of power semiconductor part and packaging methods, the encapsulating structure includes: at least one encapsulation submodule group, it include: the Upper gasket being cascading, power chip, chip positioning frame and lower gasket, wherein, the size of Upper gasket is not less than the size of lower gasket, and the difference of the size of the size and lower gasket of Upper gasket is less than preset difference value；Chip positioning frame has the contact portion contacted with chip terminal area, adhesive layer is provided between contact portion and chip terminal area, so that contact portion and chip terminal area bonding, by implementing the present invention, the bending of chip when efficiently reducing power semiconductor device package, it avoids due to even brittle failure occurs for chip because cracking and fails, improve the reliability of power semiconductor；On the other hand the gap between chip terminal and positioning framework has been reduced or even eliminated, the stress levels of chip has been significantly increased, meets requirement of the electric system to device voltage grade.
Description
Technical field
The present invention relates to semiconductor device packaging technique fields, and in particular to a kind of encapsulating structure of power semiconductor part with
Packaging method.
Background technique
Currently, with the demand of electric system higher voltage grade and larger capacity, for the resistance to of power semiconductor
Pressure property is required in 3300V to 4500V, and future may can also be higher.Under so high voltage class, existing encapsulating structure and
Technique receives serious challenge.It, can be by the way of Silica hydrogel to chip for welded type power semiconductor
Pressure-resistant terminal is protected, and the stress levels of encapsulated device are then promoted.
For rigidly crimping power semiconductor, chip is the same as being depended on pressure between other components in crimping structure
It is contacted, the back side of chip is completely attached to molybdenum sheet, and due to the presence of active area and terminal, chip front side has for the front of chip
Source region is contacted with pressure with positive small molybdenum sheet, and the terminal area of chip surrounding is often not subject to pressure.Core is resulted in this way
Piece terminal is the same as there are gaps between the frame of surrounding.With the promotion of chip voltage grade, this gap between chip and frame
It will lead to the generation of electric discharge, and then chip terminal made to be damaged, device pressure resistance is caused to fail.
On the other hand, when under pressure using the device of rigidity crimping encapsulating structure, since upper and lower contact surface is unequal,
It will lead to chip bending.In the power semiconductor device package of traditional mesolow low capacity, due to the ruler of its terminal that insulate
Very little accounting is smaller, and it is not also very that this chip is anisopleual, which to apply stressed encapsulating structure to the influence of power chip bring,
Obviously；However, with the promotion of voltage class, the area accounting of chip surface insulation terminal be will increase, this result in chip by
Curved phenomenon is more serious, generates biggish tensile stress in chip back side.Since chip itself is fragile material, fragile material
Tensile capacity it is again relatively weak, chip interior is easy to produce crackle, causes chip to occur brittle failure, preparation to device and can
It is posed a serious threat by property.
Summary of the invention
In view of this, the present invention provides a kind of encapsulating structure of power semiconductor part and packaging method, to improve power half
The reliability of conductor device.
Technical solution proposed by the present invention is as follows:
First aspect present invention provides a kind of encapsulating structure of power semiconductor part, comprising: at least one encapsulation submodule group,
The submodule group includes: the Upper gasket being cascading, power chip, chip positioning frame and lower gasket, wherein on described
The size of gasket is not less than the size of the lower gasket, and the size of the Upper gasket and the difference of the size of the lower gasket are small
In preset difference value；The chip positioning frame has the contact portion contacted with chip terminal area, the contact portion and the chip
Adhesive layer is provided between termination environment, so that the contact portion and chip terminal area bonding.
Preferably, the contact portion is the groove being adapted on the inside of the chip positioning frame with the termination environment shape.
Preferably, the Upper gasket is connected with the mode that the power chip is sintered.
Preferably, the adhesive layer includes any one in organic layer of silica gel, epoxy adhesive layer or polyimides glue-line.
Preferably, the submodule group further include: pedestal；The chip positioning frame has buckle structure, passes through the card
Buckle structure and the base engagement.
Preferably, the submodule group further include: support chip, the support chip are set to the lower section of the lower gasket, with institute
Upper gasket, power chip, chip positioning frame and lower gasket is stated to be set to jointly on the pedestal.
Preferably, the Upper gasket and the lower gasket include: molybdenum sheet or metal-base composites kovar alloy piece.
Preferably, the support chip includes: any one in aluminium flake, silver strip or alloy sheet comprising aluminium or silver metal
Kind.
Second aspect of the present invention provides a kind of power semiconductor device package method, comprising: encapsulation submodule group is obtained, it is described
The step of obtaining encapsulation submodule group includes: to connect at the back side of power chip and Upper gasket in a manner of being sintered；In chip positioning
Adhesive layer is arranged in the contact portion of frame, Nian Jie with the termination environment of the power chip；Lower gasket is set to power chip and core
The lower section of piece positioning framework, the size of the Upper gasket are not less than the size of the lower gasket, and the size of the Upper gasket with
The difference of the size of the lower gasket is less than preset difference value.
Preferably, described the step of obtaining encapsulation submodule group further include: successively by support chip, the lower gasket, the core
Piece positioning framework, the power chip and Upper gasket are set on pedestal.
Technical solution of the present invention has the advantages that
1. encapsulating structure of power semiconductor part provided by the invention and packaging method, by keeping the size of Upper gasket not small
In the size of lower gasket, and the difference of the size of the size and lower gasket of Upper gasket is less than preset difference value, so that Upper gasket can
Suitable with lower gasket area, the bending of chip when efficiently reducing power semiconductor device package avoids chip because generating
Crackle even occurs brittle failure and fails, and improves the reliability of power semiconductor, high for voltage class (3300V with
On), the chip of capacity big (50A or more), especially chip front side insulate the biggish chip of terminal accounting, device can be significantly improved
The stress reliability of part chip in a package；On the other hand chip terminal area and positioning framework are bonded, are reduced or even eliminated
Gap between chip terminal and perimeter frame, protects chip terminal, significantly increases the stress levels of chip, makes
The device obtained finally has higher voltage class, meets requirement of the electric system to device voltage grade, furthermore passes through chip
It is sintered with Upper gasket, the packaging method of chip and positioning framework bonding reduces production process, while simplifying assembling process
It also avoids and chip terminal is caused to damage in assembly.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structural schematic diagram of a specific example of encapsulating structure of power semiconductor part in the embodiment of the present invention；
Fig. 2 is the structural representation of another specific example of encapsulating structure of power semiconductor part in the embodiment of the present invention
Figure；
Fig. 3 is the flow chart of a specific example of power semiconductor device package method in the embodiment of the present invention；
Fig. 4 is the flow chart of another specific example of power semiconductor device package method in the embodiment of the present invention.
Description of symbols:
1- Upper gasket；2- power chip；3- chip positioning frame；The groove of 31- chip positioning frame；4- underlay
Piece；5- support chip；6- pedestal.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the orientation of the instructions such as term " on ", "lower", "inner" or position are closed
System is merely for convenience of description of the present invention and simplification of the description to be based on the orientation or positional relationship shown in the drawings, rather than indicates
Or imply that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore cannot understand
For limitation of the present invention.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also can be indirectly connected through an intermediary
Connection inside two elements.For the ordinary skill in the art, above-mentioned term can be understood at this with concrete condition
Concrete meaning in invention.
As long as in addition, the non-structure each other of technical characteristic involved in invention described below different embodiments
It can be combined with each other at conflict.
Embodiment 1
The embodiment of the present invention provides a kind of encapsulating structure of power semiconductor part, as shown in Figure 1, the power semiconductor
Encapsulating structure include: at least one encapsulation submodule group, the submodule group include: the Upper gasket 1 being cascading, power chip 2,
Chip positioning frame 3 and lower gasket 4, wherein the size of Upper gasket 1 is not less than the size of lower gasket 4, and the size of Upper gasket 1
It is less than preset difference value with the difference of the size of lower gasket 4；Chip positioning frame 3 has the contact portion contacted with 2 termination environment of chip
31, it is provided with adhesive layer between contact portion 31 and chip terminal area, so that contact portion 31 and chip terminal area bonding.
The embodiment of the present invention by make Upper gasket 1 size be not less than lower gasket 4 size, and the size of Upper gasket 1 with
The difference of the size of lower gasket 4 is less than preset difference value and efficiently reduces so that Upper gasket 1 can be suitable with 4 area of lower gasket
The bending of chip 2 when power semiconductor device package is avoided due to even brittle failure occurs for chip 2 because cracking and is failed, improves
The reliability of power semiconductor, for the chip of voltage class high (3300V or more), capacity big (50A or more), especially
It is the chip front side insulation biggish chip of terminal accounting, the stress reliability of device chip in a package can be significantly improved；Separately
On the one hand 2 termination environment of chip and positioning framework 3 are bonded, between having reduced or even eliminated between chip terminal and perimeter frame
Gap solves the technical issues of gap guiding discharge, is protected to chip terminal, significantly increases the pressure resistance etc. of chip
Grade, so that final device has higher voltage class, meets requirement of the electric system to device voltage grade, optionally,
Power semiconductor may include power diode, thyristor, power bipolar transistor, vertical pair in the embodiment of the present invention
It spreads in Metal-Oxide Semiconductor field effect transistor, horizontal proliferation metal-oxide field effect transistor and IGBT
Any one, but the present invention is not limited thereto.
In the embodiment of the present invention, to avoid power chip 2 when being subjected to temperature cycles operating condition, due between different materials
Thermal expansion coefficient difference, the thermal stress for causing thermal mismatching to generate cause to damage to power chip, above-mentioned Upper gasket 1 and lower gasket 4
Using same material, which can be metal molybdenum or metal-base composites kovar alloy, and metal-base composites can cut down conjunction
Gold can be the alloy of metal molybdenum and silicon or the alloy of metal molybdenum and aluminium, also, the thermal expansion coefficient of Upper gasket 1 and lower gasket 4
With the similar thermal expansion coefficient of power chip 2, which can be 6 ± 2ppm/ DEG C, to improve 2 temperature resistance of power chip
Degree circulation, the reliability of power cycle.Optionally, in some embodiments of the invention, the shape of Upper gasket 1 and lower gasket 4
It is identical, it can be rectangular.
In a preferred embodiment, as shown in Figure 1, contact portion 31 is 3 inside of chip positioning frame and termination environment shape phase
The groove 31 of adaptation in the embodiment of the present invention, sets the contact portion 31 of 3 inside of chip positioning frame to the form of groove, can
To use the equipment such as automatic dispensing machine, vacuum drying oven, it is coated with one layer of bonding agent in a groove, keeps contact portion and chip terminal area viscous
It connects, adhesive layer can be any one in organosilicon glue-line resistant to high temperature, epoxy adhesive layer or polyimides glue-line, in posting
Groove is set on the inside of frame 3, can preferably realize the protection to chip terminal area, eliminates 2 termination environment of chip and positioning framework 3
Gap.
In a preferred embodiment, Upper gasket 1 is connected with the mode that power chip 2 is sintered.
In the embodiment of the present invention, the back side of power chip 2 and Upper gasket 1 are linked together using the technique of sintering, it can
So that chip 2 is fixed together with Upper gasket 1, then is bonded with lower gasket 4, combination is formed, can use and receive in sintering
Rice silver or materials, the state of agglomerated material such as silver-tin alloy can be soldering paste shape or film-form, be also possible to other materials or
Other states of person, the present invention is not limited thereto.
In a preferred embodiment, as shown in Fig. 2, the submodule group further include: pedestal 6；Chip positioning frame 3 has buckle
Structure is cooperated by buckle structure and pedestal 6, and in the embodiment of the present invention, the top of positioning framework 3 is buckle shape, ensure that
Positioning framework 3 is not easy loose or dislocation after installing on pedestal 6, improves the stability and reliability of structure.
In a preferred embodiment, as shown in Fig. 2, the submodule group further include: support chip 5, support chip 5 are set to lower gasket
4 lower section is set on pedestal 6 jointly with Upper gasket 1, power chip 2, chip positioning frame 3 and lower gasket 4, the present invention
In embodiment, the material of support chip 5 should have good thermal conductivity and lower hardness, this is because high pressure is big
Power chip generates heat seriously at work, and selecting thermal conductivity, good material can reduce thermal resistance, reduces the junction temperature of power chip,
And the mismachining tolerance of different components will affect the height of different encapsulation submodule groups, cause answering between submodule group during crimping
Power is uneven, and the lower support chip of hardness can absorb stress by deformation, so as to improve answering between different encapsulation submodule groups
Power distribution so that respectively encapsulation submodule group between stress it is uniform, optionally, the material of support chip 5 can be aluminium flake, silver strip or
Any one in alloy sheet comprising aluminium or silver metal.
Encapsulating structure of power semiconductor part provided in an embodiment of the present invention includes multiple encapsulation submodule groups, concrete application
In, the encapsulation of the power semiconductor of different current classes can be realized by the quantity of change encapsulation submodule group, when to function
When the current class of rate semiconductor devices is more demanding, power can partly be led by increasing the quantity in parallel realization of encapsulation submodule group
The dilatation of body device.
Embodiment 2
The embodiment of the present invention provides a kind of power semiconductor device package method, as shown in figure 3, power semiconductor
Packaging method includes: to obtain encapsulation submodule group, specifically, obtains encapsulation submodule group and includes the following steps:
Step 1: the back side of power chip and Upper gasket are connected in a manner of being sintered.Sintering process can make chip with
Upper gasket is fixed together, and can be can be using materials, the states of agglomerated material such as nano silver or silver-tin alloys in sintering
Soldering paste shape or film-form can be by the way of silk-screen printings, by agglomerated material when the state of agglomerated material is soldering paste shape
Then Upper gasket is sintered by the prefabricated surface in Upper gasket with the back side of power chip.
Step 2: in the contact portion of chip positioning frame, adhesive layer is set, it is Nian Jie with the termination environment of power chip.It is being arranged
When adhesive layer, automatic dispensing machine can be used, one layer is coated in contact portion, that is, positioning framework surrounding groove of positioning framework and glues
Agent is connect, bonding agent can be organic silica gel resistant to high temperature, epoxy glue or polyimides glue, and gluing process will guarantee to have filled
At, phenomena such as being not allow for disconnected glue, gap, then power chip terminal area is carried out with positioning framework it is be bonded, after bonding
Sample be put into vacuum drying oven and solidified, by evacuation process, deaeration is carried out to the bubble in bonded adhesives, prevents from being bonded
Partial discharge phenomenon occurs for the defects of bubble in glue, after the completion of technique for sticking, finally by Upper gasket, power chip and posting
Frame is combined into one.
Step 3: lower gasket is set to the lower section of power chip and chip positioning frame.Under the size of Upper gasket is not less than
The size of gasket, and the difference of the size of the size and lower gasket of Upper gasket is less than preset difference value.
The embodiment of the present invention is by making the size of Upper gasket be not less than the size of lower gasket, and the size and underlay of Upper gasket
The difference of the size of piece is less than preset difference value, so that Upper gasket can be suitable with lower gasket area, efficiently reduces power half
The bending of chip when conductor device encapsulates avoids due to even brittle failure occurs for chip because cracking and fails, improves power half
The reliability of conductor device, for the chip of voltage class high (3300V or more), capacity big (50A or more), especially chip is exhausted
The biggish chip of edge terminal accounting can significantly improve the stress reliability of device chip in a package；On the other hand by chip
Termination environment and positioning framework bonding, have reduced or even eliminated the gap between chip terminal and perimeter frame, to chip terminal area
It is protected, significantly increases the stress levels of chip, so that final device has higher voltage class, meet electric power
Requirement of the system to device voltage grade is sintered by chip and Upper gasket, and the packaging method of chip and positioning framework bonding subtracts
Production process is lacked, has been also avoided while simplifying assembling process and chip terminal is caused to damage in assembly, improve device
The reliability of part.
In the embodiment of the present invention, to avoid power chip when being subjected to temperature cycles operating condition, due between different materials
Thermal expansion coefficient difference, the thermal stress for causing thermal mismatching to generate cause to damage to power chip, and Upper gasket uses phase with lower gasket
Same material, the material can be metal molybdenum or metal-base composites kovar alloy, and metal-base composites kovar alloy can be with
It is the alloy of metal molybdenum and silicon or the alloy of metal molybdenum and aluminium, also, the thermal expansion coefficient of Upper gasket and lower gasket and power core
The similar thermal expansion coefficient of piece, the thermal expansion coefficient can be 6 ± 2ppm/ DEG C, to improve power chip resisting temperature circulation, power
The reliability of circulation.Optionally, in some embodiments of the invention, Upper gasket is identical as the shape of lower gasket, the side of can be
Shape.
In a preferred embodiment, as shown in figure 4, the step of obtaining encapsulation submodule group further include:
Step 4: support chip, lower gasket, chip positioning frame, power chip and Upper gasket being successively set to pedestal
On.
In the embodiment of the present invention, the top of positioning framework is buckle shape, ensure that positioning framework installs on pedestal
After be not easy loose or dislocation, improve the stability and reliability of structure, optionally, the material of support chip should have good thermally conductive
Electric conductivity and lower hardness select thermal conductivity this is because high-power chip generates heat seriously at work
Good material can reduce thermal resistance, reduce the junction temperature of power chip, and the mismachining tolerance of different components will affect different encapsulation
The height of mould group, causes the Stress non-homogeneity during crimping between submodule group, and the lower support chip of hardness can pass through deformation
Stress is absorbed, so as to improve the stress distribution between different encapsulation submodule groups, so that the stress respectively between encapsulation submodule group is uniform,
Optionally, the material of support chip can be any one in aluminium flake, silver strip or alloy sheet comprising aluminium or silver metal.
Power semiconductor device package method provided in an embodiment of the present invention in the specific implementation, can be according to actual needs
The quantity that different encapsulation submodule groups is arranged can pass through increase when the current class to power semiconductor is more demanding
Encapsulate dilatation of the quantity in parallel realization of submodule group to power semiconductor.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or
It changes still within the protection scope of the invention.
Claims (10)
1. a kind of encapsulating structure of power semiconductor part characterized by comprising at least one encapsulation submodule group, the submodule
Group includes: the Upper gasket being cascading, power chip, chip positioning frame and lower gasket, wherein
The size of the Upper gasket is not less than the size of the lower gasket, and the ruler of the size of the Upper gasket and the lower gasket
Very little difference is less than preset difference value；
The chip positioning frame has the contact portion that contacts with chip terminal area, the contact portion and the chip terminal area it
Between be provided with adhesive layer so that the contact portion and the chip terminal area bonding.
2. encapsulating structure of power semiconductor part according to claim 1, which is characterized in that the contact portion is the core
The groove being adapted on the inside of piece positioning framework with the termination environment shape.
3. encapsulating structure of power semiconductor part according to claim 1, which is characterized in that the Upper gasket and the function
The mode of rate chip sintering connects.
4. encapsulating structure of power semiconductor part according to claim 1, which is characterized in that the adhesive layer includes organic
Any one in layer of silica gel, epoxy adhesive layer or polyimides glue-line.
5. encapsulating structure of power semiconductor part according to claim 1, which is characterized in that the submodule group further include:
Pedestal；
The chip positioning frame has buckle structure, passes through the buckle structure and the base engagement.
6. encapsulating structure of power semiconductor part according to any one of claims 1-5, which is characterized in that the son
Mould group further include: support chip, the support chip are set to the lower section of the lower gasket, with the Upper gasket, power chip, chip
Positioning framework and lower gasket are set to jointly on the pedestal.
7. encapsulating structure of power semiconductor part according to claim 1 to 6, which is characterized in that on described
Gasket and the lower gasket include: molybdenum sheet or metal-base composites kovar alloy piece.
8. encapsulating structure of power semiconductor part as claimed in claim 6, which is characterized in that the support chip include: aluminium flake,
Any one in silver strip or alloy sheet comprising aluminium or silver metal.
9. a kind of power semiconductor device package method characterized by comprising encapsulation submodule group is obtained, it is described to be encapsulated
The step of submodule group includes:
The back side of power chip and Upper gasket are connected in a manner of being sintered；
In the contact portion of chip positioning frame, adhesive layer is set, it is Nian Jie with the termination environment of the power chip；
Lower gasket is set to the lower section of power chip and chip positioning frame, the size of the Upper gasket is not less than the underlay
The size of piece, and the difference of the size of the Upper gasket and the size of the lower gasket is less than preset difference value.
10. power semiconductor device package method according to claim 9, which is characterized in that described to obtain encapsulation submodule
The step of group further include: successively by support chip, the lower gasket, the chip positioning frame, the power chip and upper pad
Piece is set on pedestal.
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