CN111508902B - Insulation structure, insulation piece wrapping chip periphery and preparation method thereof - Google Patents
Insulation structure, insulation piece wrapping chip periphery and preparation method thereof Download PDFInfo
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- CN111508902B CN111508902B CN202010340570.0A CN202010340570A CN111508902B CN 111508902 B CN111508902 B CN 111508902B CN 202010340570 A CN202010340570 A CN 202010340570A CN 111508902 B CN111508902 B CN 111508902B
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- 238000000576 coating method Methods 0.000 claims abstract description 21
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 31
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 12
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- 238000004806 packaging method and process Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
Abstract
The invention provides an insulating structure, an insulating piece for coating the periphery of a chip and a preparation method thereof. The insulating structure comprises a first insulating layer, a second insulating layer and a third insulating layer which are arranged in a stacked mode, wherein the thermal expansion coefficients of the first insulating layer and the third insulating layer are smaller than that of the second insulating layer. According to the insulation structure provided by the invention, the thermal expansion coefficients of the first insulation layer and the third insulation layer are smaller than that of the second insulation layer, so that the second insulation layer positioned in the middle of the insulation structure expands and deforms more than the first insulation layer and the third insulation layer positioned on two sides of the insulation structure when the insulation structure is heated, the insulation structure forms a closed insulation part, the third insulation layer positioned on the outer side inhibits outward expansion of the second insulation layer when the insulation structure is heated, the deformation stress of the third insulation layer is inwards compressed, the first insulation layer positioned on the inner side can be tightly combined with a chip coated by the first insulation layer, and the insulation part and the chip are prevented from falling off in a high-temperature state.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to an insulating structure, an insulating piece for coating the periphery of a chip and a preparation method thereof.
Background
The chip package plays a role in placing, fixing, sealing, protecting the chip and enhancing the electric heating performance, and some kinds of chips, such as Insulated Gate Bipolar Transistor (IGBT) chips, have an exceptionally bad working electric field environment, so in the chip structure and package design links, except considering the electric field distribution and insulation problems inside the chip, the electric field effect on the chip surface is also not neglected, in which the creeping discharge is a harmful discharge phenomenon, and the existence of the creeping discharge phenomenon can cause the insulation performance of the chip to be significantly reduced because the high voltage is gas discharge occurring along the interface of the solid and the air.
In order to solve the influence of the creeping discharge on the chip, the chip is usually shielded and protected by using a reliable insulating material. The currently used insulating material is alumina ceramic or a polymer material with high insulating property, and the periphery of the chip is protected by arranging an insulating member formed by the insulating material around the periphery of the chip. Although the polymer material has the advantages of easy molding processing, high breakdown electric field and the like, the polymer material has relatively poor heat dissipation performance and a larger difference between the thermal expansion coefficient and the silicon-based material, the heat dissipation of a chip can be influenced in practical application, and in addition, the insulation protection layer is caused to fall off and fail due to the difference between the thermal expansion Coefficients (CTE) in the temperature cycle process and the power cycle process. The alumina ceramic has relatively good heat dissipation performance, but a certain difference still exists between the CTE of the alumina ceramic and a silicon-based material, an alumina ceramic insulating layer is easy to fall off in practical application, and in addition, the hard ceramic can damage the terminal structure of the chip, so that the electrical reliability of the chip is influenced.
Disclosure of Invention
Therefore, the present invention is directed to overcome the defect that the insulating member around the chip is easy to fall off, and to provide an insulating structure, an insulating member covering the periphery of the chip, and a method for manufacturing the same.
In a first aspect, the present invention provides an insulating structure, including a first insulating layer, a second insulating layer, and a third insulating layer, which are stacked, wherein thermal expansion coefficients of the first insulating layer and the third insulating layer are smaller than a thermal expansion coefficient of the second insulating layer.
Further, the first insulating layer, the second insulating layer and the third insulating layer are all made of insulating materials formed by polyether-ether-ketone and fillers, and the fillers comprise aluminum nitride nanofibers and/or aluminum oxide nanofibers;
the mass percentage of the filler in the insulating materials forming the first insulating layer and the third insulating layer is higher than that of the filler in the insulating material forming the second insulating layer respectively based on the mass of each layer of insulating material.
Further, the mass percentage of the filler in the insulating material forming the first insulating layer and the third insulating layer is 26% -48% higher than that of the filler in the insulating material forming the second insulating layer.
Further, the mass percentage of the filler in the insulating material forming the first insulating layer is 30-50%, the mass percentage of the filler in the insulating material forming the second insulating layer is 2-4%, and the mass percentage of the filler in the insulating material forming the third insulating layer is 30-50%, respectively, based on the mass of each layer of insulating material.
Further, the mass percentage of the filler in the insulating material forming the first insulating layer is 40%, the mass percentage of the filler in the insulating material forming the second insulating layer is 3%, and the mass percentage of the filler in the insulating material forming the third insulating layer is 40%, respectively, based on the mass of each layer of insulating material.
Further, the thickness of the first insulating layer is 0.1-0.3mm, the thickness of the second insulating layer is 0.6-0.8mm, and the thickness of the third insulating layer is 1.0-1.2 mm.
Further, the thickness of the first insulating layer is 0.2mm, the thickness of the second insulating layer is 0.7mm, and the thickness of the third insulating layer is 1.1 mm.
In a second aspect, the present invention provides an insulating member covering a periphery of a chip, the insulating member having the insulating structure, wherein the first insulating layer is attached to the periphery of the chip.
In a third aspect, the present invention provides a method for preparing the insulating member covering the periphery of the chip, including:
preparing insulating materials for forming the first insulating layer, the second insulating layer and the third insulating layer respectively;
and forming a first insulating layer, a second insulating layer and a third insulating layer on the insulating material by adopting an injection molding process to obtain the insulating part for coating the periphery of the chip.
Further, the preparation method of the insulating material comprises the following steps: mixing polyether-ether-ketone and filler at the temperature of 360-400 ℃ to obtain the insulating material.
In a fourth aspect, the present invention provides an application of the insulating structure, or the insulating member covering the periphery of the chip obtained by the preparation method in chip insulation protection.
Further, the chip is an insulated gate bipolar transistor chip.
In a fifth aspect, the present invention provides a chip package structure, including a chip and an insulating member covering a periphery of the chip, where the insulating member is the insulating member covering the periphery of the chip, or the insulating member covering the periphery of the chip obtained by the preparation method.
The technical scheme of the invention has the following advantages:
1. according to the insulation structure provided by the invention, the first insulation layer, the second insulation layer and the third insulation layer are arranged, and the thermal expansion coefficients of the first insulation layer and the third insulation layer are smaller than that of the second insulation layer, so that the second insulation layer located in the middle of the insulation structure expands and deforms more than the first insulation layer and the third insulation layer located on two sides of the insulation structure when the insulation structure is heated, the insulation structure forms a closed insulation piece, the third insulation layer located on the outer side inhibits outward expansion of the second insulation layer when the insulation structure is heated, and the deformation stress of the third insulation layer is inwards compressed, so that the first insulation layer located on the inner side can be tightly combined with a chip coated by the first insulation layer, and further, the phenomenon that the insulation piece and the chip fall off under a high-temperature state is avoided.
2. According to the insulation structure provided by the invention, the insulation material takes polyether-ether-ketone as a matrix and takes aluminum nitride nano-fiber and/or aluminum oxide nano-fiber as a filler, wherein the polyether-ether-ketone (PEEK) belongs to a special high polymer material, has easy processability and high temperature resistance, and can be used as a high temperature resistant structure material and an electrical insulation material; the aluminum nitride nanofiber and the aluminum oxide nanofiber have excellent heat conductivity and thermal expansion coefficients close to those of silicon-based materials, and the composite material formed by the aluminum nitride nanofiber and the aluminum oxide nanofiber can keep the advantages of the material performance of each component, and can obtain comprehensive performance which cannot be achieved by a single component material through complementation and correlation of the material performance of each component: the polyether-ether-ketone is used as a matrix, so that the insulating material has certain flexibility, and the damage to the chip is avoided; the aluminum nitride nano-fiber and/or the aluminum oxide nano-fiber are/is used as the filler, so that the heat conductivity of the matrix material is effectively improved, and the excessive deformation of the matrix polymer caused by heating can be limited; the composite material formed by the two layers of insulating materials has high insulating property, can effectively inhibit the creeping discharge phenomenon of the chip when used for protecting the chip, improves the reliability of the chip in a high-temperature and high-heat environment, and can effectively prevent the chip from falling off due to an insulating structure formed by the three layers of insulating materials.
3. According to the insulating structure provided by the invention, the mass percentages of the fillers in the first insulating layer, the second insulating layer and the third insulating layer and the thicknesses of all layers are optimized, so that the insulating structure has excellent insulating property, heat-conducting property and anti-falling property.
4. The insulating piece for coating the periphery of the chip, provided by the invention, has the insulating structure, wherein the first insulating layer is attached to the periphery of the chip, so that the force for inwards extruding the chip can be generated when the insulating piece is heated, and the chip is effectively prevented from falling off.
5. The preparation method of the insulating part for coating the periphery of the chip adopts an injection molding process, is simple, is easy to process and is suitable for large-scale popularization and application.
6. The insulating structure or the insulating part coating the periphery of the chip provided by the invention is applied to chip insulation protection, and is particularly suitable for high-voltage chips, such as insulation protection of an Insulated Gate Bipolar Transistor (IGBT) chip.
7. The chip packaging structure provided by the invention can effectively improve the phenomenon of surface discharge of the chip, is stable and not easy to fall off, and can effectively prolong the service life of the chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic structural diagram of an insulation structure provided in the present invention;
fig. 2 is a top view of a chip package structure according to the present invention;
fig. 3 is a sectional view a-a of fig. 2.
Description of reference numerals:
1-a first insulating layer; 2-a second insulating layer; 3-a third insulating layer; 4-chip; 5-insulating part.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and operate, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1, the present invention provides an insulating structure, which includes a first insulating layer 1, a second insulating layer 2, and a third insulating layer 3 stacked together, wherein the thermal expansion coefficients of the first insulating layer 1 and the third insulating layer 3 are smaller than the thermal expansion coefficient of the second insulating layer 2.
According to the insulation structure provided by the invention, the first insulation layer 1, the second insulation layer 2 and the third insulation layer 3 are arranged, and the thermal expansion coefficients of the first insulation layer 1 and the third insulation layer 3 are smaller than that of the second insulation layer 2, so that the second insulation layer 2 positioned in the middle of the insulation structure expands and deforms more than the first insulation layer 1 and the third insulation layer 3 positioned on two sides of the insulation structure when being heated, the insulation structure forms a closed insulation part, the third insulation layer 3 positioned on the outer side inhibits outward expansion of the second insulation layer 2 when being heated, and deformation stress of the second insulation layer 2 is inwards compressed, so that the first insulation layer 1 positioned on the inner side can be tightly combined with a chip coated by the first insulation layer, and further, the insulation part and the chip are prevented from falling off in a high-temperature state.
The present invention does not limit the materials of the first insulating layer 1, the second insulating layer 2 and the third insulating layer 3, and any insulating structure formed by materials meeting the above requirements is within the protection scope of the present invention.
As an alternative embodiment of the present invention, the first insulating layer 1, the second insulating layer 2, and the third insulating layer 3 are each made of an insulating material formed of polyetheretherketone and a filler including aluminum nitride nanofibers and/or aluminum oxide nanofibers;
wherein, the mass percentage of the filler in the insulating material forming the first insulating layer 1 and the third insulating layer 3 is higher than that of the filler in the insulating material forming the second insulating layer 2, respectively based on the mass of each layer of insulating material.
The performance parameters relating to the materials are shown in table 1.
Table 1 properties of materials to which the invention relates
According to the insulation structure provided by the invention, the insulation material takes polyether-ether-ketone as a matrix and takes aluminum nitride nano-fiber and/or aluminum oxide nano-fiber as a filler, wherein the polyether-ether-ketone (PEEK) belongs to a special high polymer material, has easy processability and high temperature resistance, and can be used as a high temperature resistant structure material and an electrical insulation material; the aluminum nitride nanofiber and the aluminum oxide nanofiber have excellent heat conductivity and thermal expansion coefficients close to those of silicon-based materials (as shown in table 1), and the composite material formed by the aluminum nitride nanofiber and the aluminum oxide nanofiber not only can keep the advantages of the material properties of each component, but also can obtain comprehensive properties which cannot be achieved by a single component material through the complementation and the correlation of the properties of each component: the polyether-ether-ketone is used as a matrix, so that the insulating material has certain flexibility, and the damage to the chip is avoided; the aluminum nitride nano-fiber and/or the aluminum oxide nano-fiber are/is used as the filler, so that the heat conductivity of the matrix material is effectively improved, and the excessive deformation of the matrix polymer caused by heating can be limited; the composite material formed by the two layers of insulating materials has high insulating property, can effectively inhibit the creeping discharge phenomenon of the chip when used for protecting the chip, improves the reliability of the chip in a high-temperature and high-heat environment, and can effectively prevent the chip from falling off due to an insulating structure formed by the three layers of insulating materials.
Polyether ether ketone (PEEK) is a wholly aromatic semi-crystalline thermoplastic engineering plastic, contains a rigid benzene ring, flexible ether bonds and carbonyl groups in a macromolecular chain, and has excellent mechanical property, chemical corrosion resistance, creep resistance, radiation resistance and remarkable thermal stability.
Both aluminum nitride nanofibers and aluminum oxide nanofibers are known in the art and methods for their preparation are well known to those skilled in the art. For example, the alumina nanofibers and the aluminum nitride nanofibers are prepared by an electrostatic spinning process: over MgSO4Adding Al (C) into the aqueous solution in sequence3H7OH)3、Al(NO3)3·9H2O and C2H5And OH, adding polyvinylpyrrolidone (PVP) to prepare a precursor solution, putting the precursor solution into an injector for spinning, then calcining to form the alumina nano-fiber, and carrying out a high-temperature nitridation process on the alumina nano-fiber to obtain the aluminum nitride nano-fiber.
As a preferred embodiment of the present invention, the mass percentage of the filler in the insulating material forming the first insulating layer 1 and the third insulating layer 3 is higher by 26% to 48% than the mass percentage of the filler in the insulating material forming the second insulating layer 2.
Further preferably, the mass percentage of the filler in the insulating material forming the first insulating layer 1 is 30 to 50%, the mass percentage of the filler in the insulating material forming the second insulating layer 2 is 2 to 4%, and the mass percentage of the filler in the insulating material forming the third insulating layer 3 is 30 to 50%, respectively, based on the mass of each layer of insulating material.
Further preferably, the mass percentage of the filler in the insulating material forming the first insulating layer 1, the mass percentage of the filler in the insulating material forming the second insulating layer 2, and the mass percentage of the filler in the insulating material forming the third insulating layer 3 are 40%, respectively, based on the mass of each layer of the insulating material.
In a preferred embodiment of the present invention, the first insulating layer 1 has a thickness of 0.1 to 0.3mm, the second insulating layer 2 has a thickness of 0.6 to 0.8mm, and the third insulating layer 3 has a thickness of 1.0 to 1.2 mm.
Further preferably, the thickness of the first insulating layer 1 is 0.2mm, the thickness of the second insulating layer 2 is 0.7mm, and the thickness of the third insulating layer 3 is 1.1 mm.
According to the insulating structure provided by the invention, the mass percentages of the fillers in the first insulating layer, the second insulating layer and the third insulating layer and the thicknesses of all layers are optimized, so that the insulating structure has excellent insulating property, heat-conducting property and anti-falling property.
The invention provides an insulating part for coating the periphery of a chip, which is provided with the insulating structure, wherein a first insulating layer is attached to the periphery of the chip. The insulating part can generate force for inwards extruding the chip when being heated, and the chip is effectively prevented from falling off.
The invention provides a preparation method of the insulating part for coating the periphery of the chip, which comprises the following steps:
preparing insulating materials for forming a first insulating layer, a second insulating layer and a third insulating layer respectively;
and forming a first insulating layer, a second insulating layer and a third insulating layer on the insulating material by adopting an injection molding process to obtain the insulating part for coating the periphery of the chip.
The preparation method of the insulating material provided by the invention adopts an injection molding process, is simple, is easy to process and is suitable for large-scale popularization and application.
The invention does not limit the shape of the insulating piece covering the periphery of the chip, and the shape of the insulating piece can be adjusted along with the shape of the periphery of the chip.
As an alternative embodiment of the present invention, a method of preparing an insulating material includes: mixing polyether-ether-ketone and filler at the temperature of 360-400 ℃ to obtain the insulating material.
During the injection molding process, the mold temperature is maintained at 150 ℃ and 250 ℃, preferably 200 ℃.
According to a specific embodiment of the insulation structure provided by the invention, a closed insulation part is prepared according to the edge shape and size of a chip and is used for chip insulation protection, particularly suitable for insulation protection of a high-voltage chip such as an Insulated Gate Bipolar Transistor (IGBT) chip.
The IGBT power module is an important high-power device in the field of power electronics, and is increasingly emphasized in high-capacity occasions, for example, three fields such as high-speed rails, power grids, and frequency converters show its specific advantages. In recent years, with the development of a new infrastructure flexible direct-current high-voltage power transmission project such as a power grid, the demand of an IGBT power module as a core part of the flexible direct-current high-voltage power transmission project is increasing, and meanwhile, the performance requirements on the module are stricter. The insulating material provided by the invention can better meet the requirement on high performance of the IGBT power module, and is beneficial to promoting the IGBT power module to play more important role.
As shown in fig. 2 and fig. 3, the present invention provides a chip package structure, which is composed of a chip 4 and an insulating member 5 covering the periphery of the chip, where the insulating member 5 is the insulating member covering the periphery of the chip, or the insulating member covering the periphery of the chip obtained by the above preparation method. The chip packaging structure provided by the invention can effectively improve the phenomenon of surface discharge of the chip, is stable and not easy to fall off, and can effectively prolong the service life of the chip.
As an alternative embodiment of the present invention, the chip 4 and the insulating member 5 are connected to each other by means of adhesion, that is, the first insulating layer 1 in the insulating structure of the insulating member is adhered to the periphery of the chip 4.
The technical scheme provided by the invention is further illustrated by the specific examples below.
Example 1
An insulating part for coating the periphery of a chip is prepared by the following steps:
respectively taking polyether-ether-ketone and aluminum nitride nanofibers according to the mass ratio of 60:40, and blending the polyether-ether-ketone and the aluminum nitride nanofibers at 360 ℃ by using a mixing extruder to obtain an insulating material for forming a first insulating layer and a third insulating layer;
respectively taking polyether-ether-ketone and aluminum nitride nanofibers according to the mass ratio of 97:3, and blending the polyether-ether-ketone and the aluminum nitride nanofibers at 360 ℃ by using a mixing extruder to obtain an insulating material for forming a second insulating layer;
and keeping the temperature of the die at 200 ℃, and sequentially extruding a first insulating layer, a second insulating layer and a third insulating layer by adopting an injection molding process, wherein the thickness of the first insulating layer is 0.2mm, the thickness of the second insulating layer is 0.7mm, and the thickness of the third insulating layer is 1.1mm to obtain the insulating part for coating the periphery of the chip.
Example 2
An insulating part for coating the periphery of a chip is prepared by the following steps:
respectively taking polyether-ether-ketone and alumina nano-fiber according to a mass ratio of 70:30, and blending the polyether-ether-ketone and the alumina nano-fiber at 360 ℃ by using a mixing extruder to obtain an insulating material for forming a first insulating layer and a third insulating layer;
respectively taking polyether-ether-ketone and alumina nano-fiber according to the mass ratio of 97:2, and blending the polyether-ether-ketone and the alumina nano-fiber at 380 ℃ by using a mixing extruder to obtain an insulating material for forming a second insulating layer;
and keeping the temperature of the die at 150 ℃, and sequentially extruding a first insulating layer, a second insulating layer and a third insulating layer by adopting an injection molding process, wherein the thickness of the first insulating layer is 0.1mm, the thickness of the second insulating layer is 0.6mm, and the thickness of the third insulating layer is 1.2mm to obtain the insulating part for coating the periphery of the chip.
Example 3
An insulating part for coating the periphery of a chip is prepared by the following steps:
respectively taking polyether-ether-ketone and aluminum nitride nanofibers according to the mass ratio of 50:50, and blending the polyether-ether-ketone and the aluminum nitride nanofibers at 400 ℃ by using a mixing extruder to obtain an insulating material for forming a first insulating layer and a third insulating layer;
respectively taking polyether-ether-ketone and aluminum nitride nanofibers according to the mass ratio of 97:4, and blending the polyether-ether-ketone and the aluminum nitride nanofibers at 380 ℃ by using a mixing extruder to obtain an insulating material for forming a second insulating layer;
and keeping the temperature of the die at 250 ℃, and sequentially extruding a first insulating layer, a second insulating layer and a third insulating layer by adopting an injection molding process, wherein the thickness of the first insulating layer is 0.3mm, the thickness of the second insulating layer is 0.8mm, and the thickness of the third insulating layer is 1.0mm to obtain the insulating piece for coating the periphery of the chip.
Example 4
An insulating part for coating the periphery of a chip is prepared by the following steps:
respectively taking polyether-ether-ketone and aluminum nitride nanofibers according to the mass ratio of 50:50, and blending the polyether-ether-ketone and the aluminum nitride nanofibers at 370 ℃ by using a mixing extruder to obtain an insulating material for forming a first insulating layer;
respectively taking polyether-ether-ketone and alumina nano-fiber according to the mass ratio of 98:2, and blending the polyether-ether-ketone and the alumina nano-fiber at 370 ℃ by using a mixing extruder to obtain an insulating material for forming a second insulating layer;
respectively taking polyether-ether-ketone and aluminum nitride nanofibers according to the mass ratio of 60:40, and blending the polyether-ether-ketone and the aluminum nitride nanofibers at 370 ℃ by using a mixing extruder to obtain an insulating material for forming a first insulating layer;
and keeping the temperature of the die at 200 ℃, and sequentially extruding a first insulating layer, a second insulating layer and a third insulating layer by adopting an injection molding process, wherein the thickness of the first insulating layer is 0.1mm, the thickness of the second insulating layer is 0.8mm, and the thickness of the third insulating layer is 1.1mm to obtain the insulating part for coating the periphery of the chip.
Example 5
An insulating part for coating the periphery of a chip is prepared by the following steps:
respectively taking polyether-ether-ketone and aluminum nitride nanofibers according to the mass ratio of 60:40, and blending the polyether-ether-ketone and the aluminum nitride nanofibers at 400 ℃ by using a mixing extruder to obtain an insulating material for forming a first insulating layer;
respectively taking polyether-ether-ketone and aluminum nitride nanofibers according to the mass ratio of 97:3, and blending the polyether-ether-ketone and the aluminum nitride nanofibers at 360 ℃ by using a mixing extruder to obtain an insulating material for forming a second insulating layer;
respectively taking polyether-ether-ketone and alumina nano-fiber according to the mass ratio of 50:50, and blending the polyether-ether-ketone and the alumina nano-fiber at 360 ℃ by using a mixing extruder to obtain an insulating material for forming a first insulating layer;
and keeping the temperature of the die at 180 ℃, and sequentially extruding a first insulating layer, a second insulating layer and a third insulating layer by adopting an injection molding process, wherein the thickness of the first insulating layer is 0.2mm, the thickness of the second insulating layer is 0.8mm, and the thickness of the third insulating layer is 1.0mm to obtain the insulating piece for coating the periphery of the chip.
Comparative example
An insulating part for coating the periphery of a chip is prepared by the following steps:
according to the mass ratio of 60:40, the polyether-ether-ketone nano fiber and the aluminum nitride nano fiber are mixed by a mixing extruder at 360 ℃ to form an insulating material;
and keeping the temperature of the die at 200 ℃, and extruding the insulating material by adopting an injection molding process to obtain an insulating piece with the thickness of 2mm and covering the periphery of the chip.
Test example
The anti-drop performance test of the insulating member covering the periphery of the chip provided in embodiment 1 of the present invention is specifically as follows:
1. experiment grouping
Taking 40 IGBT chips produced in the same batch, randomly dividing the IGBT chips into 4 groups of 10 chips, wherein the processing method of each group is as follows:
experimental groups: the insulating member covering the periphery of the chip provided by the embodiment 1 is used for bonding with the periphery of the IGBT chip;
control group 1: protective measures are not taken on the periphery of the IGBT chip;
control group 2: bonding an insulating part made of pure ceramic material with the periphery of the IGBT chip;
control group 3: the insulator provided by the comparative example and covering the periphery of the chip is used for bonding with the periphery of the IGBT chip.
2. Experimental methods
And testing the IGBT chips of the experimental group and the control group 1-3 by adopting a temperature cycle experiment, and controlling the same testing conditions.
Detecting parameters: testing temperature cycle;
and (3) testing conditions are as follows: -40 ℃ to 150 ℃;
the heating rate is 15 ℃/min;
the cooling rate is 10 ℃/min;
and circulating for 1000 periods.
The QT2 transistor characteristic graphic instrument is adopted to test the voltage resistance and the breakdown electric field of the chip CE.
3. Results of the experiment
The test results are shown in table 1.
TABLE 1 test results of temperature cycling experiments
4. Conclusion
As can be seen from table 1, the insulating member made of pure ceramic material has low voltage-resistant protection effect on the chip, and it is seen that the insulating member is easily peeled off due to CET mismatch under thermal cycle, and loses protection effect on the chip, and meanwhile, CET mismatch may also damage the chip. The chip is protected by the novel insulating piece with the three-layer insulating structure, the yield of the chip is effectively guaranteed, and the insulating piece can still be in close contact with the chip after thermal circulation, so that the creeping discharge is effectively slowed down. In addition, the composite material of the single-layer polyetheretherketone and the filler cannot effectively inhibit the creeping discharge of the chip after temperature cycle due to the difference of the thermal expansion coefficients.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (9)
1. An insulation structure is characterized by comprising a first insulation layer, a second insulation layer and a third insulation layer which are arranged in a stacked mode, wherein the thermal expansion coefficients of the first insulation layer and the third insulation layer are smaller than that of the second insulation layer;
the first insulating layer, the second insulating layer and the third insulating layer are all made of insulating materials formed by polyether-ether-ketone and fillers, and the fillers comprise aluminum nitride nanofibers and/or aluminum oxide nanofibers;
the mass percentage of the filler in the insulating materials forming the first insulating layer and the third insulating layer is higher than that of the filler in the insulating material forming the second insulating layer respectively based on the mass of each layer of insulating material.
2. The insulation structure of claim 1, wherein the mass percentage of the filler in the insulation material forming the first and third insulation layers is 26% -48% higher than the mass percentage of the filler in the insulation material forming the second insulation layer.
3. The insulation structure according to claim 1 or 2, wherein the mass percentage of the filler in the insulation material forming the first insulation layer is 30 to 50%, the mass percentage of the filler in the insulation material forming the second insulation layer is 2 to 4%, and the mass percentage of the filler in the insulation material forming the third insulation layer is 30 to 50%, respectively, based on the mass of each layer of insulation material.
4. An insulation structure according to claim 1 or 2, characterized in that the thickness of the first insulation layer is 0.1-0.3mm, the thickness of the second insulation layer is 0.6-0.8mm, and the thickness of the third insulation layer is 1.0-1.2 mm.
5. An insulating member covering a peripheral edge of a chip, wherein the insulating member has an insulating structure according to any one of claims 1 to 4, wherein the first insulating layer is attached to the peripheral edge of the chip.
6. The method of manufacturing the chip peripheral edge covering insulator of claim 5, comprising:
preparing insulating materials for forming the first insulating layer, the second insulating layer and the third insulating layer respectively;
and forming a first insulating layer, a second insulating layer and a third insulating layer on the insulating material by adopting an injection molding process to obtain the insulating part for coating the periphery of the chip.
7. Use of the insulating structure according to any one of claims 1 to 4 for chip insulation protection, or use of the insulating member covering the chip periphery according to claim 5 for chip insulation protection, or use of the insulating member covering the chip periphery obtained by the preparation method according to claim 6 for chip insulation protection.
8. Use according to claim 7, wherein the chip is an insulated gate bipolar transistor chip.
9. A chip packaging structure, comprising a chip and an insulating member covering the periphery of the chip, wherein the insulating member is the insulating member covering the periphery of the chip according to claim 5, or the insulating member covering the periphery of the chip obtained by the preparation method according to claim 6.
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| US8878350B1 (en) * | 2013-04-12 | 2014-11-04 | Maxim Integrated Products, Inc. | Semiconductor device having a buffer material and stiffener |
| KR102512228B1 (en) * | 2015-10-01 | 2023-03-21 | 삼성전기주식회사 | Insulating material and printed circuit board having the same |
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