CN108173549A - A kind of low-power consumption sigma delta modulators based on capacitance resistance double loop structure - Google Patents
A kind of low-power consumption sigma delta modulators based on capacitance resistance double loop structure Download PDFInfo
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- CN108173549A CN108173549A CN201711372817.1A CN201711372817A CN108173549A CN 108173549 A CN108173549 A CN 108173549A CN 201711372817 A CN201711372817 A CN 201711372817A CN 108173549 A CN108173549 A CN 108173549A
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- power consumption
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- modulator
- sigma delta
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
Abstract
The invention discloses a kind of low-power consumption sigma delta modulators based on capacitance resistance double loop structure, the result of quantization is fed back to input terminal at different levels by the modulator by SCR DAC1, SCR DAC2 and SCR DAC3, reduce the superlinearity adder in the structure of Feed forward, reduce the complexity and power consumption of design.Meanwhile the modulator can make up the shortcomings that traditional CT SD modulators power consumption is big and stability is poor, promote the stability of CTSD ADC in this way, identical precision is realized with relatively low power consumption, meet the demand of Internet of Things.
Description
Technical field
The present invention relates to IC design fields, are specifically a kind of low work(based on capacitance resistance double loop structure
Consume sigma delta modulators.
Background technology
With the development of the times, people propose the power consumption and area of circuit system more and more harsh requirement, and ADC makees
Tie between analog/digital, power consumption are concerned.Once industry thought that pineline ADC were high dynamic performances
The unique selection that 100MSPS is once applied, but the appearance of continuous time sigma delta (CTSD) ADC has been overturned people and has been consolidated
Some ideas.CTSD ADC are made of CTSD modulators and decimation filter of digital.CTSD ADC are compared to traditional Nai Kuisi
Special ADC does not need to preposition High Linear frequency overlapped-resistable filter and high speed gain grade required during sampling.Compared to discrete time
Sigma delta (DTSD) modulator, CTSD modulators do not have the limitation of system settling time.Mistake has been used in CTSD modulators
Sampling, multilevel quantization and noise shaping techniques, the over-sampling rate due to modulator are limited, in order to improve modulator signal-to-noise ratio
(SNR), it needs to improve the exponent number of modulator or the digit of quantizer.The increase of quantizer precision causes modulator design to become
Complexity also brings along the increase of power consumption, and the increase of modulator exponent number will certainly deteriorate the power consumption of system and whole stability.Cause
This structure for how designing modulator becomes the key that CTSD modulators are realized.
Traditional CTSD modulators use single-stage feed forward architecture (Feed-forward), the defects of Feed-forad structures
It needs to design a superfast linear adder device in it, not only design difficulty is big but also can bring very big work(for this adder
Consumption and system delay.
Traditional continuous time sigma delta modulator structure such as Fig. 1；Fig. 1 is a three rank continuous time sigma
Delta modulator, it can be seen that the output of integrator is input to a ultrahigh speed by tri- feed-forward coefficients of C1, C2 and C3
In linear adder device.For a high-precision CTSD modulator, if the structure using Feed-forward is difficult to realize height
Required precision requires also become more harsh to the matching of domain.It can band in addition, the introducing of superfast adder is invisible
Carry out the power consumption of bigger.
Invention content
Therefore, the present invention is directed to the complexity that the continuous sigma delta modulators power consumption of tradition is big and designs, it is difficult to realize object
The requirement networked to ADC high-precision low-power consumptions, it is proposed that a kind of low-power consumption based on switching capacity resistance double loop structure is continuous
Time sigma delta modulator.The modulator can make up the shortcomings that traditional CT SD modulators power consumption is big and stability is poor, lead to
The stability that this mode promotes CTSD ADC is crossed, identical precision is realized with relatively low power consumption, meets the demand of Internet of Things.
The invention is realized in this way a kind of low-power consumption sigma delta based on capacitance resistance double loop structure of construction
The result of quantization is fed back to input terminal at different levels by modulator, the modulator by SCR DAC1, SCR DAC2 and SCR DAC3,
Reduce the superlinearity adder in the structure of Feed-forward, reduce the complexity and power consumption of design.
On the other hand, a kind of low-power consumption sigma delta modulators based on capacitance resistance double loop structure, SCR
DAC1 feeds back to the Input ends of the modulator, and SCR DAC2 feed back to the output terminal of the gain signal amplifier g1 of the modulator,
SCR DAC3 feed back to the output terminal of the gain signal amplifier g2 of the modulator；Since continuous time sigma delta is modulated
Device uses noise shaping techniques, and the only noise of input terminal can influence the signal-to-noise ratio (SNR) of system and number of significant digit (ENOB), the
The introducing of two level and third level SCRDAC can't increase additional noise.During implementation, due to continuous time sigma delta tune
Device processed uses noise shaping techniques, and the only noise of input terminal can influence the signal-to-noise ratio (SNR) and number of significant digit of system
(ENOB)), the introducing of the second level and third level SCR DAC can't increase additional noise.In addition, system is to SCR DAC's
It is required that ultrahigh speed linear adder device is far below, therefore under the premise of identical SNR is ensured, based on switching capacity resistance double loop
The continuous time sigma delta modulator of structure is lower in contrast to traditional Feed-forward structure power consumptions.
On the other hand, a kind of low-power consumption sigma delta modulators based on capacitance resistance double loop structure, it is described
The composition structure of SCR DAC includes variable resistance Rdac1, variable capacitance Cdac1, resistance R, capacitance C and differential amplification
Device, wherein Rdac1 and Cdac1 can be by the sizes for being turned on and off changing feedback resistance and capacitance of switch, so as to drop
The susceptibility of the low pulse to clock；Resistance R is connected on input terminal, and capacitance C is in parallel with difference amplifier；On the other hand, in product
Point charge it is fixed in the case of, change resistance and capacitance and be worth to maximized constant current phase so that integrator it is defeated
Go out electric current minimum, integrator power consumption at this moment will be further reduced.
The invention has the advantages that：The present invention keeps high stability and relatively low under the premise of same precision
Power consumption.Traditional sigma delta modulators limit the essence of sigma delta modulators using superfast linear adder device
Degree considerably increases the complexity and power consumption of modulator design.Continuous time based on switching capacity resistance double loop structure
The it is proposed of sigma delta modulators greatly reduces the power consumption of modulator, the variable switching capacity resistance of creative proposition
DAC reduces the power consumption of system, reduces modulator to the susceptibility of clock, improves the performance of modulator, meet Internet of Things pair
The requirement of electronic product low-power consumption.
Description of the drawings
Fig. 1 is a kind of traditional continuous time sigma delta modulator structure diagram；
Fig. 2 is a kind of continuous time sigma delta modulator based on switching capacity resistance double loop structure of the present invention
Structure diagram；
Fig. 3 is SCR DAC structures schematic diagram of the present invention.
Specific embodiment
Below in conjunction with attached drawing 1- Fig. 3, the present invention is described in detail, to the technical solution in the embodiment of the present invention into
Row clearly and completely describes, it is clear that described embodiment is only the reality of part of the embodiment of the present invention rather than whole
Apply example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work
Every other embodiment, shall fall within the protection scope of the present invention.
Since traditional continuous time sigma delta modulator structure is a three rank continuous time sigma delta
Modulator, it can be seen that by tri- feed-forward coefficients of C1, C2 and C3 to be input to a ultrahigh speed linear for the output of integrator
In adder.For a high-precision CTSD modulator, if being difficult to realize high-precision using the structure of Feed-forward
It is required that the matching of domain is required also become more harsh.It can be brought more in addition, the introducing of superfast adder is invisible
Big power consumption.
A kind of low-power consumption sigma based on capacitance resistance double loop structure is provided herein by improving to this present invention
Delta modulator as shown in Fig. 2-Fig. 3, can be practiced as follows；
The present invention proposes a kind of continuous time sigma delta modulation based on switching capacity resistance double loop structure
Device, the power consumption that the ultrahigh speed linear adder device to solve the problems, such as the introducing of Feed-forward structures is brought.Such as Fig. 2, feed-
The result of quantization is passed through SCRDAC1, SCR DAC2 and SCR DAC3 by the continuous time sigma delta modulator of back structures
Input terminal at different levels is fed back to, reduces the superlinearity adder in the structure of Feed-forward, reduces the complexity of design
Degree and power consumption.Since continuous time sigma delta modulator is using noise shaping techniques, the only noise of input terminal can influence
The signal-to-noise ratio (SNR) of system and number of significant digit (ENOB)), the introducing of the second level and third level SCR DAC can't increase additionally
Noise.In addition, requirement of the system to SCR DAC will be far below ultrahigh speed linear adder device, therefore before identical SNR is ensured
It puts, based on the continuous time sigma delta modulator of switching capacity resistance double loop structure in contrast to traditional Feed-
Forward structure power consumptions are lower.
In addition to this, since traditional continuous time sigma delta modulator is very sensitive to the shake of clock, clock
The ENOB that the clock phase noise brought will directly affect CTSD modulators is shaken, proposes SCR (switching capacity resistance) here
DAC solves the problems, such as that SNR that clock jitter is brought is reduced.Fig. 3 be SCR DAC structure diagram, wherein Rdac1 and
Cdac1 is variable resistance and capacitance, can by the size for being turned on and off changing feedback resistance and capacitance of switch, from
And reduce the susceptibility of the pulse to clock.In addition, the charge in integration is fixed, changes resistance and capacitance is worth to
Maximized constant current phase so that the output current of integrator is minimum, and integrator power consumption at this moment will be further reduced.
By above description, the present invention keeps high stability and relatively low power consumption under the premise of same precision.It passes
The sigma delta modulators of system limit the precision of sigma delta modulators using superfast linear adder device, significantly
Increase the complexity and power consumption of modulator design.Continuous time sigma based on switching capacity resistance double loop structure
The it is proposed of delta modulator, greatly reduces the power consumption of modulator, and the variable switching capacity resistance DAC of creative proposition subtracts
The small power consumption of system reduces susceptibility of the modulator to clock, improves the performance of modulator, meets Internet of Things and electronics is produced
The requirement of product low-power consumption.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications of these embodiments will be apparent for those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide range caused.
Claims (3)
1. a kind of low-power consumption sigma delta modulators based on capacitance resistance double loop structure, it is characterised in that：The modulator
The result of quantization is fed back into input terminal at different levels by SCR DAC1, SCR DAC2 and SCR DAC3.
2. a kind of low-power consumption sigma delta modulators based on capacitance resistance double loop structure according to claim 1,
It is characterized in that：SCR DAC1 feed back to the Input ends of the modulator, and SCR DAC2 feed back to the gain signal amplification of the modulator
The output terminal of device g1, SCR DAC3 feed back to the output terminal of the gain signal amplifier g2 of the modulator；Due to continuous time
Sigma delta modulators use noise shaping techniques, and the only noise of input terminal can influence the signal-to-noise ratio (SNR) of system and have
Imitate digit (ENOB)), the introducing of the second level and third level SCR DAC can't increase additional noise.
3. a kind of low-power consumption sigma delta modulators based on capacitance resistance double loop structure according to claim 1,
It is characterized in that：The composition structure of the SCR DAC includes variable resistance Rdac1, variable capacitance Cdac1, resistance R, capacitance C
And difference amplifier, wherein Rdac1 and Cdac1 can be turned on and off changing feedback resistance and capacitance by switch
Size, so as to reduce the susceptibility of the pulse to clock；Resistance R is connected on input terminal, and capacitance C is in parallel with difference amplifier；Separately
On the one hand, it is fixed in the charge of integration, change resistance and capacitance is worth to maximized constant current phase so that
The output current of integrator is minimum, and integrator power consumption at this moment will be further reduced.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995272A (en) * | 2019-12-25 | 2020-04-10 | 重庆大学 | Switched capacitor resistance feedback continuous time modulator based on variable resistor |
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