KR20090109454A - Continuous-time delta-sigma modulator - Google Patents

Abstract

PURPOSE: A continuous-time delta-sigma modulator is provided to reduce the power consumption by designing the band width and slew rate of OP-Amp lower than previous design. CONSTITUTION: A continuous-time delta-sigma modulator comprises an active integrator(100), an analog to digital converter(200), a digital analog converter(300), and a variable resistor(400). The active integrator includes a first, and second input terminal. The first input terminal is inputted the sum of the input signal and analog feedback signal. The analog to digital converter converts the output of an integrator to the digital signal. The digital analog converter converts the digital signal transformed from the analog to digital converter to the analog feedback signal. The variable resistor is connected between an integrator and digital analog converter. The variable resistor changes the amount of delivered current of the digital analog converter by controlling the resistance value according to the time.

Description

Continuous-Time Delta-Sigma Modulators {CONTINUOUS-TIME DELTA-SIGMA MODULATOR}

The present invention implements a feedback digital-to-analog converter (Feedback DAC) for a continuous-time delta-sigma modulator (CT DSM), so that the amount fed back is insensitive to clock jitter. It guarantees stable signal-to-noise ratio (SNR), and the absolute value of feedback amount is the same as the existing design, but it reduces the instantaneous change of feedback amount to reduce the instantaneous change of feedback amount (OP-Amp). It is a continuous time delta-sigma modulator that can reduce the power consumption by designing the bandwidth and slew-rate lower than the existing design.

In general, continuous-time delta-sigma modulators (CT DSMs) provide high precision, low noise and are widely used in professional audio systems, communication systems, and precision measurement devices.

FIG. 1 is a block diagram illustrating a basic structure of a continuous time delta-sigma modulator, and FIG. 2 is a graph for explaining the influence of clock jitter on a feedback DAC using a constant current source.

1 and 2, a continuous time delta-sigma modulator (CT DSM) is basically an active-RC integrator 10 and an analog-to-digital converter that converts the output of the integrator 10 into a digital signal. As a constant current source (I) that feeds back a positive (+) or a negative (-) current to the integrator (10) according to the signals of the Digital Converter (ADC) 20 and the Analog / Digital Converter (ADC) 20. Implemented feedback digital to analog converter (Digital Analog Converter, DAC) 30 is composed of.

As shown in Fig. 2, the total amount of charge fed back from the feedback digital-to-analog converter (DAC) 30 to the integrator 10 for each clock period is " Q (charge amount) = I (current) × t (time) "). If the clock for switching the current source I has jitter, the amount of charge fed back will have an error proportional to the clock jitter. {Reference 1; EJ van der Zwan and EC Dijkmans, "A 0.2-mW CMOS modulator for speech coding with 80-dB dynamic range," IEEE J. Solid-State Circuits , vol. 31, pp. 1873-1880, Dec. 1996}.

When this feedback error is transmitted to the input and interpreted, it is equivalent to the noise of the input signal, resulting in a drop in the signal-to-noise ratio (SNR) of the continuous time delta-sigma modulator (CT DSM). Will be imported.

On the other hand, when using an integrator in the form of a typical switched-capacitor (SC), as shown in Figure 4 to be described later, the transfer characteristic of the feedback current is exponentially decreased with time due to clock jitter There is little change in the amount of feedback that occurs.

Therefore, when using the constant current source feedback digital-to-analog converter (DAC) 30 in the continuous time delta-sigma modulator (CT DSM), the digital-to-analog converter (DAC) in the form of a switch-capacitor (SC), which will be described later, will be described. Has a much lower jitter requirement to achieve the same target signal-to-noise ratio (SNR) than with a clock, which is a heavy burden on clock design.

FIG. 3 is a block diagram illustrating a basic structure of a continuous time delta-sigma modulator applying a SC DAC, and FIG. 4 is a graph illustrating a current transfer waveform of the SC DAC.

3 and 4, the feedback digital-to-analog converter (DAC) 30 in the form of a constant current source having a clock jitter sensitive characteristic in a continuous time delta-sigma modulator (CT DSM) as shown in FIG. In order to solve the problem caused by the present invention, a digital-to-analog converter (DAC) 30 'in the form of a switch-capacitor (SC) is also used in the continuous time delta-sigma modulator (CT DSM). Applicable {Ref. 2; R. Veldhoven, "A Triple-Mode Continuous-Time Sigma-Delta Modulator With Switched-Capacitor Feedback DAC for a GSM-DEGE / CDMA2000 / UMTS Receiver," IEEE J. Solid-State Circuits , vol. 38, no. 12, pp. 2059-2076, March 2000}.

The digital-to-analog converter (DAC) 30 'in the form of a switch-capacitor (SC) has an exponential amount of discharge current when the charge charged in the capacitor (C _DAC ) is transferred to the integrator 10. As it decreases, most of the charge that is charged in the digital-to-analog converter (DAC) 30 'is initially delivered to integrator 10, and at the end of the integration the amount rapidly decreases so that the total charge transfer rate is clocked. It is not affected by jitter.

Thus, in the case of an ideal integrator, the digital-to-analog converter (DAC) 30 'in the form of a switch-capacitor (SC) than the case of using the constant current source digital-to-analog converter (DAC) 30 for the jitter characteristic of the same clock. In this case, a high signal-to-noise ratio (SNR) can be obtained.

However, when a digital-to-analog converter (DAC) 30 'in the form of a switch-capacitor (SC) is applied to a continuous time delta-sigma modulator (CT DSM), it is used as a digital-to-analog converter (DAC) 30'. Immediately after the capacitor C _DAC is connected to the integrator 10, a sudden current change occurs due to discharge.

In order to process such a feedback signal without error, the operational amplifier (OP-Amp) used for integration must have a significant slew rate and a wider bandwidth. In order to increase the slew rate and bandwidth of the OP-Amp, the amount of bias current must be increased, which is directly connected to power consumption and thus is not a proper direction for a low power modulator design.

FIG. 5 is a block diagram illustrating a basic structure of a continuous time delta-sigma modulator to which an SCR DAC is applied. FIG. 6 is a graph illustrating a current transfer waveform of the SCR DAC.

5 and 6, a digital-to-analog converter (DAC) 30 'in the form of a switch-capacitor (SC) in a continuous time delta-sigma modulator (CT DSM) as shown in FIG. In order to improve the problem of power increase caused by the above, an SCR digital-to-analog converter (DAC) as shown in FIG. 5 has been proposed (Ref. 3; M. Ortmanns, F. Gerfers, Y. Manoli, "Clock Jitter Insensitive Continuous-Time Sigma-Delta Modulators," ICECS 2001, pp. 1049-1052}.

That is, by connecting a resistor (R _DAC ) 15 between the capacitor (C _DAC ) of the feedback digital-to-analog converter (DAC) 30 'and the integrator 10, the maximum change in the instantaneous current is V / R. It is designed to be limited by.

In this case, as shown by reference numeral 50 of FIG. 6, the maximum value of the feedback current is determined as "V _ref / R _DAC " so that the series resistance value used in the digital-to-analog converter (DAC) 30 'is increased. As a result, it decreases in inverse proportion.

Therefore, the slew rate or bandwidth required by the operational amplifier OP-Amp of the integrator 10 to respond to the input signal is greatly reduced, which is a preferable implementation plan for low power design.

On the other hand, the limit of the current change rate is not completed at the end of the integrating section as compared to the conventional switch-capacitor (SC) type digital-to-analog converter (DAC) 30 'as shown by reference numeral 50 of FIG. This results in an increase in the amount of charge left, resulting in increased sensitivity due to clock jitter in the signal-to-noise ratio (SNR).

Therefore, this design is a trade-off of low power consumption and signal-to-noise ratio (SNR) sensitivity to clock jitter, making it difficult to simultaneously meet low power consumption and high signal-to-noise ratio (SNR). There is this.

As described above, the sensitivity to clock jitter of a conventional continuous time delta-sigma modulator (CT DSM) can be reduced by using a digital-to-analog converter (DAC) 30 'in the form of a switch-capacitor (SC). This results in increased power consumption due to increased bandwidth and slew-rate requirements, and some signal-to-noise ratio (SNR) and trade-off of power consumption must be achieved to improve this. It can be seen.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to implement a feedback digital-to-analog converter (Feedback DAC) for a continuous-time delta-sigma modulator (CT DSM). The amount of feedback is insensitive to clock jitter to ensure a stable signal-to-noise ratio (SNR), while the absolute value of the feedback amount is the same as the previous design, but the integrator is reduced by reducing the instantaneous change of the feedback amount. It is a continuous time delta-sigma modulator that can reduce the power consumption by designing the bandwidth and slew rate of OP-Amp used in.

In order to achieve the above object, the first aspect of the present invention, the first input terminal is received by adding the input signal and the analog feedback signal, the second input terminal is an active integrator using an operational amplifier connected to the reference potential; An analog / digital converter for converting the output of the integrator into a digital signal; A digital / analog converter for converting the digital signal converted from the analog / digital converter into the analog feedback signal; And a variable resistor connected between the integrator and the digital-to-analog converter, the variable resistor changing a current value of the digital-to-analog converter by adjusting a resistance value over time.

Here, at the initial stage of discharging of the digital-to-analog converter, the resistance value of the variable resistor is largely adjusted to reduce the instantaneous current change, and then the resistance value is gradually decreased to reduce the change rate of the discharge current as the discharge proceeds. At the end of the discharge, it is preferable to adjust the resistance value of the variable resistor so that all the charges charged in the digital / analog converter are discharged and transferred to the integrator by the reduced resistance value of the variable resistor.

Preferably, the variable resistor includes a resistor connected in series between the integrator and the digital-to-analog converter, and a switching transistor connected in parallel to the resistor, wherein the gate transistor of the switching transistor is increased to increase the switching transistor. By controlling the on-resistance of the resistance of the variable resistor can be adjusted.

Preferably, the voltage for driving the gate of the switching transistor may be a ramp waveform.

Preferably, the switching transistor may be formed of an N-type metal oxide semiconductor (NMOS) or a P-type metal oxide semiconductor (PMOS) transistor.

Preferably, the variable resistor, by connecting a plurality of resistors in parallel between the integrator and the digital-to-analog converter, by sequentially switching each of the resistors to reduce the equivalent resistance with time to reduce the resistance value of the variable resistor I can regulate it.

Advantageously, said digital to analog converter comprises: a switched capacitor; First and second discharge switches respectively connecting both ends of the switched capacitor to the reference potential according to a first control signal; First and second voltage sources; First and second charging switches for selectively connecting the other end of the switched capacitor and the first and second voltage sources according to the second control signal and the digital signal in which the first control signal and the active period do not overlap each other; And a third charging switch connecting one end of the switched capacitor and one end of the variable resistor according to the second control signal.

According to a second aspect of the present invention, there is provided a digital-to-analog converter for converting and feeding back a digital output into an analog signal, and a first input terminal receives a sum of an input signal and the analog feedback signal, and a second input terminal is connected to a reference potential. A continuous time delta-sigma modulator including an active integrator using a connected operational amplifier, wherein the current integrator is connected between the active integrator and the digital / analog converter, and the resistance value is adjusted over time to adjust the current transfer amount of the digital / analog converter. A variable resistor is further included, wherein the variable resistor comprises a resistor connected in series between the integrator and the digital / analog converter, and a switching transistor connected in parallel to the resistor, and charges the digital / analog converter. The clock, which is a period for sending a charged charge to the active integrator, is high It is to provide a continuous time delta-sigma modulator characterized by adjusting the resistance value of the variable resistor by gradually increasing the gate voltage of the switching transistor during the in period to reduce the ON resistance value of the switching transistor. .

According to a third aspect of the present invention, there is provided a digital / analog converter for converting and feeding back a digital output into an analog signal, a first input terminal receives an input signal and the analog feedback signal, and a second input terminal is connected to a reference potential. A continuous time delta-sigma modulator including an active integrator using a connected operational amplifier, wherein the current integrator is connected between the active integrator and the digital / analog converter, and the resistance value is adjusted over time to adjust the current transfer amount of the digital / analog converter. The variable resistor further includes a variable resistor, wherein the variable resistor connects a plurality of resistors in parallel between the integrator and the digital / analog converter, and uses the plurality of delayed clocks to connect the digital / analog converter to the active integrator. Restore the plurality of resistors while the connected clock is high. It is to provide a continuous time delta-sigma modulator characterized in that the resistance value of the variable resistor is adjusted by decreasing the equivalent resistance with time by sequentially connecting in parallel by several delayed clocks.

According to the continuous time delta-sigma modulator of the present invention as described above, in implementing a feedback digital-to-analog converter (Feedback DAC) for the continuous time delta-sigma modulator (CT DSM) The amount of feedback is insensitive to clock jitter to ensure a stable signal-to-noise ratio (SNR). The absolute value of the feedback amount is the same as the existing design, but the momentary change of the feedback amount is reduced to the integrator. The bandwidth and slew rate of OP-Amp used can be designed lower than the existing design, which has the advantage of reducing power consumption.

In addition, according to the present invention, in the feedback digital-to-analog converter (DAC) of the SCR structure is designed to vary the value of the resistance (R) over time to adjust the current transfer characteristics over time, thereby reducing the signal-to-noise ratio (SNR) It improves sensitivity to jitter while also reducing the power consumption of op-amps and is a good fit for implementing high-resolution low-power analog-to-digital converters (ADCs).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It doesn't happen.

FIG. 7 is a block diagram illustrating a structure of a continuous time delta-sigma modulator according to an embodiment of the present invention. FIG. 8 is a diagram illustrating current transfer characteristics of a digital-to-analog converter (DAC) applied to an embodiment of the present invention. Is a graph comparing the conventional SCR DAC structure.

7 and 8, a continuous-time delta-sigma modulator (CT DSM) according to an embodiment of the present invention basically includes an integrator 100 and an analog-to-digital converter ( An analog digital converter (ADC) 200, a feedback digital-to-analog converter (DAC) 300 in the form of a switched-capacitor (SC), and a variable resistor (R _Vary ) 400. .

Here, although the input signal V _IN is taken as a single-ended signal as an example, it may be a differential signal. The structure of the continuous-time delta-sigma modulator of the present invention may be modified depending on the order or the differential signal, but may not be avoided.

In addition to the continuous time delta-sigma modulator (CT DSM), the basic structure of the widely used discrete time delta-sigma modulator (DT DSM) also shows the structure of the continuous time delta-sigma modulator (CT DSM). Similar to

However, the integrator of the discrete time delta-sigma modulator (DT DSM) receives a discrete input pulse, whereas the integrator 100 of the continuous time delta-sigma modulator (CT DSM) receives an analog input signal that continuously varies with time. The difference is that it receives input.

In addition, since the continuous time delta-sigma modulator (CT DSM) of the present invention integrates an analog input signal, a settling time at which the output of the operational amplifier 150 used when implementing the internal integrator 100 is stabilized. Requirements can be relaxed compared to discrete time delta-sigma modulators (DT DSMs). In addition, the continuous time delta-sigma modulator (CT DSM) may not require an anti-aliasing filter, may be implemented in a lower order structure, and consumes less power.

The integrator 100 integrates the current which is summed to the input signal (V _IN) to the input resistor (R _IN) of the feedback values input current converter (I _IN) and divided by the analog signal (I _DAC). The more linear this integrator 100 is, the better the characteristics of the overall delta-sigma modulator are. That is, the integrator 100 is illustrated in the form of an active RC using the operational amplifier 150 and the capacitor C _I.

The analog-to-digital converter (ADC) 200 quantizes the output of the integrator 100 and outputs the result to the digital output D _out , and the feedback digital-to-analog converter (DAC) 300 outputs the digital output (D). _out ) to feed back an analog feedback signal (I _DAC ). The converted feedback signal I _DAC is added with the input current I _IN at the summation node N _SUM and applied to the integrator 100.

The feedback digital-to-analog converter (DAC) 300 in the form of a switch-capacitor (SC) integrators the positive (+) or negative (-) current according to the signal of the analog-to-digital converter (ADC) 200. It performs the function of feeding back.

The digital-to-analog converter (DAC) 300 includes switches P _C1 and P respectively connected to the reference voltages Vref + and Vref- of the feedback digital-to-analog converter (DAC) 300 at both ends of the switched capacitor C _DAC . _C2 ), the switch P _C3 connected to the variable resistor R _Vary 400, and the switches P _D1 and P _D2 connecting the switched capacitor C _DAC to ground.

That is, the second control signal (P ₂₎ and the digital output (D _out) switch (P _C1 or P _C2) and a switch (P _D1) connecting the switched capacitor (C _DAC) to ground which is connected to a reference voltage by The switch P _D2 and the switch P _c3 are connected to each other by the first control signal P ₁ which is turned on and whose active period does not overlap with the second control signal P ₂ .

Since the switched capacitor C _DAC is rapidly charged in the period in which the first control signal P ₁ is activated, a sudden current change appears at one end of the variable resistor R _Vary 400 in the initial stage of charging.

In addition, the variable resistor (R _Vary ) 400 is connected between the summing node (N _SUM ) and the digital-to-analog converter (DAC) 300 in the integrator 100, the digital-to-analog converter (DAC) 300 This function adjusts the value of the resistance according to time so that the discharge characteristic of) does not follow the unique RC time constant.

That is, at the initial stage of the discharge in which the switched capacitor C _DAC is connected to the integrator 100, the resistance R of the variable resistor R _Vary 400 connected in series is increased to decrease the instantaneous current change. By gradually decreasing the resistance (R) value, the capacitor is switched by the resistance (R) value of the variable resistor (R _Vary ) 400 reduced at the end of the discharge while the rate of change of the discharge current is not large as the discharge proceeds. Charge charged in the C _DAC is completely transferred to the integrator 100.

In this way, the power consumption of the operational amplifier 150 can be reduced and the sensitivity of the signal-to-noise ratio (SNR) to clock jitter can be effectively improved. As shown in FIG. 8, the proposed digital-to-analog converter (DAC) 300 including a variable resistor (R _Vary ) 400 applied to an embodiment of the present invention has a maximum current of SCR digital / Less than an analog converter (DAC), it reduces the charge remaining in the capacitor in the last section of current transfer.

The control of the resistance value for implementing the variable resistor R _Vary 400 applied to the above-described embodiment of the present invention may be performed in continuous time or in discrete time.

For example, FIG. 9 is a circuit diagram illustrating an input portion of the continuous time delta-sigma modulator of FIG. 7 as an example. The switching transistor M is connected in parallel to a resistor R applied to a conventional SCR digital-to-analog converter DAC. The variable resistor (R _Vary ) (400 ') can be implemented by connecting. The switching transistor M is preferably made of an N-type metal oxide semiconductor (NMOS) or a P-type metal oxide semiconductor (PMOS) transistor.

The variable resistor R _Vary 400 ′ configured as described above gradually switches the switching transistor M during a period in which the clock P ₁ , which is a period for transmitting charge of the switched capacitor C _DAC , to the integrator 100, is high. The variable resistor (R _Vary ) 400 ′ of the present invention can be implemented by decreasing the ON resistance value of the switching transistor M by increasing the gate voltage.

On the other hand, although the waveform of the voltage for driving the gate of the switching transistor (M) can be implemented in various ways, in one embodiment of the present invention has shown an example using a ramp waveform.

10 is a continuous-time delta of Figure 7 - a circuit diagram showing another example of the input part of the sigma modulator, multiple delayed first to third clock _{(P 1, P 1 ',} P 1 ") for use by D / A converter While the clock P ₁ connected to the integrator 100 is high, the first to third resistors R ₁ , R ₂ , and R _{3 are} connected to the first to third clocks (DAC) 300. By sequentially connecting in parallel by P ₁ , P ₁ ′, and P ₁ ″ to reduce the equivalent resistance with time, the variable resistor R _Vary 400 ″ of the present invention can be implemented.

Although a preferred embodiment of the continuous time delta-sigma modulator according to the present invention has been described above, the present invention is not limited thereto, and various modifications are made within the scope of the claims and the detailed description of the invention and the accompanying drawings. It is possible to implement and this also belongs to the present invention.

1 is a block diagram illustrating the basic structure of a continuous time delta-sigma modulator.

2 is a graph illustrating the effect of clock jitter on a feedback DAC using a constant current source.

3 is a block diagram illustrating a basic structure of a continuous time delta-sigma modulator using an SC DAC.

4 is a graph illustrating a current transfer waveform of the SC DAC.

FIG. 5 is a block diagram illustrating a basic structure of a continuous time delta-sigma modulator using an SCR DAC.

6 is a graph illustrating a current transfer waveform of the SCR DAC.

7 is a block diagram illustrating the structure of a continuous time delta-sigma modulator according to an embodiment of the present invention.

8 is a graph illustrating current transfer characteristics of a digital-to-analog converter (DAC) applied to an embodiment of the present invention in comparison with a conventional SCR DAC structure.

FIG. 9 is a circuit diagram illustrating an input part of the continuous time delta-sigma modulator of FIG. 7 as an example.

FIG. 10 is a circuit diagram illustrating another example of an input portion of the continuous time delta-sigma modulator of FIG. 7.

Claims (9)

A first input terminal receives the sum of the input signal and the analog feedback signal, and the second input terminal includes an active integrator using an operational amplifier connected to a reference potential; An analog / digital converter for converting the output of the integrator into a digital signal; A digital / analog converter for converting the digital signal converted from the analog / digital converter into the analog feedback signal; And And a variable resistor coupled between the integrator and the digital / analog converter, the variable resistor changing the current value of the digital / analog converter by adjusting a resistance value over time. According to claim 1, In the initial stage of discharging of the digital-to-analog converter, the resistance value of the variable resistor is largely adjusted to reduce the instantaneous current change, and then the resistance value is gradually decreased to prevent the change rate of the discharge current from increasing as the discharge proceeds. And lastly adjust the resistance value of the variable resistor so as to discharge all the charges charged in the digital / analog converter by the resistance value of the variable resistor reduced. According to claim 1, The variable resistor, A resistor connected in series between the integrator and the digital-to-analog converter, and a switching transistor connected in parallel to the resistor, And controlling the on-resistance of the switching transistor to increase the gate voltage of the switching transistor to adjust the resistance of the variable resistor. The method of claim 3, wherein The voltage for driving the gate of the switching transistor is a continuous time delta-sigma modulator characterized in that the ramp waveform. According to claim 1, The variable resistor may be configured to connect a plurality of resistors in parallel between the integrator and the digital / analog converter, and to sequentially switch the resistors to reduce the equivalent resistance over time to adjust the resistance value of the variable resistor. A continuous time delta-sigma modulator. According to claim 1, The digital to analog converter, Switched capacitors; First and second discharge switches respectively connecting both ends of the switched capacitor to the reference potential according to a first control signal; First and second voltage sources; First and second charging switches for selectively connecting the other end of the switched capacitor and the first and second voltage sources according to the second control signal and the digital signal in which the first control signal and the active period do not overlap each other; And And a third charging switch connecting one end of the switched capacitor and one end of the variable resistor according to the second control signal. A digital-to-analog converter for converting and feeding back a digital output into an analog signal; a first input terminal receives the sum of the input signal and the analog feedback signal; and a second input terminal receives an active integrator using an operational amplifier connected to a reference potential. In a continuous time delta-sigma modulator comprising: A variable resistor is connected between the active integrator and the digital-to-analog converter, and further includes a variable resistor that adjusts a resistance value over time to change a current transfer amount of the digital-to-analog converter. The variable resistor, A resistor connected in series between the integrator and the digital / analog converter, and a switching transistor connected in parallel with the resistor, By gradually increasing the gate voltage of the switching transistor to reduce the ON resistance value of the switching transistor during a period when the clock, which is a period for sending charge charged to the digital / analog converter to the active integrator, is high, And adjusting a resistance value of the variable resistor. A digital-to-analog converter for converting and feeding back a digital output into an analog signal; a first input terminal receives the sum of the input signal and the analog feedback signal; and a second input terminal receives an active integrator using an operational amplifier connected to a reference potential. In a continuous time delta-sigma modulator comprising: A variable resistor is connected between the active integrator and the digital-to-analog converter, and further includes a variable resistor that adjusts a resistance value over time to change a current transfer amount of the digital-to-analog converter. The variable resistor, A plurality of resistors are connected in parallel between the integrator and the digital / analog converter, and the plurality of resistors are connected while the clock connected to the active integrator is high by using a plurality of delayed clocks. Sequential parallel connection by the plurality of delayed clocks to reduce the equivalent resistance with time to adjust the resistance value of the variable resistor. The method according to claim 7 or 8, The digital to analog converter, Switched capacitors; First and second discharge switches respectively connecting both ends of the switched capacitor to the reference potential according to a first control signal; First and second voltage sources; First and second charging switches for selectively connecting the other end of the switched capacitor and the first and second voltage sources according to the second control signal and the digital signal in which the first control signal and the active period do not overlap each other; And And a third charging switch connecting one end of the switched capacitor and one end of the variable resistor according to the second control signal.

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