CN113452369B

CN113452369B - Analog-to-digital converter and digital calibration method thereof

Info

Publication number: CN113452369B
Application number: CN202110531760.5A
Authority: CN
Inventors: 幸新鹏; 尚雪倩; 冯海刚; 王志华; 李冬梅
Original assignee: Shenzhen International Graduate School of Tsinghua University
Current assignee: Shenzhen International Graduate School of Tsinghua University
Priority date: 2021-05-17
Filing date: 2021-05-17
Publication date: 2022-09-20
Anticipated expiration: 2041-05-17
Also published as: CN113452369A

Abstract

The invention discloses an analog-digital converter and a digital calibration method thereof, wherein the analog-digital converter comprises a loop filter, a quantizer, a feedback DAC component, a two-way selection switch, a reference DAC unit and a digital processing module, the feedback DAC component comprises a plurality of feedback DAC units which are connected in parallel, the loop filter, the quantizer and the digital processing module are sequentially connected with each other from an input end to an output end, a first end of the feedback DAC component and a first end of the reference DAC unit are respectively connected into the loop filter in opposite polarities, a second end of the feedback DAC component is connected with a first end of the two-way selection switch, a first one of two ways selectable by a second end of the two-way selection switch is connected between the quantizer and the digital processing module, and a second one way of the two ways is connected with a first digital sequence signal; the second terminal of the reference DAC cell is connected to the second digital sequence signal. The invention can effectively and economically eliminate the dynamic error and the static error of the feedback DAC component in the analog-to-digital converter.

Description

Analog-to-digital converter and digital calibration method thereof

Technical Field

The invention relates to the field of mixed signal circuits, in particular to an analog-to-digital converter and a digital calibration method thereof.

Background

In a communication system, as the amount of data to be processed becomes larger, the emphasis of a radio frequency transceiver is gradually placed on the processing of broadband data, and thus a higher demand is placed on an Analog Digital Converter (ADC) as an interface between an Analog signal and a Digital signal. The analog-to-digital converter is a core circuit of a baseband part in a communication receiver, and the performance (input signal bandwidth, dynamic range, power consumption and the like) of the analog-to-digital converter largely determines the performance of the whole system, so the development of the analog-to-digital converter is more and more important.

Compared with other types of analog-to-digital converters, the continuous-time Delta Sigma ADC is widely applied to wireless communication systems due to the characteristics of precision, pure resistive input load, reconfigurability, self-contained anti-aliasing filter and the like, and the basic block diagram of the continuous-time Delta Sigma ADC is shown in fig. 1 and consists of a continuous-time loop filter 1.1, a quantizer 1.2, a feedback digital-to-analog converter (DAC)1.3 and an adder 1.4. The Delta Sigma ADC uses oversampling and noise shaping techniques to reduce the quantisation noise introduced by the quantiser within the signal bandwidth so that a high accuracy in the ADC can be achieved with a low bit quantiser 1.2. As can be seen from FIG. 1, the front end of the feedback DAC1.3 (the most front end DAC in the feedback type Delta-Sigma ADC) does not have any analog filter, any error of the front end does not directly influence the precision of the whole Delta-Sigma ADC, and therefore, the reduction of the error of the feedback DAC to a certain degree is one of the keys for designing the Delta-Sigma ADC.

Conventional dynamic element matching techniques (DEM) can effectively eliminate the static error of the feedback DAC in the Delta-Sigma ADC, but cannot eliminate the dynamic error, and introduce additional loop delay to destroy the stability of the Delta-Sigma ADC, see documents Y.Geerts, M.S.J.Steyaert, W.Sansen, A high-performance multi-bit CMOS ADC.IEEE J.solid-State Circuits 35(12), 1829-. The calibration in the documents t.he, m.ashburn, s.ho, y.zhang and g.temes, "a 50MHZ-BW continuous-time Δ Σ ADC with dynamic error correction accessing 79.8dB SNDR and 95.2dB SFDR,"2018IEEE International Solid-State Circuits reference- (ISSCC), San Francisco, CA,2018, pp.230-232 is only for the dynamic error (inter-symbol interference, ISI) of the feedback DAC and cannot eliminate the static error of the DAC, so the DAC therein also needs a larger area to ensure that the static error is smaller; therefore, the calibration is dependent on an analog mode and is sensitive to various non-ideal factors. Documents j.g. kauffman, p.witte, j.becker and m.ortmann, "An 8.5mW Continuous-Time $ \ Delta \ Sigma $ Modulator With 25MHz band width Using Digital Background DAC linear simulation to achieves 63.5dB SNDR and 81dB SFDR," In IEEE Journal of solvent-State Circuits, vol.46, No.12, pp.2869-2881, dec.2011 and documents m.de Bock, x.xing, l.weyten, g.gielen, p.rombouts, Calibration of DAC mismatch In Δ ADCs, baseband a side-In-system, IEEE train, circuit ii, etc. do not provide a dynamic feedback for the ADC feedback error (ADC) In high speed, but only In ADC 8, 7, 8, 7, the feedback error is not eliminated dynamically. Furthermore, the digital Calibration In the documents M.De Bock, X.Xing, L.Weyten, G.Gielen, P.Rombouts, Calibration of DAC mismatch errors In Sigma Δ ADCs based on a sine-wave measurement, IEEE Trans.circuits Syst.II Express Briefs 60(9),567 + 571(2013) requires a very accurate sine wave analog signal as the Calibration input signal of the ADC.

The above background disclosure is only for the purpose of assisting understanding of the concept and technical solution of the present invention and does not necessarily belong to the prior art of the present patent application, and should not be used for evaluating the novelty and inventive step of the present application in the case that there is no clear evidence that the above content is disclosed at the filing date of the present patent application.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides an analog-to-digital converter and a digital calibration method thereof, which can effectively and economically eliminate the dynamic error and the static error of the feedback DAC component in the analog-to-digital converter within continuous time.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention discloses an analog-digital converter, which comprises a loop filter, a quantizer, a feedback DAC component, a two-way selection switch, a reference DAC unit and a digital processing module, wherein the feedback DAC component comprises a plurality of feedback DAC units which are connected in parallel, the loop filter, the quantizer and the digital processing module are sequentially connected with one another from an input end to an output end, a first end of the feedback DAC component and a first end of the reference DAC unit are respectively connected to the loop filter in opposite polarities, a second end of the feedback DAC component is connected with the first end of the two-way selection switch, the first of two ways selectable by the second end of the two-way selection switch is connected between the quantizer and the digital processing module, and the second way of the two-way selection switch is connected with a first digital sequence signal; and the second end of the reference DAC unit is connected with a second digital sequence signal.

The invention also discloses a digital calibration method of the analog-to-digital converter, which comprises an error extraction step and an error elimination step, wherein:

the error extraction step includes:

a1: communicating a second end of the two-way selection switch in the analog-to-digital converter with a second one of the two selectable ways, so that the digital input of the ith feedback DAC unit in the feedback DAC assembly is the first digital sequence signal, and the digital inputs of the other feedback DAC units are set to be zero;

a2: setting the input signal at the input terminal to zero and making the digital input of the reference DAC cell the second digital sequence signal;

a3: calculating a static error and a dynamic error of the ith feedback DAC unit relative to the reference DAC unit in each clock cycle according to the output of the quantizer;

a4: repeating the steps A1 to A3 to respectively obtain the static errors and the dynamic errors of all the feedback DAC units in the feedback DAC component relative to the reference DAC unit;

the error elimination step comprises:

b1: connecting a second end of the two-way selection switch in the analog-to-digital converter with a first way of the two selectable ways, so that the feedback DAC assembly, the loop filter and the quantizer form a closed loop;

b2: setting an input signal of an input end as a normal input signal, and setting a digital input of the reference DAC unit as zero;

b3: calculating the sum of errors introduced by all the feedback DAC units in the current clock period according to the inputs of all the feedback DAC units in the current clock period;

b4: in the digital processing module, a calibrated digital output is obtained according to the converted digital output and the error sum introduced by all the feedback DAC units of the current clock period obtained in step B3.

Preferably, the error extraction step further comprises setting the loop filter in the form of a first order integrator.

Preferably, the first digital sequence signal in step a1 is specifically: in the first 2N clock cycle and the second 2N clock cycle, the first digital sequence signal is composed of N '10' combinations, wherein N is a positive integer.

Preferably, the second digital sequence signal in step a2 is specifically: during a first 2N clock cycle, the second digital sequence signal consists of N consecutive 1 s and N consecutive 0 s; during the second 2N clock cycle, the second digital sequence signal consists of 2 identical sequences, each sequence being N/2 consecutive 1's and N/2 consecutive 0's.

Preferably, the static error E of the ith feedback DAC cell relative to the reference DAC cell per clock cycle calculated in step a3 _Si And dynamic error E _Di Respectively as follows:

E _Di ＝E _T1 -E _T2

wherein E is _T1 Is the output of the quantizer at clock cycle 2N, E _T2 The output of the quantizer at clock cycle 4N.

Preferably, N is an even number.

Preferably, the error sum E introduced by all the feedback DAC cells of the current k-th clock cycle calculated in step B3 _total Comprises the following steps:

E _total ＝E _Stotal +E _Dtotal

wherein E is _Stotal For the sum of static errors introduced by the feedback DAC components during the kth clock cycle:

E _Si for each clock cycle the static error of the ith feedback DAC unit relative to the reference DAC unit, Y _k The digital output of the analog-to-digital converter in the k clock period;

E _Dtotal for the sum of the dynamic errors introduced by the feedback DAC components during the k-th clock cycle:

E _Di for each clock cycle the dynamic error of the ith feedback DAC unit relative to the reference DAC unit, Y _k-1 The digital output of the analog-to-digital converter in the k-1 clock cycle.

Preferably, the calibrated digital output Y obtained in step B4 _cal Comprises the following steps:

Y _cal ＝Y+E _total

wherein Y is the digital output converted by the digital processing module, E _total The sum of the errors introduced for all the feedback DAC cells of the current clock cycle obtained in step B3.

The present invention additionally discloses a computer-readable storage medium having stored thereon computer-executable instructions that, when invoked and executed by a processor, cause the processor to implement the digital calibration method described above.

Compared with the prior art, the invention has the beneficial effects that: by adopting the analog-to-digital converter and the digital calibration method thereof, the static error and the dynamic error of the feedback DAC component can be eliminated at the same time, and extra loop delay is not introduced. And because the calibration is digital, except a reference DAC unit, no additional analog circuit is needed, no additional analog signal is needed, and the calibration is robust to various non-ideal factors.

Drawings

FIG. 1 is a schematic diagram of a conventional continuous-time Delta-Sigma analog-to-digital converter;

FIG. 2 is a schematic diagram of static errors in a feedback DAC unit;

FIG. 3 is a schematic diagram of dynamic errors in a feedback DAC unit;

FIG. 4 is a schematic diagram of the structure of the analog-to-digital converter of the preferred embodiment of the present invention;

FIG. 5 is a circuit diagram of the analog-to-digital converter of FIG. 4 in extracting the error of the ith feedback DAC unit;

fig. 6 is a schematic diagram of the number sequence S1 and the number sequence S2 in fig. 5.

Detailed Description

The embodiments of the present invention will be described in detail below. It should be emphasized that the following description is merely exemplary in nature and is not intended to limit the scope of the invention or its application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element. In addition, the connection may be for either a fixed function or a circuit/signal communication function.

It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the embodiments of the present invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be in any way limiting of the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.

Feedback DAC errors include static errors and dynamic errors, both of which affect the accuracy of the Delta Sigma ADC. The static error of DAC refers to the feedback 2 in DAC in a multi-bit (B bits) Delta-Sigma ADC ^B -1 DAC sheetThe output size of the element deviates from the standard value to form a sample of 2 ^B -1, as shown in figure 2. This causes the input-output relationship of the DAC to be no longer linear, thereby introducing non-linear distortion in the Delta Sigma ADC. Dynamic error of a DAC refers to the fact that the sum of the output of the DAC and the sum of its digital inputs are no longer linear over a period of time, since the rising and falling edges of the DAC output waveform are not equal. The dynamic error of the DAC can be divided into a linear part, which is calibrated with the static error, and a non-linear part, which is equivalent to the rising edge part. As shown in fig. 3, in the case where the digital input is 1, it is assumed that each non-return-to-zero (NRZ) DAC cell has an output current sum of 1 in one clock cycle; the shaded portion is the error introduced by each non return to zero (NRZ) DAC cell in each 0 → 1 transition, denoted as Δ. The sum of the output currents in the above example is 2- Δ (it should originally output 2, but it undergoes 10 → 1 transition, so a dynamic error- Δ is introduced) due to the presence of the dynamic error; the middle example has a total of 2-2 delta of DAC output current (which should have output 2, but which has undergone 20 → 1 transitions, thus introducing a dynamic error of-2 delta), and the following example has a total of 4-delta of current (which should have output 4, but which has undergone 10 → 1 transition, thus introducing a dynamic error of-delta). It can be seen that the sum of the output currents is related to the order of their digital inputs, as is the case with 2 1's and 2 0's for the digital inputs in 4 clock cycles, the sum of the DAC output currents being 2- Δ in the above example and 2-2 Δ in the middle example. The presence of DAC dynamic errors increases noise in the output spectrum of the analog-to-digital converter and degrades harmonic distortion.

Currently, there are many circuits that use a single-bit DAC or a return-to-zero (RZ) DAC to mitigate the error of the feedback DAC. But single-bit DACs are more sensitive to clock jitter and require higher oversampling rates (OSR) and/or noise shaping orders for the same ADC accuracy requirements, whereas return-to-zero (RZ) DACs require higher slew rates for the amplifiers in the loop filter and are more affected by clock jitter. Therefore, it is very meaningful to study how to effectively and economically solve static and dynamic errors in the case of using a non-return-to-zero (NRZ) DAC.

The invention has proposed a open-loop digital calibration technique used to Delta-Sigma analog-to-digital converter of continuous time, the structure chart is shown in fig. 4, the Delta-Sigma analog-to-digital converter includes the loop filter 1, quantizer 2, feedbacks DAC assembly 3, two-way selector switch 4, benchmark DAC unit 5 and digital processing module (DSP)6, feedbacks DAC assembly 3 includes B feedbacks DAC units paralleled, begin loop filter 1, quantizer 2 and digital processing module 6 to interconnect sequentially from the input end, one end of two-way selector switch 4 connects feedbacks DAC assembly 3, one of two-way of another end connects between quantizer 2 and digital processing module 6, another way connects input sequence S1; the feedback DAC component 3 and the reference DAC cell 5 have opposite polarity to each other, and the other end of the reference DAC cell 5 is connected to the reference sequence S2. The two-way selection switch 4 is inserted between the quantizer 2 and the feedback DAC component 3 and is used for configuring the Delta-Sigma analog-digital converter to be in a normal working state or an open-loop calibration state; the added reference DAC cell 5 may be calibrated sequentially for all feedback DAC cells of the feedback digital-to-analog converter 3 with reference to this reference DAC cell 5. In the case of the same input sequence S1, by inputting two different reference sequences S2, two equations containing static errors and dynamic errors of each feedback DAC cell with respect to the reference DAC cell 5 are obtained, and thus the magnitudes of the static errors and the dynamic errors introduced by each feedback DAC cell can be solved. The digital output of the quantizer 2 is connected to a digital processing module 6, which is used to store the error of each feedback DAC unit and complete some digital operations in the digital calibration process, and finally obtain the calibrated digital output. In a circuit implementation, the digital processing block 6 may be combined with a decimation filter block of a Delta-Sigma analog-to-digital converter. The digital calibration technique can eliminate static and dynamic errors of the feedback DAC at the same time, and does not introduce extra loop delay. In addition, due to the fact that the calibration is digital, besides a reference DAC unit, an extra analog circuit and an extra analog signal are not needed, and the calibration is robust to various non-ideal factors.

Based on the Delta-SigmaThe process of the open-loop digital calibration of the analog-to-digital converter is divided into two steps: first, extract 2 in calibration mode ^B Digital error of 1 feedback DAC cell relative to reference DAC cell 5, including static error E _S1 ，E _S2 ，…，E _Si ，…，E _S(2^B-1) And dynamic error E _D1 ，E _D2 ，…，E _Di ，…，E _D(2^B-1) And these errors are stored in the digital processing module 6. And secondly, correspondingly eliminating the errors in the digital output of the Delta-Sigma ADC in the normal working mode according to the obtained digital errors of the feedback DAC unit to obtain the calibrated ADC digital output.

As shown in fig. 5, is the process by which the error of the ith feedback DAC cell relative to the reference DAC cell is extracted in the calibration mode of the Delta-Sigma analog-to-digital converter. At the moment, the two-way selector switch is connected with the lower port, and the upper port is suspended (namely, the ith feedback DAC unit is connected with the input sequence S1), so that the loop of the traditional closed-loop Delta-Sigma ADC is disconnected, and an open-loop amplified and quantized signal link is formed; while the analog input X of the Delta Sigma ADC is set to zero so that the difference between the analog output of the reference DAC cell and the analog output of the feedback DAC block is the input signal to the loop filter, which is set in the form of a first order integrator H1(s), which accumulates the error. Wherein the digital input of the ith feedback DAC cell is the digital sequence S1 in the figure; the digital input of the reference DAC cell is the digital sequence S2 in the figure, as shown in fig. 6; the digital inputs of the other feedback DAC cells are set to 0. It can be seen that in the first 2N (for convenience, N takes 4 in fig. 6) clock cycle (2N x T) _S ) In this case, the number sequence S1 consists of N "10" combinations, where there are N1 'S and N0' S, and there are N0 → 1 transitions; the number sequence S2 consists of N consecutive 1S and N consecutive 0S, with N1S and N0S, with only 10 → 1 transition. During the second 2N clock cycle, the digital sequence S1 consists of N "10" combinations of N1 'S and N0' S, with N0 → 1 transitions; the number sequence S2 consists of 2 identical sequences of N/2 consecutive 1S and N/2 consecutive 0S, for a total of N1S and N0S, and 20 → 1 transitions. Analog output of reference DAC unit within 2N clock cyclesThe difference between the analog outputs of the ith feedback DAC unit is integrated and amplified by an analog filter H1(s) as an input signal, and then oversampled and quantized by a quantizer (the sampling frequency of the quantizer is F) _S ) The error of the digitized ith feedback DAC unit relative to the reference DAC unit is obtained (i.e., -E is shown in the figure) _i ). Assume the output of the 2N clock cycle quantizer is E _T1 The output of the 4 Nth clock period quantizer is E _T2 The static error of the ith feedback DAC unit relative to the reference DAC unit in each clock cycle is E _Si Dynamic error of E _Di Then, there are:

E _T1 ＝N·E _Si +(N-1)·E _Di

E _T2 ＝N·E _Si +(N-2)·E _Di

solving the equation yields:

E _Di ＝E _T1 -E _T2

according to the same method, static errors and dynamic errors of other feedback DAC units relative to the reference DAC unit can be obtained. In the phase of extracting the error of a certain feedback DAC cell, the digital inputs of other feedback DAC cells are set to zero. Thus, the static error E of all feedback DAC units can be extracted after 4 × N (2^ B-1) clock cycles _S1 ，E _S2 ，…，E _Si ，…，E _S(2^B-1) And dynamic error E _D1 ，E _D2 ，…，E _Di ，…，E _D(2^B-1) 。

FIG. 4 illustrates a circuit configuration in a normal operating mode, with a dual-way selector switch connected to the upper port and the lower port suspended, and a feedback DAC, loop filter, and quantizer forming a normal closed-loop Delta-Sigma ADC; the Delta-Sigma ADC analog input is X; while the digital input of the reference DAC cell is zero.

Suppose the digital output of the Delta-Sigma ADC in the k-th clock cycle is Y _k The digital output in the k-1 clock cycle is Y _k-1 Wherein Y is _k-1 And Y _k Has a value of 0,1,2 … 2 ^B -1 of them. This means that the 1 st, 2 … i … Y clock cycle is the k-th clock cycle _k DAC unit (total Y) _k One DAC unit) is a digital 1, the other Yth _k+1 ，Y _k+2 …2 ^B 1 DAC units (total 2) ^B -1-Y _k DAC cell) input is digital 0; 1,2 … i … Y in the k-1 clock cycle _k-1 DAC unit (total Y) _k-1 One DAC unit) is a digital 1, the other Yth _k-1 +1，Y _k-1 +2…2 ^B -1 DAC units (total 2) ^B -1-Y _k-1 DAC cell) is a digital 0. The sum of the static errors introduced by the feedback DAC during the kth clock cycle is:

the calculation of the dynamic error is more complicated, and needs to be based on Y _k And Y _k-1 The classification and discussion are carried out according to the following formula:

therefore, the errors introduced by the feedback DAC cell during the kth clock cycle include static errors and dynamic errors:

E _total ＝E _Stotal +E _Dtotal

the final digital output Y is (where Q is quantization noise):

the error sum E needs to be eliminated in the DSP _total Obtaining the digital output Y of the calibrated Delta-Sigma ADC _cal ：

Finally, the DSP outputs Y according to the digital output and the error sum E introduced by all the feedback DAC units _total Obtaining a calibrated digital output Y _cal 。

Embodiments of the present invention further provide a computer-readable storage medium, where the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are called and executed by a processor, the computer-executable instructions cause the processor to implement the above-mentioned flow steps of open-loop digital calibration.

The background of the invention may contain background information related to the problem or environment of the present invention rather than the prior art described by others. Accordingly, the inclusion in the background section is not an admission of prior art by the applicant.

The foregoing is a more detailed description of the invention in connection with specific/preferred embodiments and is not intended to limit the practice of the invention to those descriptions. It will be apparent to those skilled in the art that various substitutions and modifications can be made to the described embodiments without departing from the spirit of the invention, and these substitutions and modifications should be considered to fall within the scope of the invention. In the description herein, references to the description of the term "one embodiment," "some embodiments," "preferred embodiments," "an example," "a specific example," or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction. Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the invention as defined by the appended claims.

Claims

1. A digital calibration method of an analog-to-digital converter is characterized by comprising an error extraction step and an error elimination step, wherein:

the analog-to-digital converter comprises a loop filter, a quantizer, a feedback DAC assembly, a two-way selection switch, a reference DAC unit and a digital processing module, wherein the feedback DAC assembly comprises a plurality of feedback DAC units which are connected in parallel, the loop filter, the quantizer and the digital processing module are sequentially connected with one another from an input end to an output end, a first end of the feedback DAC assembly and a first end of the reference DAC unit are respectively connected to the loop filter in opposite polarities, a second end of the feedback DAC assembly is connected with the first end of the two-way selection switch, the first of two ways which can be selected by the second end of the two-way selection switch is connected between the quantizer and the digital processing module, and the second way is connected with a first digital sequence signal; the second end of the reference DAC unit is connected with a second digital sequence signal;

the error extraction step includes:

a3: calculating a static error and a dynamic error of the ith feedback DAC unit relative to the reference DAC unit in each clock period according to the output of the quantizer;

the error elimination step includes:

b3: calculating the error sum introduced by all the feedback DAC units in the current clock period according to the input of all the feedback DAC units in the current clock period;

2. The digital calibration method of claim 1, wherein the error extraction step further comprises setting the loop filter in the form of a first order integrator.

3. The digital calibration method according to claim 1, wherein the first digital sequence signal in step a1 is specifically: in the first 2N clock cycle and the second 2N clock cycle, the first digital sequence signal is composed of N '10' combinations, wherein N is a positive integer.

4. The digital calibration method according to claim 3, wherein the second digital sequence signal in step A2 is specifically: during a first 2N clock cycle, the second digital sequence signal consists of N consecutive 1 s and N consecutive 0 s; during the second 2N clock cycle, the second digital sequence signal consists of 2 identical sequences, each sequence being N/2 consecutive 1's and N/2 consecutive 0's.

5. The digital calibration method according to claim 4, wherein the static error E of the ith feedback DAC unit relative to the reference DAC unit per clock cycle calculated in step A3 _Si And dynamic error E _Di Respectively as follows:

E _Di ＝E _T1 -E _T2

6. The digital calibration method according to any one of claims 3 to 5, wherein N is an even number.

7. The digital calibration method according to claim 1, wherein the error sum E introduced by all the feedback DAC units of the current k-th clock cycle calculated in step B3 _total Comprises the following steps:

E _total ＝E _Stotal +E _Dtotal

wherein E is _Stotal For the sum of the static errors introduced by the feedback DAC components during the kth clock cycle:

8. The digital calibration method of claim 1, wherein the calibrated digital output Y obtained in step B4 _cal Comprises the following steps:

Y _cal ＝Y+E _total

9. A computer-readable storage medium having stored thereon computer-executable instructions that, when invoked and executed by a processor, cause the processor to implement the digital calibration method of any of claims 1 to 8.